NTE74LS107

NTE74LS107 Integrated Circuit TTL − Dual J−K Negative Edge Triggered Flip−Flop with Clear Description: The NTE74LS107 contains two independent negative−edge−triggered flip−flops in a 14−Lead plastic DIP type package. The J and K inputs must be stable one setup prior to the high−to−low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q output high. Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V DC Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C Note 1. Unless otherwise specified, all voltages are referenced to GND. Recommended Operating Conditions: Parameter Symbol Min Typ Max Unit Supply Voltage VCC 4.75 5.0 5.25 V High−Level Input Voltage VIH 2.0 − − V Low−Level Input Voltage VIL − − 0.8 V High−Level Output Current IOH − − −0.4 mA Low−Level Output Current IOL − − 8 mA fclock 0 − 30 MHz 20 − − ns 25 − − ns 20 − − ns 25 − − ns Clock Frequency Pulse Duration CLK High tw CLR Low Setup Time before CLK Data High or Low tsu CLR Inactive Hold Time Data after CLK th 20 − − ns Operating Temperature Range TA 0 − +70 C Electrical Characteristics: (Note 2, Note 3) Parameter Symbol Test Conditions Min Typ Max Unit − − −1.5 V 2.7 3.4 − V Input Clamp Voltage VIK VCC = MIN, II = −18mA High Level Output Voltage VOH VCC = MIN, VIH = 2V, VIL = MAX, IOH = -0.4mA Low Level Output Voltage VOL VCC = MIN, VIH = 2V, VIL = MAX, IOL = 4mA − 0.25 0.4 V VCC = MIN, VIH = 2V, VIL = MAX, IOL = 8mA − 0.35 0.5 V VCC = MAX, VI = 7V − − 0.1 mA CLR − − 0.3 mA CLK − − 0.4 mA − − 20 A CLR − − 60 A CLK − − 80 A − − −0.4 mA − − −0.8 mA Input Current J or K II High Level Input Current J or K IIH Low Level Input Current J or K IIL VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.4V CLK or CLR Short−Circuit Output Current IOS VCC = MAX, Note 4 −20 − −100 mA Supply Current ICC VCC = MAX, Note 5 − 4 6 mA Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended Operation Conditions”. Note 3. All typical values are at VCC = 5V, TA = +25C. Note 4. For certain devices where state commutation can be caused by shorting an output to GND, an equivalent test may be performed with VO = 2.125V and the minimum and maximum limits reduced to one half of their stated values. Note 5. With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded. Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified) Parameter Symbol Maximum Clock Frequency tmax Propagation Delay Time (From CLR or CLK Input to Q or Q Output) Test Conditions RL = 2k, CL = 15pF Min Typ Max Unit 30 45 − MHz − 15 20 ns tPLH, tPHL Truth Table: CLR L H H H H H Inputs CLK X     H J X L H L H X K X L L H H X Outputs Q Q L H Q0 Q0 H L L H Toggle Q0 Q0 Pin Connection Diagram 1J 1 14 VCC 1Q 2 1Q 3 13 1CLR 12 1CLK 1K 4 11 2K 2Q 5 10 2CLR 2Q 6 GND 7 9 2CLK 8 2J 14 8 1 7 .300 (7.62) .785 (19.95) Max .200 (5.08) Max .100 (2.45) .600 (15.24) .099 (2.5) Min