Numonyx™ Wireless Flash Memory (W18 SCSP)
128-Mbit W18 Family with Synchronous PSRAM
Datasheet
Product Features
Device Architecture — Flash Die Density: 32, 64 or 128-Mbit — PSRAM Die Density: 16 or 32-Mbit — x16 Non-Mux or ADMux I/O Interface Option — Bottom or Top Flash Parameter Configuration Device Voltage — Core: VCC = 1.8 V — I/O: VCCQ = 1.8 V Device Packaging — Ballout: QUAD+ (88 Balls) — Area: 8x10 mm — Height: 1.2 mm PSRAM Performance — 70 ns Initial Read Access; 20 ns Asynchronous Page-Mode Read — Up to 66 MHz with 9 ns Clock-to-Data Synchronous Burst-Mode Reads and Writes — Configurable 4-, 8-, 16- and ContinuousWord Burst-Length Reads and Writes — Partial-Array Self and TemperatureCompensated Refresh — Programmable Output Impedance Flash Performance — 60 ns Initial Read Access; 20 ns Asynchronous Page-Mode Read — Up to 66 MHz with 11 ns Clock-to-Data Output Synchronous Burst-Mode Read — Enhanced Factory Programming Modes: 3.1 µs/Word (Typ) Flash Architecture — Read-While-Write/Erase — Asymmetrical blocking structure — 4-KWord parameter blocks (Top or Bottom) — 32-KWord main blocks — 4-Mbit partition size — 128-bit One-Time Programmable (OTP) Protection Register — Zero-latency block locking — Absolute write protection with block lock using F-VPP and F-WP# Flash Software — Numonyx™ FDI, Numonyx™ PSM, and Numonyx™ VFM — Common Flash Interface — Basic and Extended Flash Command Set Quality and Reliability — Extended Temperature –25 °C to +85 °C — Minimum 100K Flash Block Erase cycles — 90 nm ETOX ™ IX Flash Technology — 130 nm ETOX™ VIII Flash Technology
Order Number: 311760-10 November 2007
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Legal L ines and D isc laim er s
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Numonyx B.V., All Rights Reserved.
Datasheet 2
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Contents
1.0 Introduction .............................................................................................................. 6 1.1 Nomenclature ..................................................................................................... 6 1.2 Acronyms........................................................................................................... 7 1.3 Conventions ....................................................................................................... 7 Functional Overview .................................................................................................. 8 2.1 Product Description ............................................................................................. 8 2.2 Device Combinations ........................................................................................... 9 2.3 Device Operation Overview................................................................................. 10 2.3.1 Flash and Synchronous PSRAM Bus Operations........................................... 10 2.3.2 Flash Configuration Operation .................................................................. 11 2.3.3 Flash Memory Map and Partitioning........................................................... 11 Device Package Information .................................................................................... 12 Ballout and Signal Descriptions ............................................................................... 13 4.1 Device Signal Ballout ......................................................................................... 13 4.2 Signal Descriptions ............................................................................................ 14 Maximum Ratings and Operating Conditions ............................................................ 16 5.1 Device Absolute Maximum Ratings....................................................................... 16 5.2 Device Operating Conditions ............................................................................... 17 Device Electrical Specifications ................................................................................ 17 6.1 Flash DC Characteristics ..................................................................................... 17 6.2 Synchronous PSRAM DC Characteristics................................................................ 17 6.3 Device AC Test Conditions .................................................................................. 19 6.3.1 Flash Die Capacitance ............................................................................. 19 6.3.2 Synchronous PSRAM Die Capacitance ........................................................ 19 Device AC Characteristics ........................................................................................ 19 7.1 Flash AC Characteristics ..................................................................................... 19 7.2 PSRAM Asynchronous Read................................................................................. 19 7.3 PSRAM Asynchronous Write ................................................................................ 23 7.4 PSRAM Synchronous Read and Write.................................................................... 26 Device Bus Interface ............................................................................................... 31 8.1 PSRAM Reads ................................................................................................... 31 8.1.1 PSRAM Asynchronous Read...................................................................... 31 8.1.2 PSRAM Asynchronous Page-Mode Read ..................................................... 32 8.1.3 PSRAM Synchronous Burst-Mode Reads..................................................... 32 8.1.4 PSRAM Asynchronous Fetch Control Register Read ...................................... 32 8.2 PSRAM Writes ................................................................................................... 33 8.2.1 PSRAM Asynchronous Write ..................................................................... 33 8.2.2 PSRAM Synchronous Write....................................................................... 33 8.2.3 PSRAM Asynchronous Set Control Register Write ........................................ 34 8.2.4 PSRAM Synchronous Set Control Register Write.......................................... 34 8.3 PSRAM No Operation Command .......................................................................... 34 8.4 PSRAM Deselect ................................................................................................ 35 8.5 PSRAM Deep Power Down................................................................................... 35 8.6 PSRAM WAIT Signal........................................................................................... 35 Device Operations ................................................................................................... 37 9.1 Device Power-Up/Down...................................................................................... 37 9.1.1 Flash Power and Reset Specifications ........................................................ 37
2.0
3.0 4.0
5.0
6.0
7.0
8.0
9.0
November 2007 Order Number: 311760-10
Datasheet 3
128-Mbit W18 Family with Synchronous PSRAM
9.2 9.3 9.4
9.5 9.6
9.7
9.1.2 PSRAM PSRAM 9.3.1 9.3.2 PSRAM 9.4.1 9.4.2 9.4.3 PSRAM 9.5.1 PSRAM 9.6.1 9.6.2 9.6.3 PSRAM
PSRAM Power-Up Sequence and Initialization .............................................37 Operating Modes .....................................................................................37 Control Registers ....................................................................................38 PSRAM Bus Control Register .....................................................................38 PSRAM Refresh Control Register ...............................................................42 Access to Control Register ........................................................................45 PSRAM Hardware Control Register Access ..................................................45 PSRAM Software Register Access ..............................................................45 Cautionary Note About Software Register Access.........................................46 Self-Refresh Operation.............................................................................47 PSRAM Self-Refresh Operations at Low Frequency .......................................47 Burst Suspend, Interrupt, or Termination ...................................................47 PSRAM Burst Suspend .............................................................................47 PSRAM Burst Interrupt ............................................................................48 PSRAM Burst Termination ........................................................................49 Row Boundary Crossing ...........................................................................49
10.0 Additional Information .............................................................................................50 11.0 Ordering Information ...............................................................................................51
Datasheet 4
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Revision History
Date February 2006 Revision 001 Initial release • March 2006 002 • • • • Corrected flash and PSRAM specification of CLK from 66 MHz to 54 MHz, and flash burst-mode read timing from 11 ns to 14 ns. Remove Page-Mode Read details for flash and PSRAM, feature not supported. Changed tCLK3 Min value in Section 11, “PSRAM AC Characteristics—Asynchronous Read” on page 21 from 15 ns to 18 ns to correlate CLK value change. Updated Ordering Information Table. Added ADMux I/O interface flash references, making document inclusive of Non-Mux and ADMux I/O flash interface WQ product family, superseding 64-Mbit WQ Family with Synchronous PSRAM datasheet #311641. Updated PSRAM burst-mode improved read timing from 14 ns to 9 ns. Added 16 Mbit PSRAM AC/DC specifications that was TBD in revision -002. Update various descriptions of the W18 and PSRAM features, specifications and operations for clarity. Made miscellaneous edits and formatting changes. Added 90 nm device option. Revised datasheet to show improved CLK from 54 MHz to 66 MHz for Non Mux and AD Mux products. Revised datasheet to show improved flash burst mode read timing from 14 ns to 11 ns. Revised ordering information to add non-muxed line items Added section for configuring device in asynchronous mode. Revised typos in Ordering infomation: Changed AD-Mux to Non-Mux. Added LIs PF38F2030W0YTQE and PF38F2040W0YCQE. Updated ordering information Applied Numonyx branding. Description
May 2006
003
• •
July 2006 August 2006 November 2006 January 2007 July 2007 August 2007 November 2007
004 005 006
• • • •
007 008 009 10
• •
• •
November 2007 Order Number: 311760-10
Datasheet 5
128-Mbit W18 Family with Synchronous PSRAM
1.0
Introduction
The 128-Mbit Numonyx™ Wireless Flash memory with synchronous PSRAM stacked device family offers multiple high-performance solutions. The W18 (Non-Mux or AD Mux I/O interface option) highlighted features like asymmetrical block array, configurable burst lengths, security using OTP and zero-latency block lock. The W18 delivers up to 66 MHz synchronous burst and page-mode read rates with multipartitioning Read-While-Write and Read-While-Erase operations. The synchronous PSRAM (Non-Mux and AD-Mux I/O interface) is a high-performance volatile memory operating at speeds up to 66 MHz with configurable burst lengths. The PSRAM lower sixteen addresses can be routed to the data pins on the PCB board to enable a flexible flash and PSRAM A/D-Mux I/O interface device design. The W18 stacked device features 1.8 volt low-voltage operation in an Numonyx™ QUAD+ standard footprint and signal ballouts. This document contains information pertaining to the 128-Mbit Title stacked device family. The W18 is available as a Non-Multiplex or Address-Data Muxltiplex (ADMux) I/ O interface option, while the synchronous PSRAM is available only as a Non-Multiplex I/ O interface. The intent of this document is to provide information where this product differs from the Intel® Wireless Flash Memory (W18) device. Refer to the latest revision of the Intel® Wireless Flash Memory (W18) Discrete Datasheet (order number: Non-Mux I/O doc #290701 and ADMux I/O doc #313272) for specific flash product details not included in this document.
1.1
Nomenclature
1.8 Volt Core 1.8 Volt I/O ADMux I/O Asserted Block Deasserted Device Die High-Z Low-Z Non-Array Reads Non-Mux I/O Partition Program Write
VCC (memory subsystem die core) voltage range of 1.7 V – 1.95 V. VCCQ (memory subsystem I/O) voltage range of 1.7 V – 1.95 V. Address-Data Multiplex I/O interface, where the lower sixteen (16) addresses are multiplexed on the data pins (DQ[15:0]) during any address cycle. Signal with logical voltage level VIL, or enabled. Group of cells, bits, bytes, or words within the flash memory array that get erased with one erase instruction. Signal with logical voltage level VIH or disabled. A specific memory type or stacked flash and xRAM memory density configuration combination within a memory subsystem product family. Individual flash or xRAM die used in a stacked package memory device. High Impedance. Signal is Driven on the bus. Flash reads which return flash Device Identifier, CFI Query, Protection Register, and Status Register information. Traditional parallel flash interface where address are not multiplex onto the data pins. All address and data pins are unique. A group of flash blocks that shares common status register read state. An operation to Write data to the flash array or xRAM. Bus cycle operation at the inputs of the flash or xRAM die, in which a command or data are sent to the flash array or xRAM.
Datasheet 6
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
1.2
Acronyms
APS EFA BCR Buffered EFP CR CSP MLC OTP PLR PR RCR RFU RWW / RWE SR WSM
Automatic Power Savings Extended Flash Array (PSRAM) Bus Control Register Buffered Enhanced Factory Programming (Flash) Configuration Register Chip Scale Package Multi-Level Cell One-Time Programmable Protection Lock Register Protection Register (PSRAM) Refresh Control Register Reserved for Future Use Read-While-Write / Read-While-Erase Status Register Write State Machine
1.3
Conventions
A5 Clear DQ[15:0] F-CE# P-CE# or P-CS#
Denotes one element of a signal group, in this case address bit 5. Logical zero (0). Denotes a group of similarly named signals, such as data bus. Denotes Chip Enable of the flash die, where “F” to denote the specific signal suffix and “CE#” is the root signal name of the NOR flash die. Denotes Chip Enable of the PSRAM die, where “P” to denote the specific signal suffix and “CE# or CS#” are the root signal name of the PSRAM die. PSRAM CE# and CS# is used interchangably throughout the document. Denotes Chip Enable of the SRAM die, where “S” to denote the specific signal suffix and “CS1#” is the root signal name of the SRAM die. Logical one (1). A flash status register bit, in this case status register bit 4 of SR[15:0]. Signal or voltage connection. Signal or voltage level. Denotes a global power signal of the stacked device. VSS is common to all memory dies within a stacked memory device.
S-CS1# Set SR4 VCC VCC VSS
November 2007 Order Number: 311760-10
Datasheet 7
128-Mbit W18 Family with Synchronous PSRAM
2.0
2.1
Functional Overview
Product Description
The W18 family with synchronous PSRAM stacked product family encompasses multiple W18 flash memory plus synchronous PSRAM die combinations. Figure 1 shows the maximum configuration options for W18 non-multiplex I/O (standard) product and Figure 2 shows the maximum configuration options for W18 AD-Multiplex I/O product family with synchronous PSRAM internal package connections.
Note:
See detailed signal information in Section 4.2, “Signal Descriptions” on page 14.
Figure 1:
W18 Product Family with Sync PSRAM Block Diagram
W18 Family with Sync PSRAM
F1-CE# F1-OE# CLK WAIT ADV# F-WP# F-WE# VSS VCCQ F-VPP F1-VCC
Flash Die 128-Mbit, 64-Mbit, or 32-Mbit
F-RST#
A[MAX:0]
DQ[15:0] P-CS# R-OE# P-CRE R-LB# R-WE#
PSRAM Die 32-Mbit or 16-Mbit
P-VCC R-UB#
Notes: 1. F2-OE# must be treated as RFU. However, for future product compatiblity, F2-OE# can be tied to F1-OE# or left floated. 2. F2-VCC must be treated as RFU. However, for future product compatibility, F2-VCC can be tied to F1-VCC or left floated.
Note:
See detailed signal information in Section 4.2, “Signal Descriptions” on page 14.
Datasheet 8
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Figure 2:
W18 ADMux I/O Interface Product Family with Sync PSRAM Block Diagram
W18 ADMux Family with Sync PSRAM
F1-CE# F1-OE# CLK WAIT ADV# F-WP# F-WE# F-VPP F1-VCC
Flash Die 128-Mbit, 64-Mbit, or 32-Mbit
(Address/Data Multiplex I/O)
A/DQ[15:0]
F-RST#
VCCQ
A[MAX:16]
VSS
A[MAX:0]
DQ[15:0] P-CS# R-OE# P-CRE R-LB# R-WE#
PSRAM Die 32-Mbit or 16-Mbit
(Non-Multiplex I/O)
P-VCC R-UB#
Notes: 1. F2-OE# must be treated as RFU. However, for future product compatiblity, F2-OE# can be tied to F1-OE# or left floated. 2. F2-VCC must be treated as RFU. However, for future product compatibility, F2-VCC can be tied to F1-VCC or left floated.
2.2
Note:
Device Combinations
For combination not listed, contact your local Numonyx Sales Representative for details.
Table 1:
I/O Voltage
Device Combinations
Flash Type (Mbit) 64 W18 xRAM Type (Mbit) 32 Sync PSRAM 16 Sync PSRAM 16 Sync PSRAM 32 Sync PSRAM Package Size (mm) 8x10x1.2 8x10x1.2 8x10x1.2 8x10x1.2 Package Ballout QUAD+ QUAD+ QUAD+ QUAD+
1.8 V
32 W18 (ADMux I/O) 64 W18 (ADMux I/O) 64 W18 (ADMux I/O)
November 2007 Order Number: 311760-10
Datasheet 9
128-Mbit W18 Family with Synchronous PSRAM
2.3
Device Operation Overview
The following sections describes the bus operations and device state between the flash and synchronous PSRAM.
2.3.1
Flash and Synchronous PSRAM Bus Operations
Bus operations for the W18 stacked device involve the control of flash and PRAM inputs. The bus operations are shown in Table 2.
Note:
See the Intel® Wireless Flash Memory (W18) Discrete Datasheet (order number: NonMux I/O doc #290701 and ADMux I/O doc #313272) for complete descriptions of the flash modes and commands, command bus-cycle definitions, and flowcharts that illustrate operational routines not documented in this Datasheet. Flash and PSRAM Device Bus Operations
P-CRE# F-RST# R-UB#, R-LB# R-WE# F-WE# ADV#8 R-OE# F-OE# P-CS# F-CE# F-VPP Mode DQ[15:0] WAIT7 Notes
Table 2:
Device
Flash (#1, #2, #3, or #4)
Synchronous Array and NonArray Read Asynchronous Read Write Output Disable Standby Reset Read
H
L
L
H
L
X
X
H
X
X
X
Flash DOUT Flash DOUT Flash DIN Flash High-Z
Active
1,2,4
H H H H L X X
L L L H X H H
L H H X X X X
H L H X X X X
X L X X X X X
X VPPL or VPPH X X X X X
X X
H H
X X
X X
X X
Deasserted Deasserted Flash High-Z Flash High-Z Flash High-Z Active Active PSRAM High-Z PSRAM High-Z PSRAM High-Z
1,2,4 1,2,3 1,2 1,2 1,2 1,2,5,7 1,2,5,7 1,2 1,2 1,2
Any PSRAM mode allowed
Flash High-Z Flash High-Z
L L L
L L L H X
L H H X X
H L H X X
L L X X X
PSRAM (#1 or #2)
PSRAM DOUT PSRAM DIN PSRAM High-Z PSRAM High-Z PSRAM High-Z
Write Output Disable Standby Low Power Mode
Any Flash mode allowed
L X
Notes: 1. For flash, do not simultaneously assert F-OE# and F-WE#. For PSRAM, do not simultaneously assert R-OE# and R-WE#. 2. X can be VIL or VIH for flash or xRAM inputs; VPPLK , VPPL,or VPPH for F-VPP. 3. Refer to the latest revision of the Intel® Wireless Flash Memory (W18) Datasheet (order number: Non-Mux I/O doc #290701 and ADMux I/O doc #313272) for valid DIN during Flash writes. 4. Flash CFI query and Status Register accesses, use DQ[7:0] only. All other reads use DQ[15:0]. 5. P-CRE# is low if PSRAM is in standby. P-CRE# is X if PSRAM is in Low-Power mode. See Section 9.0, “Device Operations” on page 37 for more details about Standby and Low Power mode. 6. WAIT indicates data validity only when in Synchronous mode. Ignore this setting in Asynchronous and Page-mode. 7. The Flash and Synchronous PSRAM dies share the WAIT signal. 8. During AD-Mux I/O operation, ADV# must remain deasserted during the data phase.
Datasheet 10
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Table 3:
State Read Write Set Control Register Fetch Control Register No Operation
PSRAM Bus Operation
Operation Modes Asynchronous Asynchronous NOR-Flash Asynchronous NOR-Flash Asynchronous Asynchronous Synchronous NOR-Flash Asynchronous Synchronous NOR-Flash Asynchronous Synchronous NOR-Flash Synchronous NOR-Flash Synchronous NOR-Flash Synchronous Synchronous Synchronous Power Mode Active Active Active CLK L L L PCS# L L L ADV# L L L RWE# H L L ROE# L X H R-UB# R-LB# L L X PCRE L L H A19/ Addr. A18 V V LL HL LL HL LH X V V RCR BCR X DQ DOUT DIN X RCR BCR DIDR High-Z 3 1,2 Notes
Active
L
L
L
H
L
L
H
Standby /Active
L
L
H
H
H
X
L
X
Deselect
Standby
L
H
X
X
X
X
X
X
X
High-Z
Deep Power Down Burst Init Read Burst Read Burst Init Write Burst Write Set Control Register Fetch Control Register
Deep Power Down Active Active Active Active Active
L
H
X
X
X
X
X
X
X
High-Z
L->H L->H L->H L->H L->H
L L L L L
L H L H L
H X L X L
X L H X H
L L X L X
L X L X H
V X V X LL HL LL HL LH
V X V X RCR BCR X
X DOUT X DIN X RCR BCR DIDR
4 4,5 4 4 4
Synchronous
Active
L->H
L
L
H
L
L
H
4,6
Notes: 1. The table reflects behavior if R-UB# and R-LB# are asserted low. If only either of the signals, R-UB# or R-LB# is asserted low only the corresponding data byte will be written (UB# enables DQ15-DQ8, LB# enables DQ7-DQ0). 2. During a write access invoked by R-WE# set to low the R-OE# signal is ignored. 3. Power mode of Standby or Active will depend on the internal operation of device at the time. 4. Clock configuration is rising edge. 5. Output drivers are controlled by the asynchronous R-OE# control signal. 6. During the initial command cycle R-OE# is don’t care (X) and subsequent cycles it must be low (L)
2.3.2
Flash Configuration Operation
Refer to the Intel® Wireless Flash Memory (W18) Datasheet (order number: Non-Mux I/O doc #290701 and ADMux I/O doc #313272) for configuration operation detailed information.
2.3.3
Flash Memory Map and Partitioning
Refer to the Intel® Wireless Flash Memory (W18) Datasheet (order number: Non-Mux I/O doc #290701 and ADMux I/O doc #313272) for the memory map and partitioning information.
§
November 2007 Order Number: 311760-10
Datasheet 11
128-Mbit W18 Family with Synchronous PSRAM
3.0
Figure 3:
Device Package Information
Mechanical Specifications for QUAD+ Ballout Package (8x10x1.2 mm)
A1 Index Mark
1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M D A B C D E F G H J K L M b E e S1
Top View - Ball Down
A2 A1
Bottom View - Ball Up
A
Y
Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D
Note:
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.200 0.325 9.900 7.900
Millimeters Nom Max 1.200 0.860 0.375 10.000 8.000 0.800 88 1.200 0.600
Notes
Min 0.0079
Inches Nom
Max 0.0472
0.425 10.100 8.100
0.0128 0.3898 0.3110
0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236
0.0167 0.3976 0.3189
1.100 0.500
0.100 1.300 0.700
0.0433 0.0197
0.0039 0.0512 0.0276
For mechanical drawings not shown in this document, contact your local Numonyx Sales representative for additional details.
Datasheet 12
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
4.0
4.1
Figure 4:
Ballout and Signal Descriptions
Device Signal Ballout
QUAD+ Ballout
Pin 1
1 2 3 4 5 6 7 8
A
DU
DU
DU
DU
A
B
A4
A18
A19
VSS
F1-VCC
F2-VCC
A21
A11
B
C
A5
R-LB#
A23
VSS
S-CS2
CLK
A22
A12
C
D
A3
A17
A24
F-VPP
R-WE#
P1-CS#
A9
A13
D
E
A2
A7
A25
F-WP#
ADV#
A20
A10
A15
E
F
A1
A6
R-UB#
F-RST#
F-WE#
A8
A14
A16
F
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
F2-CE#
G
H
R-OE#
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
F2-OE#
H
J
S-CS1#
F1-OE#
DQ9
DQ11
DQ4
DQ6
DQ15
VCCQ
J
K
F1-CE#
P2-CS#
F3-CE#
S-VCC
P-VCC
F2-VCC
VCCQ
P-Mode# / P-CRE
K
L
VSS
VSS
VCCQ
F1-VCC
VSS
VSS
VSS
VSS
L
M
DU
DU
DU
DU
M
1
2
3
4
5
6
7
8
Top View - Ball Side Down
Legend: Active Signals De-Populated Balls Do Not Use
Note:
See Figure 1, “W18 connections details.
Product Family with Sync PSRAM Block Diagram” on page 8 for electrical
November 2007 Order Number: 311760-10
Datasheet 13
128-Mbit W18 Family with Synchronous PSRAM
4.2
Table 4:
Symbol
Signal Descriptions
Signal Descriptions (Sheet 1 of 3)
Type Signal Descriptions Note s
Address and Data Signals, Non-Mux ADDRESS: Global device signals. Shared address inputs for all memory die during Read and Write operations. • 128-Mbit: AMAX = A22 • 64-Mbit: AMAX = A21 • 32-Mbit: AMAX = A20 • 16-Mbit: AMAX = A19 • A0 is the lowest-order word address. • Unused address inputs should be treated as RFU. Note: During AD-Mux I/O operation, W18 A[MAX:16] can be treated as a NC pins, but CL will exist on the pins.
A[MAX:0]
Input
1
DQ[15:0]
Input / Output
DATA INPUT/OUTPUTS: Global device signals. Inputs data and commands during Write cycles, outputs data during Read cycles. Data signals are High-Z when the device is deselected or its output is disabled.
Address and Data Signals, AD-Mux ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux I/O flash signals. During AD-Mux Read cycles, DQ[15:0] are used to input the lower address followed by read-data output. During AD-Mux Write cycles, DQ[15:0] are used to input the lower address followed by commands or data. • DQ[15:0] are High-Z when the device is deselected or its output is disabled. • DQ[15:0] is only used with AD-Mux I/O flash device.
DQ[15:0]
Input / Output
1
Control Signals ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input. During a synchronous read operation, the address is latched on the rising edge of ADV# or on the next valid CLK edge with ADV# low, whichever occurs first. • In an asynchronous flash read operation, the address is latched on the rising edge of ADV#, or continuously flows through while ADV# is low. • During a synchronous flash Read operation, the address is latched on the rising edge of ADV# or the first active CLK edge whichever occurs first. . • During synchronous PSRAM read and synchronous write modes, the address is either latched on the first rising clock edge after ADV# assertion or on the rising edge of ADV# whichever edge occurs first. In asynchronous read and asynchronous write modes, ADV# can be used to latch the address, but can be held low for the entire operation as well. Note: During AD-Mux I/O operation, ADV# must remain deasserted during the data phase.
ADV#
Input
F[3:1]CE#
Input
FLASH CHIP ENABLE: Flash-specific signal; low-true input. When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT outputs are placed in a High-Z state. • F1-CE# is dedicated to flash die #1. • F[3:2]-CE# are dedicated to flash die #3 through #2, respectively, if present. Otherwise, any unused flash chip enable should be treated as RFU. CLOCK: Flash- and Synchronous PSRAM-specific input signal. CLK synchronizes the flash and/or synchronous PSRAM with the system clock during synchronous operations. FLASH OUTPUT ENABLE: Flash-specific signal; low-true input. When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE# disables the output drivers of the selected flash die and places the output drivers in High-Z. • F2-OE# common to all other flash dies, if present. Otherwise it is an RFU, however, it is highly recommended to always common F1-OE# and F2-OE# on the PCB.
CLK
Input
F[2:1]OE#
Input
Datasheet 14
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Table 4:
Symbol
Signal Descriptions (Sheet 2 of 3)
Type Signal Descriptions RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input. When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE# disables the output drivers of the selected memory die and places the output drivers in High-Z if present. Otherwise it is an RFU. FLASH RESET: Flash-specific signal; low-true input. When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables normal operation. WAIT: Flash- and Synchronous PSRAM-specific signal; configurable true-level output. When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid output data. • WAIT is driven whenever the flash or the synchronous PSRAM is selected and its output enable is low. • WAIT is High-Z whenever flash or the synchronous PSRAM is deselected, or its output enable is high. • Flash and PSRAM must configure the WAIT RCR bit to be the same true-level state. FLASH WRITE ENABLE: Flash-specific signal; low-true input. When low, F-WE# enables Write operations for the enabled flash die. Address and data are latched on the rising edge of F-WE#. RAM WRITE ENABLE: PSRAM- and SRAM-specific signal; low-true input. When low, R-WE# enables Write operations for the selected memory die. Data is latched on the rising edge of R-WE# if present. Otherwise it is an RFU. FLASH WRITE PROTECT: Flash-specific signals; low-true inputs. When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the LockDown function, enabling locked-down blocks to be unlocked with the Unlock command. PSRAM CONTROL REGISTER ENABLE: Synchronous PSRAM-specific signal; high-true input. When high, P-CRE enables access to the PSRAM Refresh Control Register (P-RCR) or Bus Control Register (P-BCR). When low, P-CRE enables normal Read or Write operations if present. Otherwise it is an RFU. PSRAM MODE#: Asynchronous only PSRAM-specific signal; low-true input. When low, P-MODE# enables access to the PSRAM configuration register, and to enter or exit LowPower mode. When high, P-MODE# enables normal Read or Write operations if present. Otherwise it is an RFU. PSRAM CHIP SELECT: PSRAM-specific signal; low-true input. When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT outputs are placed in a High-Z state. • P1-CS# is dedicated to PSRAM die #1 if present. Otherwise it is an RFU. • P2-CS# is dedicated to PSRAM die #2 if present. Otherwise it is an RFU. SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input. When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or S-CS2 is deasserted, the SRAM die is deselected. • S-CS1# and S-CS2 are dedicated to SRAM if present. Otherwise it is an RFU. RAM UPPER/LOWER BYTE ENABLES: PSRAM- and SRAM-specific signals; low-true inputs. When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read and Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0] if present. Otherwise it is an RFU. 3 Note s
R-OE#
Input
3
F-RST#
Input
WAIT
Output
F-WE#
Input
R-WE#
Input
F-WP#
Input
P-CRE
Input
2
P-MODE#
Input
2
P[2:1]CS#
Input
3
S-CS1# S-CS2
Input
3
R-UB# R-LB#
Input
3
Power Signals F-VPP F[2:1]VCC Power FLASH PROGRAM/ERASE VOLTAGE: Flash specific. F-VPP supplies program or erase power to the flash die. FLASH CORE POWER SUPPLY: Flash specific. • F[2:1]-VCC supplies the core power to the flash dies. • F2-VCC is recommended to be tied to F1-VCC, else it is an RFU.
Power
November 2007 Order Number: 311760-10
Datasheet 15
128-Mbit W18 Family with Synchronous PSRAM
Table 4:
Symbol VCCQ P-VCC S-VCC VSS
Signal Descriptions (Sheet 3 of 3)
Type Power Power Power Groun d — Signal Descriptions I/O POWER SUPPLY: Global device I/O power. VCCQ supplies the device input/output driver voltage. PSRAM CORE POWER SUPPLY: PSRAM specific. P-VCC supplies the core power to the PSRAM die if present. Otherwise it is an RFU. SRAM POWER SUPPLY: SRAM specific. S-VCC supplies the core power to the SRAM die if present. Otherwise it is an RFU. DEVICE GROUND: Global ground reference for all signals and power supplies. Connect all VSS balls to system ground. Do not float any VSS connections. DO NOT USE: This ball should not be connected to any power supplies, signals, or other balls. This ball can be left floating. RESERVED for FUTURE USE: Reserved by Numonyx for future device functionality and enhancement. This ball must be left floating. 3 3 Note s
DU
RFU
—
Notes: 1. Only used when AD-Mux I/O flash is present 2. P-CRE and P-Mode share the same package ball location. Only one signal function is available, depending on the stacked device combination. 3. Only available on stacked device combinations with PSRAM, and/or SRAM die. Otherwise, it should be treated as RFU.
5.0
5.1
Warning: Table 5:
Parameter
Maximum Ratings and Operating Conditions
Device Absolute Maximum Ratings
Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Device Absolute Maximum Ratings
Min –25 –55 –0.2 –0.2 –0.2 –0.2 — Max +85 +125 +2.1 +2.45 +2.45 +13.1 +50 Unit °C °C V V V V mA 1,3 1,2 1,3 1,4 5 Notes
Device Case Temperature Under Bias Storage Temperature Voltage On Any Signal (Except for F-VCC, F-VPP, P-VCC, VCCQ, and S-VCC) F-VCC Voltage VCCQ, P-VCC, and Optional S-VCC Voltage F-VPP Voltage ISH (Output Short Circuit Current)
Notes: 1. Voltage is referenced to VSS. 2. During power transitions, minimum DC voltage may undershoot to –2.0 V for periods < 20 ns; maximum DC voltage may overshoot to VCC (operating max) + 2.0 V for periods < 20 ns. 3. During power transitions, minimum DC voltage may undershoot to –1.0 V for periods < 20 ns; maximum DC voltage may overshoot to VCCQ (operating max) + 1.0 V for periods < 20 ns. 4. During power transitions, minimum DC voltage may undershoot to –2.0 V for periods < 20 ns; maximum DC voltage may overshoot to VPPH (operating max) + 2.0 V for periods < 20 ns. 5. Output shorted for no more than one second. No more than one output shorted at a time.
Datasheet 16
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
5.2
Warning: Table 6:
Device Operating Conditions
Operation beyond the Operating Conditions is not recommended and extended exposure may affect device reliability. Device Operating Conditions
Parameter Test Condition — — — — — VPP = VCC VPP = VPPH Flash + xRAM Unit Min –25 +1.7 +1.7 –0.9 +11.4 100,000 — Max +85 +1.95 +1.95 +1.95 +12.6 — 1000 °C V V V V Cycles Cycles
Symbol
TC F-V CC V CCQ, P-VCC, S-V CC V PPL V PPH Block Erase Cycles Note:
Device Case Operating Temperature Flash Supply Voltage Flash and PSRAM I/O Voltage PSRAM and SRAM Supply Voltage F-VPP (Flash Programming Voltage Supply, Logic Level) F-VPP (Flash Factory Word Programming Voltage Supply) Flash Main Array and EFA Blocks
In typical operation, the F-VPP program voltage is VPPL. F-VPP can be connected to 11.4 V - 12.6 V for a maximum of 80 cumulative hours or 1000 cycles on the main array blocks.
6.0
Device Electrical Specifications
The DC current and voltage characteristics referenced in this document are for individual memory die types within the SCSP device. The total current for each parameter is determined by sum of the current for each memory die type specification within the SCSP device. NOTICE: Individual DC Characteristics of all dies in a SCSP device must be considered accordingly, depending on the SCSP device stacked combinations and operations.
6.1
Flash DC Characteristics
Refer to the Intel® Wireless Flash Memory (W18) Datasheet (order number: Non-Mux I/O doc #290701 and ADMux I/O doc #313272) for flash DC characteristics.
6.2
Synchronous PSRAM DC Characteristics
Synchronous PSRAM DC characteristics are shown in Table 7 and Table 8.
Table 7:
Parameter VCC VCCQ VIH
PSRAM DC Characteristics (Sheet 1 of 2)
Description Supply Voltage range I/O Supply Voltage range Input High Voltage Test Conditions — — — Density Min 1.7 1.7 VCCQ - 0.4 Typ 1.8 1.8 — Max 1.95 1.95 VCCQ + 0.2 Unit V V V 1 Notes
November 2007 Order Number: 311760-10
Datasheet 17
128-Mbit W18 Family with Synchronous PSRAM
Table 7:
VIL VOH VOL IIL IOL ICC1
PSRAM DC Characteristics (Sheet 2 of 2)
Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Async Random Read/Write @ TRCMin — IOH = -0.2 mA IOL = 0.2 mA — — VIN = VCC or VSS; IOUT = 0 VIN = VCC or VSS; IOUT = 0 VIN = VCC or VSS; IOUT = 0 VIN = VCC or VSS; IOUT = 0 VIN = VCC or VSS; IOUT = 0 VIN = VCC or VSS; P-CS# = Deselected VIN = VCC or VSS; P-CS# = Deselected 16Mb 32Mb 16Mb 32Mb 16Mb 32Mb 16Mb 32Mb 16Mb 32Mb 16Mb 32Mb 16Mb 32Mb -0.2 0.8 x VCCQ — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0.4 — 0.2 x VCCQ 1 1 20 20 15 15 25 25 25 35 30 35 80 110 70 70 V V V μA μA mA
ICC1P
Async Page Read
mA
ICC4R
Synchronous Burst Read (continuous)
mA
ICC4W
Synchronous Burst Write (continuous)
mA
ICC5
Burst Initial Access Standby Current (Full Array Refresh) Deep Power-Down
mA
ICC2
μA
ICC3
μA
Note:
To avoid unnecessary current flow, VCCQ is not allowed to be outside of P-VCC ± 0.2 V except during power-up situation.
Table 8:
Density
PSRAM Partial-Array Self-Refresh (Typical) Current
Active Array Full 1/2 Typical Standby Current (μA) 85 oC 50 40 35 35 30 70 60 55 50 40 70 oC 45 35 35 35 25 65 55 50 45 35 45 oC 40 30 30 30 25 50 45 40 40 30 15 oC 35 25 25 25 20 45 40 35 35 25
16-Mbit
1/4 1/8 0 Full 1/2
32-Mbit
1/4 1/8 0
Note:
On-chip temperature sensor is used for temperature-compensated self-refresh, therefore the standby current values at 70, 45 and 15 °C are for reference only.
Datasheet 18
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
6.3
Figure 5:
Device AC Test Conditions
Device Transient Equivalent Testing Load Circuit
I/O O u tp u t
ZO = 50 Ohm s
50 Ohm s V C C Q /2
CL = 30pf
Notes: 1. Test configuration component value for worst case speed conditions. 2. CL includes jig capacitance.
6.3.1
Table 9:
Symbol CIN COUT Note:
Flash Die Capacitance
W18 Individual Die Capacitance
Parameter Input Capacitance (Address, CLK, F-CE#, F-OE#, ADV#, WE#, F-WP#) Output Capacitance (Data and WAIT) Min 6 6 Max 8 8 Unit pF pF Condition VIN = 0.0 V to 1.8 V VOUT = 0.0 V to 1.8 V
Sampled, not 100% tested. TC = 25 °C, f = 1 MHz.
6.3.2
Synchronous PSRAM Die Capacitance
Table 10: Synchronous PSRAM Individual Die Capacitance
Symbol CIN COUT CI/O Note: Parameter Input Capacitance (Address, CLK, P-CS#, R-OE#, ADV#, WE#, R-UB#, R-LB#) Output Capacitance (WAIT) Input/Output Capacitance (DQ) Sampled, not 100% tested. TC = 25 °C, f = 1 MHz. Min — — — Max 6.5 6.5 6.5 Unit pF pF pF Condition VIN = 0.0 V VOUT = 0.0 V VOUT = 0.0 V
7.0
7.1
Note:
Device AC Characteristics
Flash AC Characteristics
Refer to the Numonyx™ Wireless Flash Memory Datasheet for detailed flash die information.
7.2
Note:
PSRAM Asynchronous Read
All PSRAM AC characteristic timing parameters are measured with the default output drive strength (half drive strength).
November 2007 Order Number: 311760-10
Datasheet 19
128-Mbit W18 Family with Synchronous PSRAM
Table 11: PSRAM AC Characteristics—Asynchronous Read
Symbol tRC tAA tAADV tPC tPAA tAVH tAVS tCVS tOH tCO tBA tOE tCSL tLZ tHZ tBLZ tBHZ tOLZ tOHZ tVP tVPH tCPH tCRES tASKEW tASKEWP Notes: 1. 2. 3. 4. 5. Read Cycle Time Address Access Time ADV# Access Time Page Address Cycle Time Page Address Access Time Address Hold from ADV# High Address Setup to ADV# High CE# Low to ADV# High Output Hold from Address Change CE# Access Time UB#, LB# Access Time OE# to Valid Output Data CE# Pulse Width Low Time CE# Low to Output Low-Z CE# High to Output High-Z UB#, LB# Low to Output Low-Z UB#, LB# High to Output High-Z OE# Low to Output Low-Z OE# High to Output HIgh-Z ADV# Pulse Width Low ADV# Pulse Width High UB#, LB# and CE# Pulse Width High CRE Setup to CE# Low Address Skew (Non-Page Access) Page Mode Access Address Skew [A3:A0] Parameter Min 70 — — 20 — 5 10 10 5 — — — — 6 0 6 0 3 0 10 10 10 0 — — Max — 70 70 — 20 — — — — 70 70 20 4 — 8 — 8 — 8 — — — — 10 2 Units ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1,3 1,3 1,3 1 1 1 1 1,2 1 1 1 1 1 1 1,3 1,3 1 1 1,4 1,5
Timing parameters are at the default output drive strength (half drive strength). tCSL max limit applies during asynchronous reads when page mode is enabled. Applies to ADV# controlled Asynchronous Read operations. Applies when control signals (ADV#, CS#, UB#/LB#) are active. When operating the PSRAM as an ADMux I/O interface, Page-Mode operation is not available.
Datasheet 20
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Figure 6:
Address Skew for Asynchronous Operations
tASKEW Address ADV# (case 1) tASKEW CE# (case 1) tASKEW ADV# (case 2) tASKEW CE# (case 2) tASKEW
Figure 7:
PSRAM Asynchronous Single-Word Read
tRC tAA
A[MAX:0] tAADV ADV# tCO CE# OE# W E# tBA UB#/LB# tOLZ tOE tBLZ tLZ DQ[15:0]
Note: WAIT is configured for active-low polarity.
tCPH
tCPH
tBHZ tHZ tOHZ
November 2007 Order Number: 311760-10
Datasheet 21
128-Mbit W18 Family with Synchronous PSRAM
Figure 8:
Asynchronous Address-controlled Read
tRC
A[MAX:0] tAA DQ[15:0]
Note:
ADDRESS tOH Previous Data
Data Valid
CE# = OE# = UB# =LB# = CRE = Low; WE# = High
Figure 9:
PSRAM Asynchronous Page-Mode Read
A[MAX:0] tRC tAA ADDRESS tVPH ADV# tCO P-CS# tAADV
ADDRESS tPC ADDR
A3-A0
ADDR
ADDR
ADDR tOH
tCSL tBLZ R-UB#, R-LB# R-WE# R-OE# tOLZ tLZ Data tCEW WAIT deasserted tOH Data tPAA Data
tHZ tBHZ
tOHZ Data Data Data
Note:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, Page-Mode operation cannot be used. RCR7 must be set to Zero.
Datasheet 22
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Figure 10: PSRAM Asynchronous Control Register Read
tRC tAA A[19:18] A[M AX:20,17:0] tCRES CR E tAADV AD V# tC O CE# OE# WE# tBA UB#/LB# tOLZ tOE tBLZ tLZ DQ[15:0] tCPH tCPH
tBHZ tHZ tOHZ
7.3
PSRAM Asynchronous Write
The figures and tables below shows the PSRAM AC characteristics. All timing parameters are measured with the default output drive strength (half drive strength).
Table 12: PSRAM AC Characteristics—Asynchronous Write (Sheet 1 of 2)
Symbol tWC tAS tAW tWR tCSL tCW tVPH tVP tAVH tAVS tCVS tVS tBW tCKA tWP tWPH Write Cycle Time Address Setup Time Address Valid to End of Write Write Recovery CE# Pulse Width Low Time CE# to End of Write ADV# Pulse Width High ADV# Pulse Width Low Address Hold from ADV# High Address Setup to ADV# High CE# Low to ADV# High ADV# Setup to End of Write UB#, LB# Setup to End of Write Asynchronous Address to Burst Transition Time WE# Pulse Width Low WE# Pulse Width High Parameter Min 70 0 70 0 — 70 10 10 5 10 10 70 70 70 46 10 Max — — — — 4 — — — — — — — — — — — Units ns ns ns ns µs ns ns ns ns ns ns ns ns ns ns ns 1 2 2 2 2 2 Notes
November 2007 Order Number: 311760-10
Datasheet 23
128-Mbit W18 Family with Synchronous PSRAM
Table 12: PSRAM AC Characteristics—Asynchronous Write (Sheet 2 of 2)
Symbol tCPH tWHZ tOW tDW tDH tCRES tCREH tASKEW Notes: 1. 2. 3. 4. Parameter UB#, LB# and CE# Pulse Width High Write Enable Low to Output High-Z End of Write to Output Low-Z Write Data Setup Time Write Data Hold Time CRE SetupTime to CE# and WE# Low CRE Hold Time From WE# High Address Skew (Non-Page Access) Min 10 — 5 23 0 0 0 — Max — 8 — — — — — 10 Units ns ns ns ns ns ns ns ns 4 4 3 Notes
WE# Low time must be limited to tCSL Max. For ADV# controlled Async Write operation. Applies when control signals (ADV#, CE#, UB#, LB#) are Active. For ADV# controlled write tAVS and tAVH apply to CRE signal instead of tCRES and tCREH .
Figure 11: PSRAM Asynchronous WE# controlled Write
tWC tAW tWR A[MAX:0] tVS ADV# tCW CE# tWP tAS WE# tBW UB#/LB# tWHZ tBLZ tLZ DQ[15:0] tDW tDH tOW tWPH
Datasheet 24
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Figure 12: PSRAM Asynchronous CE# controlled Write
tWC tAW tWR A[MAX:0] tVS ADV# tCW tAS CE# tWP WE# tBW UB#/LB# tWHZ tBLZ tLZ DQ[15:0] tDW tDH tCPH
Figure 13: PSRAM Asynchronous UB#/LB# controlled Write
tWC tAW tWR A[MAX:0] tVS ADV# tCW tAS CE# tWP WE# tBW UB#/LB# tWHZ tBLZ tLZ DQ[15:0] tDW tDH tCPH
November 2007 Order Number: 311760-10
Datasheet 25
128-Mbit W18 Family with Synchronous PSRAM
Figure 14: PSRAM Asynchronous ADV# controlled Write
tAW A[MAX:0] tAVS tVP tVS ADV# tCW CE# tAS W E# tBW UB#/LB# tWHZ tBLZ tLZ DQ[15:0] tDW tDH tW P tCPH tAVH tVPH
Figure 15: PSRAM Asynchronous Control Register Write
tWC tAW tW R A[MAX:0] tCRES CRE tVS ADV# tCW tAS CE# tAS WE# UB#/LB# DQ[15:0] tW P tCREH tCPH
7.4
PSRAM Synchronous Read and Write
The figures and tables below shows the PSRAM AC characteristics. All timing parameters are measured with the default output drive strength (half drive strength).
Datasheet 26
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Table 13: PSRAM AC Characteristics—Synchronous Read and Write
Symbol fCLK2 fCLK6 tCLK2 tCLK6 tCKH tCKL tT tABA tAA tAADV tCO tAVH tSP tHD tCSS tCSL tCBPH tOL tOD tAOE tCWT tWZ tWK tACLK tKOH tASKEW Notes: 1. 2. 3. 4. 5. Parameter CLK Frequency (Variable Latency = 2) Non-Mux and AD Mux CLK Frequency (Fixed Latency = 6) Non Mux and AD Mux CLK Period (Variable Latency = 2) Non Mux CLK Period (Fixed Latency = 6) CLK High Time CLK Low Time CLK Rise/Fall Time Burst Read First Access Delay (Variable Latency = 2) Address Access Time (Fixed Latency) ADV# Access Time (Fixed Latency) CE# Access Time (Fixed Latency) Address Hold from ADV# High (Fixed Latency) Input Setup to CLK High (except CE#) Input Hold from CLK High CE# Low Setup to CLK High CE# Pulse Width Low Time CE# Pulse Width High Time Between Operations OE# or UB#/LB# Low to Output Low-Z CE#, OE#, or UB#/LB# High to Output in High-Z OE# Low to Output Delay CE# Low to WAIT Valid CE# High to WAIT High-Z CLK to WAIT Valid CLK to Output Delay Output Hold from CLK Address Skew Min — — 18.5 18.5 4 4 — — — — — 5 3 2 4.5 — 6 3 0 — 1 — — — 2 — Max 66 66 — — — — 1.8 47.5 70 70 70 — 20 — 20 4 — — 8 20 7.5 8 9 9 — 10 Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns ns ns ns ns ns — 5 3 4 5 2 1 Notes
In case of refresh collisions with the first access, more WAIT cycles will be added. tSP Max values only applies to ADV#. The purpose of the Max limit is to prevent the PSRAM from starting Async access cycle. To allow for proper refresh operation, the CE# must be high during a clock low to high transition or keep CE# high for min 15 ns. Address Skew maximum must not be exceeded during synchronous operations to avoid inadvertent asynchronous operation
November 2007 Order Number: 311760-10
Datasheet 27
128-Mbit W18 Family with Synchronous PSRAM
Figure 16: Address Skew for Synchronous Operations
CLK Address ADV# (Case 1) tASKEW CE# (Case 1) tASKEW ADV# (Case 2) CE# (Case 2)
Figure 17: PSRAM Synchronous Read followed by Synchronous Write
CLK tHD tSP A [MAX:0] tHD tSP ADV# tCBP H tCSS tSP tHD tAVH tSP tHD tAVH
tCSS CE #
tHD
tHD
tHD OE # tHD tSP W E# tSP UB #/LB # tHD tSP
tHD
tHD
tSP
tHD
tCW T tCWT W AIT tACLK tAOE tOL tABA DQ[15:0] tOD tKOH tHD tSP tW K tW Z tWK tW Z
Datasheet 28
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Figure 18: PSRAM Synchronous Write followed by Synchronous Read
tHD tS P A[MA X:0] tHD tS P ADV # tCB P H tCSS tSP tHD tAV H tSP tHD tA VH
tCS S CE # tHD tS P OE # tHD tS P WE # tS P UB #/LB #
tHD
tHD
tHD
tHD tSP
tSP
tHD
tCW T tCW T WA IT tA CLK tHD tS P DQ[15:0] tOL tAOE tA BA tKOH tOD tW K tW Z tW K tW Z
Figure 19: PSRAM Synchronous Read followed by Asynchronous Write
CLK tH D tS P A [ MA X :0 ] tA V S tV P tH D tS P AD V# tC B P H tC S S CE # tH D OE # tH D tS P W E# tS P U B #/L B # tC W T W A IT tA C LK tA O E tOL tA B A D Q [1 5 :0 ] t OD tK O H tW K tW Z tH D tA S tH D tV P H tA V H tV S tA V H tA W
November 2007 Order Number: 311760-10
Datasheet 29
128-Mbit W18 Family with Synchronous PSRAM
Figure 20: PSRAM Asynchronous Write followed by Synchronous Read
C LK tH D tSP
tA W A [M A X :0] tA V S tV P tV S AD V# tC P H tC W C E# tA V H tVP H
tH D tSP
tC S S
tW P tAS WE# OE# tW P H
tH D tSP
tSP tB W U B #/LB # tW H Z tB L Z tLZ D Q [1 5:0] tD H tD W tO L tC P H
Figure 21: PSRAM Synchronous Control Register Read
C LK t HD tSP A [19:18] A [ M A X : 20 : 17 : 0 ] tSP CRE tHD tSP A DV # tC B PH t CS S CE# tHD O E# tHD tSP W E# tSP U B # / LB # tCW T W A IT tA O E tO L tA B A D Q [ 15 : 0 ] tA C LK tK O H tO D tW K tW Z tHD tHD tHD t HD tAV H
Datasheet 30
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Figure 22: PSRAM Synchronous Control Register Write
C LK tH D tS P A [ M A X :0 ] tS P CRE tS P AD V# tC B P H tC S S C E# tS P O E# tS P W E# U B # /L B # tC W T W A IT D Q [1 5 : 0 ] tW K tW Z tH D tH D tH D tH D tH D tH D tA V H
8.0
Note:
Device Bus Interface
Refer to the Numonyx™ Wireless Flash Memory Datasheet for detailed flash die information. The PSRAM Bus Interface is described in the sections that follow. The PSRAM bus interface supports asynchronous and synchronous read and write transfers. By default the PSRAM device is reset to the asynchronous SRAM-type mode after power-up. To put the device in a different operation mode the Bus Configuration Register must be programmed first accordingly.
8.1
PSRAM Reads
The PSRAM bus interface supports asynchronous single-word, asynchronous pagemode, and synchronous burst-mode reads. PSRAM Refresh Control Register bit 7 (RCR7) defines whether page-mode reads are enabled. Page-mode reads are enabled when RCR7 is set to a one, and disabled when RCR7 is set to zero.
8.1.1
PSRAM Asynchronous Read
To initiate an asynchronous read operation: • CE#, OE#, and UB#/LB# must be asserted. • WE# and CRE must be deasserted. • ADV# can be toggled to latch the address or held low for the entire read operation. • CLK must be held in a static state.
November 2007 Order Number: 311760-10
Datasheet 31
128-Mbit W18 Family with Synchronous PSRAM
Valid data is available on the data bus after the specified access time has elapsed. WAIT output is driven, but should be ignored for asynchronous-mode read operations. Warning: When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data phase cycle.
8.1.2
PSRAM Asynchronous Page-Mode Read
Page mode allows toggling of the four lower address bits (A3 to A0) to perform subsequent random read accesses (max. 16-words by A3-A0) at much faster speed than the 1st read access. Only page mode Read operations are supported by the PSRAM. Once page mode is enabled by appropriately setting the BCR, tCSL restrictions will apply to asynchronous Read accesses. Therefore CE# will have to be pulled high at least every tCSL period during asynchronous Read operations. ADV# has to be held low for the entire page operation.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, Page-Mode operation cannot be used. RCR7 must be set to Zero.
8.1.3
PSRAM Synchronous Burst-Mode Reads
In the Full Synchronous mode and NOR-Flash mode, PSRAM read operations are synchronous. A BURST INIT READ command is used to initiate a synchronous read operation and latch the burst start address. To initiate a synchronous read operation: • CE#, ADV#, and both UB# and LB# must be asserted; • WE# and CRE must be deasserted; and • Burst start address is latched on the rising edge of the clock; To continue the synchronous read operation: • CE#, OE#, and both UB# and LB# must be asserted; and • ADV# must be deasserted; The first data word is output after the number of clock cycles defined by the programmed latency mode and latency count in the BCR. Subsequent data words are output at successive clock cycles after the first data word. • WAIT output will be driven and should be monitored in Variable Latency mode. • WAIT may be ignored in fixed latency mode. • Both UB# and LB# must be held static low for the entire read access. The size of the burst is also specified in the BCR.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data phase cycle.
8.1.4
PSRAM Asynchronous Fetch Control Register Read
In the Asynchronous (SRAM-type) mode the contents of the BCR and RCR can be read asynchronously. To initiate an asynchronous Fetch Control Register (FCR): • CE#, OE#, CRE, and both UB# and LB# must be asserted; • WE# must be deasserted; • ADV# can be toggled to latch the address or held low for the entire read operation;
Datasheet 32
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
• CLK must be held in a static low state. Except for A19 and A18, all other address and data bits are don’t care. A19 and A18 specify the target register (RCR = 00b, BCR = 10b) The contents of the selected register are available on the data bus after the specified access time has elapsed. WAIT output will be driven but should be ignored for asynchronous operations. Warning: When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data phase cycle.
8.2
PSRAM Writes
The PSRAM bus interface supports asynchronous single-word and synchronous burstmode writes. BCR15 defines whether asynchronous or synchronous mode is enabled.
8.2.1
PSRAM Asynchronous Write
In the Asynchronous (SRAM-type) mode and NOR-Flash mode, PSRAM write commands are asynchronous. To initiate an asynchronous write operation: • CE# and WE# must be asserted; • UB# and LB# must be asserted appropriately depending on the data byte(s) that are being written. UB# enables DQ[15:8] and LB# enables DQ[7:0]. • CRE must be deasserted; • ADV# can be toggled to latch the address or held low for the entire read operation; • CLK must be held in a static state. The data to be written will be latched on the rising edge of CE#, WE# or UB#/LB# whichever occurs first. WAIT output will be driven but should be ignored for asynchronous-mode operations.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data phase cycle.
8.2.2
PSRAM Synchronous Write
In the Full Synchronous mode, PSRAM write operations are synchronous. A BURST INIT WRITE command is used to initiate a synchronous write operation and latch the burst start address. To initiate a synchronous write operation: • CE#, ADV#, and WE# must be asserted; • OE# and CRE must be deasserted; and • Burst start address is latched on the rising edge of the clock; To continue the synchronous write operation: • CE#, and UB#/LB# must be asserted; and • ADV# must be deasserted; The first data word is input after the number of clock cycles defined by the programmed latency mode and latency count in the BCR. Subsequent data words are input at successive clock cycles after the first data word. The size of the burst is also specified in the BCR. WAIT output will be driven and may be monitored. But since
November 2007 Order Number: 311760-10
Datasheet 33
128-Mbit W18 Family with Synchronous PSRAM
synchronous write is always at fixed latency regardless of the Latency Mode setting, WAIT may be ignored. UB# or LB# may be deasserted to mask the associated data byte. Warning: When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data phase cycle.
8.2.3
PSRAM Asynchronous Set Control Register Write
In the Asynchronous (SRAM-type) mode and NOR-Flash mode the contents of the BCR and RCR can be set asynchronously. To initiate an asynchronous Set Control Register: • CE#, WE#, and CRE must be asserted; • OE# must be deasserted; • ADV# can be toggled to latch the address or held low for the entire read operation; • CLK must be held in a static low state. The DQ signals are ignored by the PSRAM. Address bits A19 and A18 specify the target register (RCR = 00b, BCR = 10b.) The values of the remaining address bits are loaded into the selected register. The Set Control Register command should only be issued when the PSRAM is in the idle state (deselected).
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data phase cycle.
8.2.4
PSRAM Synchronous Set Control Register Write
In the full Synchronous mode the contents of the BCR and RCR can be set synchronously. To initiate a synchronous Set Control Register: • CE#, WE#, ADV#, and CRE must be asserted; and • OE# must be deasserted; • Address is latched on the rising edge of the clock The DQ signals are ignored by the PSRAM and therefore the WAIT signal should be ignored. Address bits A19 and A18 specify the target register (RCR = 00b, BCR = 10b.) The values of the remaining address bits are loaded into the selected register. The Set Control Register command should only be issued when the PSRAM is in the idle state (deselected).
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data phase cycle.
8.3
PSRAM No Operation Command
The No Operation (NOP) command is used to perform a no operation to a selected PSRAM (CE# = Low) Operations in progress are not affected. A NOP may be issued in Asynchronous, Synchronous, or NOR-Flash mode. To initiate a NOP: • CE#, must be asserted; • WE#, ADV#, OE#, and CRE must be deasserted; and • CLK must be held in a static low state while in Asynchronous mode. CLK may toggle during a NOP in Synchronous mode.
Datasheet 34
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
• In Synchronous mode, ADV# deasserted hold time (tHD) must be observed. Warning: When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data phase cycle.
8.4
PSRAM Deselect
The Deselect function prevents new commands from being executed by the PSRAM. A deselected PSRAM places its I/O signals in a high impedance state. To place the device in a deselected state: • CE# must be deasserted. • CLK must be held in a static low state while in Asynchronous mode. CLK may toggle during a NOP in Synchronous mode.
8.5
PSRAM Deep Power Down
Deep Power Down (DPD) stops all refresh-related activities and the current consumption of the device drops to a very low level. The contents of the Memory are not preserved. After setting RCR4 = 1b, to place the device in the DPD state • CE# must be deasserted. • CLK must be held in a static low state to achieve minimum current consumption levels.
8.6
PSRAM WAIT Signal
The WAIT signal is used in synchronous mode to indicate to the host system periods of invalid data. Periods of invalid data are caused by: 1. First access delays, or 2. End of Row condition for continuous or wrap-off burst settings. For fixed length bursts with wrap on, WAIT remains deasserted when the End of Row is reached and the burst will wrap around and continue without any delay. Therefore for fixed length bursts with wrap on, WAIT is only asserted during First access delays. For continuous or wrap-off burst length configuration, End of Row condition, WAIT will transition from being de-asserted to being asserted within the time window defined by tKOH and tWK. Depending on the implementation for a burst write, WAIT may be asserted at the same time as the delay (condition A of Figure 23) or one clock cycle later (condition B of Figure 23.) This inconsistency does not occur during burst read.
November 2007 Order Number: 311760-10
Datasheet 35
128-Mbit W18 Family with Synchronous PSRAM
Figure 23: PSRAM WAIT Behavior during Burst Write End-of-Row with Wrap Off
CLK tCSS tHD CE# tWK tWZ
B
tWK WAIT DQ[15:0]
A
End of Row
Figure 24: PSRAM WAIT Behavior during Burst Read End-of-Row with Wrap Off
CLK tCSS tHD CE# tWK WAIT tOD DQ[15:0] End of Row tWZ
During variable latency burst write operations and fixed latency burst write and read operations the initial latency is fixed so the system is not required to monitor the WAIT signal although the WAIT signal is fully functional and may be monitored by the system. The system should terminate or interrupt the burst access to avoid row boundary crossings in both fixed and variable latency mode. To match with the Flash interfaces of different microprocessor types the polarity and the timing of the WAIT signal can be configured. The polarity can be programmed to be either active low or active high. The timing of the WAIT signal can be adjusted as well. Depending on the BCR setting the WAIT signal will be either asserted at the same time the data becomes invalid or it will be set active one clock period in advance. In asynchronous mode including page mode, the WAIT signal is not used but stays asserted as BCR bit 10 is specified. In this case, the system should ignore the WAIT signal. When the PSRAM is deselected or in deep power down, the WAIT output will be in a high impedance state.
Datasheet 36
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
9.0
Note:
Device Operations
Refer to the Numonyx™ Wireless Flash Memory Datasheet for detailed flash die information. PSRAM device operations are described in the sections that follow.
9.1
9.1.1
Device Power-Up/Down
Flash Power and Reset Specifications
Refer to the Intel® Wireless Flash Memory (W18) Datasheet (order number: Non-Mux I/O doc #290701 and ADMux I/O doc #313272) for detailed information.
9.1.2
PSRAM Power-Up Sequence and Initialization
The power-on and initialization sequence ensures that the device is properly preconditioned to operate as expected. Like conventional DRAMs, the PSRAM must be powered up and initialized in a predefined manner. VCC and VCCQ must be applied at the same time to the specified voltage while the input signals are held in a deselected state (CS# = High). After power on, an initial pause of 150 µs is required prior to the control register access or normal operation. Failure to follow these steps may lead to unpredictable behavior. The default operation mode after power up is the asynchronous (SRAM) mode.
Figure 25: PSRAM Timing Waveform for Power-Up Sequence
P-VCC/ VCCQ P-CS#
P-Vcc MIN
tPU >= 150 μ s
Device Initialization
§
Device ready for normal operation
9.2
PSRAM Operating Modes
The PSRAM can be used in three different operating modes: • SRAM (full asynchronous) mode: In this mode the PSRAM applies the standard asynchronous SRAM protocol to perform read and write accesses. In additions, reads may be performed in page mode if the page mode is properly enabled by programming the RCR. In this mode the clock must always remain static low. • Fully Synchronous mode: In this mode, both read and write accesses are performed synchronously with respect to the clock. Synchronous operations are defined by the states of the control signals CE#, ADV#, OE#, WE# and UB#, LB# at the positive (default) edge of the clock. • NOR-Flash mode: In this mode, reads are performed synchronously with respect to the clock and writes are performed asynchronously. The asynchronous write operation requires that the clock remain static low during the entire write. Synchronous read operations are defined by the states of the control signals CE#, ADV#, OE#, WE# and UB#, LB# at the positive (default) edge of the clock.
November 2007 Order Number: 311760-10
Datasheet 37
128-Mbit W18 Family with Synchronous PSRAM
9.3
PSRAM Control Registers
The PSRAM includes two control registers that define the PSRAM device operation. The Bus Control Register (BCR) defines how the PSRAM interacts with the system memory busy, and the Refresh Control Register (RCR) defines low-power refresh modes. Both these registers are loaded with default values on power-up and can be updated at any time using hardware or software access method.
9.3.1
PSRAM Bus Control Register
The Bus Control Register (BCR) specifies the interface configurations. The Bus Control Register is programmed via the Set Control Register command (with CRE = 1 and A[19:18] = 10b) and retains the stored information until it is reprogrammed or the device loses power. Reserved bit fields of the BCR should be ignored during a Fetch Control Register command as they may have undefined values even when set to 0b with a Set Control Register command. The BCR contents can only be set or changed when the PSRAM is in idle state.
Table 14: PSRAM Bus Control Register Map
WAIT Configuration Latency Counter Operating Mode Register Select Drive Strength Initial Latency WAIT Polarity
DQ [15:0] A [MAX:0 ] BCR Bit A22 A20 2220 A1 9 19 A1 8 18 A17 A16 1716
DQ1 5 A15
DQ1 4 A14
DQ1 3 A13
DQ1 2 A12
DQ1 1 A11
DQ1 0 A10
DQ 9 A9
DQ 8 A8
DQ 7 A7
DQ 6 A6
DQ 5 A5
DQ 4 A4
DQ 3 A3
DQ 2 A2
DQ 1 A1
Burst Length DQ 0 A0 2 1 0
15
14
13
12
11
10
9
8
7
6
5
4
3
Table 15: Bus Control Register Description
BCR Bit 22:20 19:18 17:16 15 14 Reserved Register Select Reserved Operating Mode Initial Latency NAME Description Reserved bits should be set to ‘0’ during set control register commands 10 = Select BCR Reserved bits should be set to ‘0’ during set control register commands 0 = Synchronous Burst Mode 1 = Asynchronous Mode (Default) 0 = Variable (Default) 1 = Fixed
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November 2007 Order Number: 311760-10
Burst Wrap
Reserved
Reserved
Reserved
Reserved
128-Mbit W18 Family with Synchronous PSRAM
Table 15: Bus Control Register Description
BCR Bit NAME 000 001 010 011 100 101 110 111 = = = = = = = = Code Code Code Code Code Code Code Code 0 1 2 3 4 5 6 7 - Reserved - Reserved (Default) Description
13:11
Latency Counter
- Reserved
10 9 8 7:6
WAIT Polarity Reserved WAIT Configuration Reserved
0 = Active Low 1 = Active High (Default) Reserved bits should be set to ‘0’ during set control register commands 0 = WAIT asserted during delay 1 = WAIT asserted one data cycle before delay (Default) Reserved bits should be set to ‘0’ during set control register commands 00 01 10 11 = = = = Full 1/2 (Default) 1/4 Reserved
5:4
Drive Strength
3
Burst Wrap
0 = Burst wraps within the burst length 1 = Burst does not wrap (Default) 000 001 010 011 100 101 110 111 = = = = = = = = Reserved 4 words 8 words 16 words 32 words Reserved Reserved Continuous Burst (Default)
2:0
Burst Length
9.3.1.1
PSRAM BCR Operating Mode
The PSRAM supports three different interface access protocols: • SRAM-type protocol with asynchronous read and write accesses • NOR-Flash-type protocol with synchronous read and asynchronous write accesses • FULL SYNCHRONOUS mode with synchronous read and synchronous write accesses Operating the PSRAM in synchronous mode maximizes bandwidth. The NOR-Flash type mode is the recommended mode for legacy systems which are not able to run the synchronous write protocol. The Operating Mode bit BCR15 defines whether the device is operating in synchronous (fully or partially) mode or asynchronous mode. When BCR15 is set low, the mode of write operation, NOR-flash or Full synchronous, is adaptively detected by detecting a rising clock edge during ADV# valid. If a rising clock edge occurs within ADV# valid, Full synchronous write is detected. If there is no rising clock edge then NOR-Flash write is detected and CE# must go high when transitioning from asynchronous to synchronous operation or when transitioning from synchronous to asynchronous operation.. When BCR15 is set high, the SRAM-type mode of operation is selected.
November 2007 Order Number: 311760-10
Datasheet 39
128-Mbit W18 Family with Synchronous PSRAM
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data phase cycle.
9.3.1.2
PSRAM Initial Latency BCR Bit
The PSRAM latency is related to the number of clock cycles from the burst-init command to be either 1st valid data output (read burst) or 1st valid data input (burst write.) • In Fixed Latency mode, the number of clock cycles from bust-init command to valid data is always fixed as defined by the Latency Counter setting in the BCR. • In Variable Latency mode, the number of clock cycles from bust-init command to valid data output (read burst) is variable depending on internal device operation. The minimum latency in Variable Latency mode is defined by the Latency Counter setting in the BCR. Additional WAIT cycles may be added in Variable Latency mode if the burst-init Read command collides with an on-going internal refresh. Additional WAIT cycles are not added for burst-init Write commands in Variable Latency mode.
9.3.1.3
PSRAM Latency Counter BCR Bit
The latency counter defines the number of clock cycles that pass before the first output data is valid (read burst) or before the first input data is valid (read burst.) Each Latency Code setting has an associate maximum PSRAM clock frequency. In the case of Variable Latency the first access delay might be extended by additional wait cycles in case the burst read access collides with an ongoing self-refresh operation. The allowed values of the Latency Counter also depend on the Initial Latency setting in BCR.
Table 16: Optional PSRAM BCR Latency Counter Settings in Variable Latency
Latency Counter 010 011 Others PSRAM Code 2; Max 66 MHz Code 3; Max 80 MHz Reserved
Table 17: Optional PSRAM BCR Latency Counter Settings in Fixed Latency
Latency Counter 010 011 100 101 110 Others PSRAM Code 2; Max 33 MHz Code 3; Max 52 MHz Code 4; Max 66 MHz Code 5; Max 75 Mhz Code 6; Max 104 MHz Reserved
Datasheet 40
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Figure 26: Example of the Latency of First Valid Data in Synchronous Mode
9.3.1.4
PSRAM WAIT Polarity BCR Bit
The WAIT polarity control bit allows the user to define the polarity of the WAIT output signal. The WAIT output line is used during a variable latency synchronous read burst to signal when the output data is invalid. Active low WAIT polarity means that when WAIT is asserted low, output data is invalid. Similarly active high WAIT polarity means that when WAIT is asserted high, output data is invalid.
9.3.1.5
PSRAM WAIT Configuration BCR Bit
The WAIT signal configuration control bit specifies whether the WAIT signal is asserted at the time of the delay or whether it is asserted one clock cycle in advance of the delay.
9.3.1.6
PSRAM Drive Strength BCR Bit
For adaptation to different system characteristics the output impedance can be configured. Full drive strength is targeted for 25-30 Ohm systems, half drive strength is targeted for 50 Ohm systems, and quarter drive strength is targeted for 100 Ohm systems.
9.3.1.7
PSRAM Burst Wrap BCR Bit
The burst wrap control bit defines whether there is a wrap around within a burst access or not. In case of fixed 8-word burst length, this means that after word #7, word #0 is going to be output in wrap mode. In case of continuous burst mode the internal address counter will increment continuously until terminated by the system. For continuous burst mode or non-wrap mode, the burst access must be terminated prior to a row boundary crossing. The burst wrap setting is used for both Write and Read operations.
9.3.1.8
PSRAM Burst Length BCR Bit
The burst length setting defines the Wrap boundary whenever Burst Wrap is enabled by setting BCR3 = 0b. When Burst Wrap is disabled by setting BCR3 = 1b, all burst behave as Continuous Bursts regardless of the Burst Length setting. Furthermore all fixed length bursts (4-, 8-, 16-, and 32-word bursts) will continue until terminated by bringing CE# high or interrupted by initiating a new burst access. Continuous Burst and
November 2007 Order Number: 311760-10
Datasheet 41
128-Mbit W18 Family with Synchronous PSRAM
Fixed Length Burst with Wrap Off will increment the address until a row boundary crossing is reached. Fixed Length Bursts will continue to wrap around and cycle through their limited address space until terminated or interrupted. The burst length setting is used for both Write and Read operations. Table 18: PSRAM Burst Length Sequences
Burst Length Starting Address [A4:A0] 00000b 00001b ... 11110b 11111b 00000b 00001b ... 11110b 11111b 00000b 00001b ... 11110b 11111b 00000b 00001b ... 11110b 11111b 00000b 00001b ... 11110b 11111b Burst Address Sequence (decimal) Wrap Off 0-1-2-3-4-5-6-7-...-EOR 1-2-3-4-5-6-7-8-...-EOR ... 30-31-32-33-34-...-EOR 31-32-33-34-35-...-EOR 0-1-2-3-4-5-6-7-...-EOR 1-2-3-4-5-6-7-8-...-EOR ... 30-31-32-33-34-...-EOR 31-32-33-34-35-...-EOR 0-1-2-3-4-5-6-7-...-EOR 1-2-3-4-5-6-7-8-...-EOR ... 30-31-32-33-34-...-EOR 31-32-33-34-35-...-EOR 0-1-2-3-4-5-6-7-...-EOR 1-2-3-4-5-6-7-8-...-EOR ... 30-31-32-33-34-...-EOR 31-32-33-34-35-...-EOR 0-1-2-3-4-5-6-7-...-EOR 1-2-3-4-5-6-7-8-...-EOR ... 30-31-32-33-34-...-EOR 31-32-33-34-35-...-EOR Wrap On 0-1-2-3-0-1-2-3-... 1-2-3-0-1-2-3-1-... ... 30-31-28-29-30-31-28-29-... 31-28-29-30-31-28-29-30-... 0-1-2-3-4-5-6-7-0-1-2-3-... 1-2-3-4-5-6-7-0-1-2-3-4-... ... 30-31-24-25-26-27-28-29-30-... 31-24-25-26-27-28-29-30-31... 0-1-2-...-13-14-15-0-1-2-... 1-2-3-...-14-15-0-1-2-3-... ... 30-31-16-17-...-29-30-31-16-17-... 31-16-17-...-29-30-31-16-17-... 0-1-2-...-29-30-31-0-1-2-... 1-2-3-...-29-30-31-0-1-2-... ... 30-31-0-...-29-30-31-0-1-... 31-0-1-...-29-30-31-0-1-... 0-1-2-3-4-5-6-7-...-EOR 1-2-3-4-5-6-7-8-...-EOR ... 30-31-32-33-34-...-EOR 31-32-33-34-35-...-EOR
4
8
16
32
Continuous
Note:
EOR = End of Row
9.3.2
PSRAM Refresh Control Register
The Refresh Control Register (RCR) allows for additional stand-by power savings by making use of the Partial-Array Self Refresh (PASR) and Deep Power Down (DPD) features. The RCR is programmed via the Control Register Set command (with CRE = 1 and A[18:19] = 00b) and retains the stored information until it is reprogrammed or the device loses power. Reserved bit fields of the RCR should be ignored during a Fetch Control Register command as they may have undefined values even when set to 0b with a Set Control Register command. The RCR contents can only be set or changed when the PSRAM is in idle state.
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November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Table 19: PSRAM Refresh Control Register Map
Reserved DQ[15:0] A[MAX:0 ] RCR Bit A22 - A20 22 - 20 A19 19 A18 18 Register Select Reserved DQ16-DQ8 A17 - A8 17 - 8 Page Mode DQ7 A7 7 Reserved DQ6 A6 6 DQ5 A5 5 Deep Power Down (DPD) DQ4 A4 4 Reserved DQ3 A3 3 DQ2 A2 2 PASR DQ1 A1 1 DQ0 A0 0
Table 20: PSRAM Refresh Control Register Description
RCR Bit 22:20 19:18 17:8 7 6:5 4 3 Reserved Register Select Reserved Page Mode Reserved Deep Power Down (DPD) Reserved NAME Description Reserved bits should be set to ‘0’ during set control register commands 00 = Select RCR Reserved bits should be set to ‘0’ during set control register commands 0 = Page Mode disabled (Default) 1 = Page Mode enabled Reserved bits should be set to ‘0’ during set control register commands 0 = DPD enabled 1 = DPD disabled (Default) Reserved bits should be set to ‘0’ during set control register commands 000 001 010 011 100 101 110 111 = = = = = = = = Full array refreshed (Default) Bottom 1/2 of array refreshed Bottom 1/4 of array refreshed Bottom 1/8 of array refreshed None of array refreshed Top1/2 of array refreshed Top1/4 of array refreshed Top1/8 of array refreshed
2:0
Partial Array Self Refresh
9.3.2.1
PSRAM Page Mode RCR Bit
In asynchronous (SRAM) mode, the user has the option to enable page mode. Page mode applies only to asynchronous read operations and has no impact on asynchronous write operations. In synchronous and NOR-Flash modes, the page mode setting has no impact on PSRAM operation. The maximum page length is 16 words, so A[3:0] is regarded as the page address.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, Page-Mode operation cannot be used. RCR7 must be set to Zero.
9.3.2.2
PSRAM Deep-Power Down RCR Bit
To put the device in deep power down mode the DPD control bit must be set low (RCR4 =0.) All internal voltage generators inside the PSRAM are switched off and the internal self-refresh is stopped. This means that all stored memory information will be lost by entering DPD. Only the register values of BCR, and RCR remain valid during DPD.
November 2007 Order Number: 311760-10
Datasheet 43
128-Mbit W18 Family with Synchronous PSRAM
Deep Power Down Entry: To enter deep power down, RCR4 is set low, CE# is then pulled high and is maintained high for the entire time duration that Deep Power Down mode is desired. To insure proper operation, once CE# is pulled high, it should be maintained high for minimum of 150 µs before beginning the Deep Power Down Exit sequence. Deep Power Down Exit: To exit the deep power down mode the CE# must go low for minimum 10 µs, followed by a guard time of at least 150 µs where CE# must be maintained high. Once deep power down is exited, the DPD control bit RCR4 is automatically reset to 1. All other Control Register contents are unchanged.
Figure 27: Deep Power Down Exit Timing
9.3.2.3
PSRAM Partial-Array Self-Refresh RCR Bit
By applying PASR the user can dynamically customize the memory capacity to the system’s actual need in normal operation mode and standby mode. RCR[2:0] specifies the active memory array and its location (starting from bottom or top). The memory parts not used are powered down immediately after the mode register has been programmed. Advice for the proper register setting including the address ranges is given in the figure below. PASR is effective in normal operation and standby mode as soon as it has been configured by register programming.
Table 21: PASR Address Pattern for PSRAM
Device A2 A1 A0 Density (Mb) Active Section Address
32 Mbit
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
32 16 8 4 0 16 8 4
Full Die 1/2 of die 1/4 of die 1/8 of die None 1/2 of die 1/4 of die 1/8 of die
000000h – 1FFFFFh 000000h – 0FFFFFh 000000h – 07FFFFh 000000h – 03FFFFh 0 100000h – 1FFFFFh 180000h – 1FFFFFh 1C0000h – 1FFFFFh
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November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Table 21: PASR Address Pattern for PSRAM
Device A2 A1 A0 Density (Mb) Active Section Address
16 Mbit
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
16 8 4 2 0 8 4 2
Full Die 1/2 of die 1/4 of die 1/8 of die None 1/2 of die 1/4 of die 1/8 of die
00000h – FFFFFh 00000h – 7FFFFh 00000h – 3FFFFh 00000h – 1FFFFh 0 80000h – FFFFFh C0000h – FFFFFh E0000h – FFFFFh
9.4
PSRAM Access to Control Register
The PSRAM control registers (BCR and RCR) can be updated at any time to select desired operating modes. The control registers can be accessed by the hardware access method using the CRE pin or software access method consisting of a series of reads and writes. The two methods are described in the sections below.
9.4.1
PSRAM Hardware Control Register Access
Hardware write or read access to the PSRAM registers occurs by applying the SCR and FCR commands with the CRE signal asserted high. During the SCR and FCR commands, A[19:18] designates target register. A[19:18] = 00b accesses the Refresh Control Register (RCR), A[19:18] = 10b accesses the Bus Control Register (BCR). The SCR and FCR commands can be applied in either synchronous or asynchronous mode. After applying the SCR command in asynchronous mode, CE# must be pulled high for minimum of tCPH prior to initiating any subsequent command. After applying the SCR command in synchronous mode, CE# must be pulled high for minimum of tCPBH prior to initiating a subsequent synchronous command. Additionally, when applying the synchronous SCR command CE# must remain low to complete a burst of one write even though the DQ values are ignored by the PSRAM. To insure predictable device behavior, an SCR command should not be terminated or interrupted prematurely and ADV# should not go low more than one time prior to CE# being pulled high.
9.4.2
PSRAM Software Register Access
Software access of the registers uses a sequence of asynchronous read and asynchronous write operations. First 2 asynchronous reads to the maximum address are performed followed by an asynchronous write to the maximum address. The data values during this asynchronous write select the appropriate register. During the fourth operation DQ[15:0] transfer data in to or out of the bits [15:0] of the registers. During the software access sequence, it is necessary to: • Toggle CE# between every read or write command (so the Device can distinguish 4 separate cycles). • Maintain the address input until it is latched by ADV# or until CE# goes high. After setting the control registers using the software access method, CE# must be pulled high for minimum of tCPH prior to initiating any subsequent command.
November 2007 Order Number: 311760-10
Datasheet 45
128-Mbit W18 Family with Synchronous PSRAM
• To insure predictable device behavior, the fourth access cycle of the software access should not be terminated or interrupted prematurely and ADV# should not go low more than one time during each access where CE# is low Figure 28: PSRAM Loading Configurations Registers Using Software Access
A[MAX:0] MAX MAX MAX MAX
CE# OE# WE# UB#/LB# DQ[15:0] XXXXh XXXXh
RCR: 0000h BCR: 0001h
Input
Figure 29: PSRAM Reading Registers Using Software Access
A[MAX:0] MAX MAX MAX MAX
CE# OE# WE# UB#/LB# DQ[15:0] XXXXh XXXXh
RCR: 0000h BCR: 0001h DIDR: 0002h
Output
9.4.3
Cautionary Note About Software Register Access
To insure inadvertent access to the PSRAM registers during asynchronous operation, the following two command sequences must be avoided when accessing the main memory array. On the 3rd cycle of these command sequences, a write operation to the main memory may be blocked and the software register access mode is accessible. To prevent this, the two command sequences must be avoided except to access the registers through the software method.
Datasheet 46
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Table 22: Cautionary Command Sequences
Cautionary Command Sequence #1 Address Command Max Async Read Max Async Read Max Async Write
Cautionary Command Sequence #2 Address Command Max Async Write (WE# controlled) Max Async Read Max Async Write
9.5
PSRAM Self-Refresh Operation
Unlike DRAMs, The PSRAM relieves the host system from issuing refresh commands. Self-refresh operations are autonomously scheduled and performed by the PSRAM device. In synchronous mode of operations (variable latency Read), the additional WAIT cycles are used to indicate when the data output is delayed in case a burst initiated access collides with an ongoing refresh cycle.
9.5.1
PSRAM Self-Refresh Operations at Low Frequency
At low frequencies (< 100 KHz), the PSRAM can support only asynchronous read (nonpage and non-burst modes) operations. All other operations (asynchronous writes, page-mode reads, and synchronous burst-mode accesses) are subject to refresh restrictions.
9.6
9.6.1
PSRAM Burst Suspend, Interrupt, or Termination
PSRAM Burst Suspend
While in synchronous burst operation, the bus interface may need to be assigned to other memory transaction sharing the same bus. Burst suspend is used to fulfill this purpose. Keeping CE# low (WAIT stays active although the DQ are tri-stated), burst suspend is initiated by halting CLK. CLK can stay at either high or low state. Burst suspend may also by initiated while WAIT is asserted during the initial latency period or at the end of a row. As specified, duration of keeping CE# low can not exceed tCSL maximum so that internal refresh operation is able to run properly. In the event that tCSL maximum may be exceeded, termination of burst by bringing CE# high is strongly recommended instead of using burst suspend mode.
November 2007 Order Number: 311760-10
Datasheet 47
128-Mbit W18 Family with Synchronous PSRAM
Figure 30: Example of PSRAM Burst Suspend with Read Burst with Latency Code 2
CLK A[MAX:0] ADV# tCSL tCSS CE# OE# WE# UB#/LB# tCWT WAIT tACLK tAOE tOL tABA DQ[15:0]
Note:
tWK
tWZ
tOD tKOH D0
tAOE tOL D1
tKOH D2 D3
tOD
WAIT is configured as Active Low and asserted during delay.
9.6.2
PSRAM Burst Interrupt
In burst interrupt an on-going burst is ended and new burst command issued while keeping CE# low (subject to tCSL restrictions.) To insure proper device operation, a burst interrupt is prohibited until the previous burst-init command completes its first valid data transaction. If a burst read is interrupted by a new burst command, the DQ are put into a high-Z state (within tWHZ time period.) If a burst write is interrupted by a new burst command, the write data is automatically masked regardless of UB#/LB# setting. Also note, that prior to initiating a burst interrupt by taking ADV# low, the ADV# high hold time of tHD must be met with respect to the previous clock cycle
Datasheet 48
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Figure 31: Example of PSRAM Burst Interrupt
Earliest allow ed burst interrup t
CK L C ntrol o
Burst Init N P o-O
NP o-O N -O oP NP o-O
Burst Init
tH D
AV D# D Q
tW Z H C ode 3 R ead b ecom high es -Z W ritedataism asked
9.6.3
PSRAM Burst Termination
A burst access is terminated by bringing CE# high and maintaining high for minimum of tCBPH. In burst mode a refresh opportunity must be provided every tCSL period by maintaining CE# high for minimum of 15ns or maintaining CE# high during a clock low to high transition.
9.7
PSRAM Row Boundary Crossing
Row boundary crossings are not allowed in burst mode (regardless of using variable or fixed latency mode.) An on-going burst must be terminated by the system prior to a row boundary crossing. A row boundary crossing would never occur if the PSRAM is operating in fixed burst length and wrap mode. Therefore the only time the system should be concerned with row boundary crossing is if the PSRAM is operating with “no wrap” (BCR3 = 0b) or “continuous burst length” (BCR[2:0] = 111b) settings. In terminating bursts prior to row boundary crossing, the system may read the row size (128 or 256 words) to determine at which addresses the row boundary crossing occurs. If the system cannot do this, then it should be assumed that the row size is 128 words. In the case of 128-word row size the boundary between adjacent rows occurs at every address ending in 7Fh (111 1111 b.) In the case of 256-word row size the boundary between adjacent rows occurs at every address ending in FFh (1111 1111 b.) At a Row boundary crossing, a burst interrupt or termination must occur no later than 2-clock cycle past the transaction representing the last word of a row.
November 2007 Order Number: 311760-10
Datasheet 49
128-Mbit W18 Family with Synchronous PSRAM
Figure 32: Terminating or Interrupting Burst Prior to Row Boundary Crossing
L te t a w d a s llo e b r t te m a us r in te
L te t a w d a s llo e b r t in r u t us te r p
CK L C# E
Hh ig Lw o
AV D# D Q
Ls a t-1 Ls at L s Wrdo R w at o f o Ls a t-1 Ls at L s Wrdo R w at o f o
10.0
:
Additional Information
Document Intel® Wireless Flash Memory (W18) Datasheet Intel® Wireless Flash Memory (W18) ADMux I/O Datasheet
Order Number 290701 313272 Note:
Contact your local Numonyx Sales Representative or visit the Numonyx website at http://www.Numonyx.com for current information on Numonyx™ Flash memory products, software, and tools.
Datasheet 50
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
11.0
Ordering Information
To order samples, obtain datasheets or inquire about any stack combination, please contact your local Numonyx representative.
Table 23: 38F Type Stacked Components
PF Package Designator 38F Product Line Designator 5070 Product Die/ Density Configuration Char 1 = Flash die #1 Char 2 = Flash die #2 PF = SCSP, RoHS RD = SCSP, Leaded Stacked NOR Flash + RAM Char 3 = RAM die #1 Char 4 = RAM die #2 (See First character applies to Flash die #1 Second character applies to Flash die #2 (See M0 NOR Flash Product Family Y Voltage/NOR Flash CE# Configuration V= 1.8 V Core and I/O; Separate Chip Enable per die (See 0 Parameter / Mux Configuration B Ballout Identifier 0 Device Details
0= No parameter blocks; NonMux I/O interface (See
B= x16D Ballout (See 0= Original released version of this product
Table 25, “38F / 48F Density Decoder” on page 52
for details)
details)
Table 26, “NOR Flash Family Decoder” on page 53 for
details)
Table 27, “Voltage / NOR Flash CE# Configurati on Decoder” on page 53 for
Table 28, “Paramete r / Mux Configurati on Decoder” on page 53 for
details)
Table 2 9, “Ballout Decoder ” on page 54
f or details)
November 2007 Order Number: 311760-10
Datasheet 51
128-Mbit W18 Family with Synchronous PSRAM
Table 24: 48F Type Stacked Components
PC Package Designator PC = Easy BGA, RoHS RC = Easy BGA, Leaded JS = TSOP, RoHS TE = TSOP, Leaded PF = SCSP, RoHS RD = SCSP, Leaded 48F Product Line Designator 4400 Product Die/ Density Configuration Char 1 = Flash die #1 Char 2 = Flash die #2 Char 3 = Flash die #3 Stacked NOR Flash only Char 4 = Flash die #4 (See First character applies to Flash dies #1 and #2 Second character applies to Flash dies #3 and #4 (See P0 NOR Flash Product Family V Voltage/NOR Flash CE# Configuration B Parameter / Mux Configuration 0 Ballout Identifier 0 Device Details
V= 1.8 V Core and 3 V I/O; Virtual Chip Enable (See
B= Bottom parameter; Non-Mux I/O interface (See
0= Discrete Ballout (See
for details)
Table 25, “38F / 48F Density Decoder” on page 52
details)
Table 26, “NOR Flash Family Decoder” on page 53 for
Table 27, “Voltage / NOR Flash CE# Configurati on Decoder” on page 53 for
details)
Table 28, “Paramete r / Mux Configurati on Decoder” on page 53 for
details)
for details)
Table 2 9, “Ballout Decoder ” on page 54
0= Original released version of this product
Table 25: 38F / 48F Density Decoder
Code 0 1 2 3 4 5 6 7 8 9 A B C D E F No Die 32-Mbit 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit 2-Gbit 4-Gbit 8-Gbit 16-Gbit 32-Gbit 64-Gbit 128-Gbit 256-Gbit 512-Gbit Flash Density No Die 4-Mbit 8-Mbit 16-Mbit 32-Mbit 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit 2-Gbit 4-Gbit 8-Gbit 16-Gbit 32-Gbit 64-Gbit RAM Density
Datasheet 52
November 2007 Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Table 26: NOR Flash Family Decoder
Code C C3 J3v.D L18 / L30 M18 P30 / P33 W18 / W30 Family Marketing Name Numonyx Advanced+ Boot Block Flash Memory Numonyx Embedded Flash Memory Numonyx StrataFlash® Wireless Memory Numonyx StrataFlash® Cellular Memory Numonyx StrataFalsh® Embedded Memory Numonyx Wireless Flash Memory No Die
J
L M P W 0(zero)
Table 27: Voltage / NOR Flash CE# Configuration Decoder
Code Z I/O Voltage (Volt) 3.0 1.8 3.0 3.0 1.8 3.0 3.0 1.8 3.0 1.8 1.8 3.0 1.8 1.8 3.0 1.8 1.8 3.0 Core Voltage (Volt) CE# Configuration Seperate Chip Enable per die Seperate Chip Enable per die Seperate Chip Enable per die Virtual Chip Enable Virtual Chip Enable Virtual Chip Enable Virtual Address Virtual Address Virtual Address
Y
X V U T R Q P
Table 28: Parameter / Mux Configuration Decoder
Code, Mux Identification 0 = Non Mux 1 = AD Mux1 2= AAD Mux 3 =Full" AD Mux2 Number of Flash Die Bus Width Flash Die 1 Flash Die 2 Flash Die 3 Flash Die 4
Any
NA
Notation used for stacks that contain no parameter blocks
1 B = Non Mux C = AD Mux F = "Full" Ad Mux 2 3 4 2 4 X32 X16
Bottom Bottom Bottom Bottom Bottom Bottom
Top Bottom Top Bottom Bottom
Top Bottom Top
Top Top
November 2007 Order Number: 311760-10
Datasheet 53
128-Mbit W18 Family with Synchronous PSRAM
Table 28: Parameter / Mux Configuration Decoder
Code, Mux Identification Number of Flash Die 1 T = Non Mux U = AD Mux W = "Full" Ad Mux 2 3 4 2 4 X32 X16 Bus Width Flash Die 1 Top Top Top Top Top Top Bottom Top Bottom Top Top Flash Die 2 Bottom Top Bottom Flash Die 3 Bottom Bottom Flash Die 4
1. Only Flash is Muxed and RAM is non-Muxed 2. Both Flash and RAM are AD-Muxed
Table 29: Ballout Decoder
Code 0 (Zero) B C Q U V W SDiscrete ballout (Easay BGA and TSOP) x16D ballout, 105 ball (x16 NOR + NAND + DRAM Share Bus) x16C ballout, 107 ball (x16 NOR + NAND + PSRAM Share Bus) QUAD/+ ballout, 88 ball (x16 NOR + PSRAM Share Bus) x32SH ballout, 106 ball (x32 NOR only Share Bus) x16SB ballout, 165 ball (x16 NOR / NAND + x16 DRAM Split Bus x48D ballout, 165 ball (x16/x32 NOR + NAND + DRAM Split Bus Ballout Definition
Datasheet 54
November 2007 Order Number: 311760-10
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