313295-04

Numonyx™ StrataFlash® Wireless Memory (L18) with AD-Multiplexed I/O Datasheet Product Features High performance Read-While-Write/Erase — 85 ns initial access — 54MHz with zero wait state, 14 ns clock-todata output synchronous-burst mode — 4-, 8-, 16-, and continuous-word burst mode — Burst suspend — Programmable WAIT configuration — Buffered Enhanced Factory Programming (Buffered EFP): 5 µs/byte (Typ) — 1.8 V low-power buffered and non-buffered programming @ 7 µs/byte (Typ) Architecture — Asymmetrically-blocked architecture — Multiple 8-Mbit partitions: 64Mb and 128Mb devices — Multiple 16-Mbit partitions: 256Mb devices — Four 16-KWord parameter blocks: top configuration — 64-KWord main blocks — Dual-operation: Read-While-Write (RWW) or Read-While-Erase (RWE) — Status register for partition and device status Density and Packaging — 64-, 128-, and 256 Mbit density in VF BGA package — 16-bit wide data bus Power — 1.7 V to 2.0 V VCC operation — I/O voltage: 1.35 V – 2.0 V, 1.7 V– 2.0 V — Standby current: 25 µA (Typ) for 256-Mbit — 4-Word synchronous read current: 15 mA (Typ) @ 54 MHz — Automatic Power Savings (APS) mode Security — OTP space: • 64 unique device identifier bits • 64 user-programmable OTP bits • Additional 2048 user-programmable OTP bits — Absolute write protection: VPP = GND — Power-transition erase/program lockout — Individual zero-latency block locking — Individual block lock-down Software — 20 µs (Typ) program suspend — 20 µs (Typ) erase suspend — Intel® Flash Data Integrator (FDI) optimized — Basic Command Set (BCS) and Extended Command Set (ECS) compatible — Common Flash Interface (CFI) capable Quality and Reliability — Expanded temperature: –25° C to +85° C — Minimum 100,000 erase cycles per block — Intel ETOX* VIII process technology (0.13 µm) 313295-04 November 2007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Numonyx B.V., All Rights Reserved. Datasheet 2 November 2007 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Contents 1.0 Introduction .............................................................................................................. 7 1.1 Nomenclature ..................................................................................................... 7 1.2 Acronyms........................................................................................................... 7 1.3 Conventions ....................................................................................................... 8 Functional Overview .................................................................................................. 9 Package Information ............................................................................................... 10 Ballout and Signal Descriptions ............................................................................... 12 4.1 Signal Descriptions ............................................................................................ 13 4.2 Memory Map..................................................................................................... 15 Maximum Ratings and Operating Conditions ............................................................ 17 5.1 Absolute Maximum Ratings................................................................................. 17 5.2 Operating Conditions ......................................................................................... 17 Electrical Specifications ........................................................................................... 18 6.1 DC Current Characteristics.................................................................................. 18 6.2 DC Voltage Characteristics.................................................................................. 19 AC Characteristics ................................................................................................... 20 7.1 AC Test Conditions ............................................................................................ 20 7.2 Capacitance...................................................................................................... 21 7.3 AC Read Specifications (VCCQ = 1.35 V – 2.0 V) ................................................... 21 7.4 AC Read Specifications: 64- and 128-Mb Densities................................................. 22 7.5 AC Read Specifications for 256-Mb Density ........................................................... 23 7.6 AC Write Specifications ...................................................................................... 30 7.7 Program and Erase Characteristics....................................................................... 32 Power and Reset Specifications ............................................................................... 33 8.1 Power Up and Down .......................................................................................... 33 8.2 Reset............................................................................................................... 33 8.3 Power Supply Decoupling ................................................................................... 34 8.4 Automatic Power Saving (APS)............................................................................ 35 Device Operations ................................................................................................... 36 9.1 Bus Operations ................................................................................................. 36 9.1.1 Reads ................................................................................................... 36 9.1.2 Writes................................................................................................... 36 9.1.3 Output Disable ....................................................................................... 36 9.1.4 Standby ................................................................................................ 37 9.1.5 Reset.................................................................................................... 37 9.2 Device Commands............................................................................................. 37 9.3 Command Definitions......................................................................................... 38 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Read Operations ...................................................................................................... 41 10.1 Asynchronous Read Mode ................................................................................... 41 10.2 Synchronous Burst-Mode Read............................................................................ 41 10.2.1 Burst Suspend ....................................................................................... 42 10.3 Read Configuration Register (RCR) ...................................................................... 42 10.3.1 Read Mode ............................................................................................ 43 10.3.2 Latency Count........................................................................................ 43 10.3.3 WAIT Polarity......................................................................................... 45 10.3.3.1 WAIT Signal Function ................................................................ 45 10.3.4 Data Hold.............................................................................................. 46 November 2007 313295-04 Datasheet 3 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 WAIT Burst Clock Burst Burst Delay............................................................................................46 Sequence ......................................................................................47 Edge.............................................................................................47 Wrap ............................................................................................48 Length ..........................................................................................48 11.0 Programming Operations .........................................................................................49 11.1 Word Programming ............................................................................................49 11.1.1 Factory Word Programming......................................................................50 11.2 Buffered Programming .......................................................................................50 11.3 Buffered Enhanced Factory Programming ..............................................................51 11.3.1 Buffered EFP Requirements and Considerations...........................................51 11.3.2 Buffered EFP Setup Phase ........................................................................52 11.3.3 Buffered EFP Program/Verify Phase ...........................................................52 11.3.4 Buffered EFP Exit Phase ...........................................................................53 11.4 Program Suspend ..............................................................................................53 11.5 Program Resume ...............................................................................................53 11.6 Program Protection ............................................................................................53 12.0 Erase Operations......................................................................................................55 12.1 Block Erase .......................................................................................................55 12.2 Erase Suspend ..................................................................................................55 12.3 Erase Resume ...................................................................................................56 12.4 Erase Protection ................................................................................................56 13.0 Security Modes ........................................................................................................57 13.1 Block Locking ....................................................................................................57 13.1.1 Lock Block .............................................................................................57 13.1.2 Unlock Block ..........................................................................................57 13.1.3 Lock-Down Block ....................................................................................57 13.1.4 Block Lock Status ...................................................................................58 13.1.5 Block Locking During Suspend ..................................................................58 13.2 Protection Registers ...........................................................................................59 13.2.1 Reading the Protection Registers...............................................................60 13.2.2 Programming the Protection Registers .......................................................61 13.2.3 Locking the Protection Registers ...............................................................61 14.0 Dual-Operation Considerations ................................................................................62 14.1 Memory Partitioning ...........................................................................................62 14.2 Read-While-Write Command Sequences................................................................62 14.2.1 Simultaneous Operation Details ................................................................63 14.2.2 Synchronous and Asynchronous Read-While-Write Characteristics and Waveforms ............................................................................................63 14.2.2.1 Write operation to asynchronous read transition ............................63 14.2.2.2 Write to synchronous read operation transition..............................63 14.2.2.3 Write Operation with Clock Active ................................................64 14.2.3 Read Operation During Buffered Programming Flowchart..............................64 14.2.4 Simultaneous Operation Restrictions .........................................................64 15.0 Special Read States..................................................................................................66 15.1 Read Status Register..........................................................................................66 15.1.1 Clear Status Register ..............................................................................67 15.2 Read Device Identifier ........................................................................................67 15.3 CFI Query .........................................................................................................68 A B Write State Machine .................................................................................................69 Flowcharts ...............................................................................................................76 Datasheet 4 November 2007 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) B.1 B.2 B.3 B.4 B.5 B.6 C Common Flash Interface (CFI) ............................................................................ 83 Query Structure Output...................................................................................... 84 Query Structure Overview .................................................................................. 84 CFI Query Identification String ............................................................................ 85 Device Geometry Definition ................................................................................ 87 Intel-Specific Extended Query Table..................................................................... 88 Ordering Information .............................................................................................. 96 November 2007 313295-04 Datasheet 5 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Revision History Date May 2006 July 2006 August 2007 November 2007 Revision 001 002 003 04 Description Initial Release Removed Intel Confidential status. Updated ordering information Applied Numonyx branding. Datasheet 6 November 2007 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 1.0 Introduction This document provides information about the Numonyx™ StrataFlash® Wireless Memory (L18) with AD-Multiplexed I/O device. This document describes device features, operation, and specifications. The Numonyx™ StrataFlash® Wireless Memory (L18) with AD-Multiplexed I/O product is the latest generation of Intel StrataFlash® memory featuring flexible, multiplepartition, dual operation. It provides high performance asynchronous read mode and synchronous-burst read mode using 1.8 V low-voltage, multi-level cell (MLC) technology. The multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. This dual-operation architecture also allows two processors to interleave code operations while program and erase operations take place in the background. 8-Mbit partitions allow system designers to choose the size of the code and data segments. The Numonyx™ StrataFlash® Wireless Memory (L18) with AD-Multiplexed I/O device is manufactured using Intel 0.13 µm ETOX™ VIII process technology, available in industry-standard chip scale packaging. 1.1 1.8 V Nomenclature Vcc voltage range of 1.7 V – 2.0 V (except where noted) Vccq voltage range of 1.35 V – 2.0 V VPP voltage range of 8.5 V – 9.5 V 1.8 V Extended Range VPP = 9.0 V Block Main block Parameter block A group of bits, bytes or words within the flash memory array that erase simultaneously when the Erase command is issued to the device. The device has two block sizes: 16K-Word and 64K-Word. An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. An array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in EEPROM. Previously referred to as a top-boot device, a device with its parameter partition located at the highest physical address of its memory map. Parameter blocks within a parameter partition are located at the highest physical address of the parameter partition. A group of blocks that share common program/erase circuitry. Blocks within a partition also share a common status register. If any block within a partition is being programmed or erased, only status register data (rather than array data) is available when any address within that partition is read. A partition containing only main blocks. A partition containing parameter blocks and main blocks. Top parameter device Partition Main partition Parameter partition 1.2 CUI MLC OTP PLR PR Acronyms Command User Interface Multi-Level Cell One-Time Programmable Protection Lock Register Protection Register November 2007 Order Number: 313295-04 Datasheet 7 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) RCR SR WSM Read Configuration Register Status Register Write State Machine 1.3 VCC VCC Conventions Signal or voltage connection Signal or voltage level 0x 0b Hexadecimal number prefix Binary number prefix SR[4] A[15:0] A5 Denotes an individual register bit Denotes a group of similarly named signals, such as address or data bus bit byte word Binary unit Eight bits Two bytes, or sixteen bits Kbit KByte KWord Mbit MByte MWord 1024 bits 1024 bytes 1024 words 1,048,576 bits 1,048,576 bytes 1,048,576 words Datasheet 8 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 2.0 Functional Overview The Numonyx™ StrataFlash® Wireless Memory (L18) with AD-Multiplexed I/O device provides read-while-write and read-while-erase capability with density upgrades through 256-Mbit. This device provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Each device density contains one parameter partition and several main partitions. The flash memory array is grouped into multiple 8-Mbit partitions for the 64-Mbit and 128-Mbit devices, and into multiple 16-Mbit partitions for the 256-Mbit device. By dividing the flash memory into partitions, program or erase operations can take place at the same time as read operations. Although each partition has write, erase and burst read capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in read mode. The device allows burst reads that cross partition boundaries. User application code is responsible for ensuring that burst reads don’t cross into a partition that is programming or erasing. Upon initial power up or return from reset, the device defaults to asynchronous read mode. Configuring the Read Configuration Register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. Designed for lowvoltage systems, it supports read operations with VCC at 1.8 V, and erase and program operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (Buffered EFP) provides the fastest flash array programming performance with VPP at 9.0 V, which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP is less than VPPLK. A Command User Interface (CUI) is the interface between the system processor and all internal operations of the device. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments (x16). The Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) device offers power savings through Automatic Power Savings (APS) mode and standby mode. The device automatically enters APS following read-cycle completion. Standby is initiated when the system deselects the device by deasserting CE# or by asserting RST#. Combined, these features can significantly reduce power consumption. The device’s protection register allows unique flash device identification that can be used to increase system security. Also, the individual Block Lock feature provides zerolatency block locking and unlocking. November 2007 Order Number: 313295-04 Datasheet 9 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 3.0 Figure 1: Package Information 64- and 128-Mbit, 88-ball (80-active ball) (8x10x1.2 mm) A 1 Index M a rk 1 2 3 4 5 6 7 8 A B C D E D F G H J K L M b E e 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M S1 T o p V ie w - B a ll D o w n A2 A1 B o t t o m V ie w - B a ll Up A Y D r a w in g n o t to s c a le . D i m e n s io n s Pa c k a g e H e ig h t B a ll H e ig h t Pa c k a g e B o d y T h ic k n e s s B a ll (L e a d ) W id th Pa c k a g e B o d y L e n g th Pa c k a g e B o d y W id th Pitc h B a ll (L e a d ) C o u n t Se a tin g P la n e C o p la n a rity C o r n e r t o B a ll A 1 D is ta n c e A lo n g E C o r n e r t o B a ll A 1 D is ta n c e A lo n g D S y m bo l A A1 A2 b D E e N Y S1 S2 Min 0 .20 0 0 .32 5 9 .90 0 7 .90 0 M il li m e te r s N om M ax 1 .2 0 0 0.860 0.375 1 0 .0 0 0 8.000 0.800 88 1.200 0.600 Notes M in 0 .0 0 7 9 I nc h e s N om M ax 0.0472 0 .4 2 5 10 .1 0 0 8 .1 0 0 0 .0 1 2 8 0 .3 8 9 8 0 .3 1 1 0 0 .0 3 3 9 0 .0 1 4 8 0 .3 9 3 7 0 .3 1 5 0 0 .0 3 1 5 88 0 .0 4 7 2 0 .0 2 3 6 0.0167 0.3976 0.3189 1 .10 0 0 .50 0 0 .1 0 0 1 .3 0 0 0 .7 0 0 0 .0 4 3 3 0 .0 1 9 7 0.0039 0.0512 0.0276 Datasheet 10 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 2: 256-Mbit, 88-ball (80-active ball) (8x11x1.0 mm) A 1 In d e x M a rk 1 2 3 4 5 6 7 8 A B C D E D F G H J K L M b E 8 7 6 5 4 3 2 1 S1 S2 A B C D E F G H J K L M e T o p V ie w - B a ll D o w n A2 A1 B o t t o m V i e w - B a ll U p A Y D r a w in g n o t to s c a le . N o t e : D im e n s io n s A 1 , A 2 , a n d b a r e p r e lim in a r y D im e n s io n s P a c k a g e H e ig h t B a ll H e ig h t P a c k a g e B o d y T h ic k n e s s B a ll ( L e a d ) W id t h P ac ka g e B o d y Le n g th P a c k a g e B o d y W id t h P it c h B a ll ( L e a d ) C o u n t S e a t in g P la n e C o p la n a r it y C o r n e r t o B a ll A 1 D is t a n c e A lo n g E C o r n e r t o B a ll A 1 D is t a n c e A lo n g D S ym bol A A1 A2 b D E e N Y S1 S2 M in 0 .1 1 7 0 .3 0 0 1 0 .9 0 0 7 .9 0 0 0 .7 4 0 0 .3 5 0 1 1 .0 0 8 .0 0 0 .8 0 88 1 .2 0 0 1 .1 0 0 0 .4 0 0 1 1 .1 0 0 8 .1 0 0 M illim e te r s N om M ax 1 .0 0 N o te s M in 0 .0 0 4 6 0 .0 1 1 8 0 .4 2 9 1 0 .3 1 1 0 0 .0 2 9 1 0 .0 1 3 8 0 .4 3 3 1 0 .3 1 5 0 0 .0 3 1 5 88 0 .0 4 7 2 0 .0 4 3 3 0 .0 1 5 7 0 .4 3 7 0 0 .3 1 8 9 In c h e s N om M ax 0 .0 3 9 4 1 .1 0 0 1 .0 0 0 0 .1 0 0 1 .3 0 0 1 .2 0 0 0 .0 4 3 3 0 .0 3 9 4 0 .0 0 3 9 0 .0 5 1 2 0 .0 4 7 2 November 2007 Order Number: 313295-04 Datasheet 11 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 4.0 Table 1: Ballout and Signal Descriptions QUAD+ Ballout Pin 1 1 2 3 4 5 6 7 8 A DU DU DU DU A B A4 A18 A19 VSS F1-VCC F2-VCC A21 A11 B C A5 R-LB# A23 VSS S-CS2 CLK A22 A12 C D A3 A17 A24 F-VPP R-WE# P1-CS# A9 A13 D E A2 A7 A25 F-WP# ADV# A20 A10 A15 E F A1 A6 R-UB# F-RST# F-WE# A8 A14 A16 F G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G H R-OE# DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H J S-CS1# F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J K F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode# / P-CRE K L VSS VSS VCCQ F1-VCC VSS VSS VSS VSS L M DU DU DU DU M 1 2 3 4 5 6 7 8 Top View - Ball Side Down Legend: Active Signals De-Populated Balls Do Not Use Datasheet 12 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 4.1 Table 2: Symbol Signal Descriptions Signal Descriptions (Sheet 1 of 3) Type Signal Descriptions Note s Address and Data Signals, AD-Mux ADDRESS: Global device signals. Shared address inputs for all memory die during Read and Write operations. • 256-Mbit: AMAX = A23 • 128-Mbit: AMAX = A22 • 64-Mbit: AMAX = A21 • A0 is the lowest-order word address. • Unused address inputs should be treated as RFU. ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux I/O flash signals. During AD-Mux Read cycles, DQ[15:0] are used to input the lower address followed by read-data output. During AD-Mux Write cycles, DQ[15:0] are used to input the lower address followed by commands or data. • DQ[15:0] are High-Z when the device is deselected or its output is disabled. • DQ[15:0] is only used with AD-Mux I/O flash device. A[MAX:16 ] Input DQ[15:0] Input / Output 1 Control Signals ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input. • During a synchronous flash Read operation, the address is latched on the rising edge of ADV# or the first active CLK edge whichever occurs first. In an asynchronous flash Read operation, the address is latched on the rising edge of ADV# or continuously flows through while ADV# is low. • During synchronous PSRAM read and synchronous write modes, the address is either latched on the first rising clock edge after ADV# assertion or on the rising edge of ADV# whichever edge comes first. In asynchronous read and asynchronous write modes, ADV# can be used to latch the address, but can be held low for the entire operation as well. Note: During A/D-Mux I/O operation, ADV# must remain deasserted during the data phase. ADV# Input F[3:1]CE# Input FLASH CHIP ENABLE: Flash-specific signal; low-true input. When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT outputs are placed in a High-Z state. • F1-CE# is dedicated to flash die #1. • F[3:2]-CE# are dedicated to flash die #3 through #2, respectively, if present. Otherwise, any unused flash chip enable should be treated as RFU. CLOCK: Flash- and Synchronous PSRAM-specific input signal. CLK synchronizes the flash and/or synchronous PSRAM with the system clock during synchronous operations. FLASH OUTPUT ENABLE: Flash-specific signal; low-true input. When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE# disables the output drivers of the selected flash die and places the output drivers in High-Z. • F2-OE# common to all other flash dies, if present. Otherwise it is an RFU, however, it is highly recommended to always common F1-OE# and F2-OE# on the PCB. RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input. When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE# disables the output drivers of the selected memory die and places the output drivers in High-Z. If device not present, treat as RFU. FLASH RESET: Flash-specific signal; low-true input. When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables normal operation. CLK Input F[2:1]OE# Input R-OE# Input 2 F-RST# Input November 2007 Order Number: 313295-04 Datasheet 13 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 2: Symbol Signal Descriptions (Sheet 2 of 3) Type Signal Descriptions WAIT: Flash -and Synchronous PSRAM-specific signal; configurable true-level output. When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid output data. • WAIT is driven whenever the flash or the synchronous PSRAM is selected and its output enable is low. • WAIT is High-Z whenever flash or the synchronous PSRAM is deselected, or its output enable is high. FLASH WRITE ENABLE: Flash-specific signal; low-true input. When low, F-WE# enables Write operations for the enabled flash die. Address and data are latched on the rising edge of F-WE#. RAM WRITE ENABLE: PSRAM- and SRAM-specific signal; low-true input. When low, R-WE# enables Write operations for the selected memory die. Data is latched on the rising edge of R-WE#. If device not present, treat as RFU. FLASH WRITE PROTECT: Flash-specific signals; low-true inputs. When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the LockDown function, enabling locked-down blocks to be unlocked with the Unlock command. • F-WP1# is dedicated to flash die #1. • F-WP2# is common to all other flash dies, if present. Otherwise it is an RFU. PSRAM CONTROL REGISTER ENABLE: Synchronous PSRAM-specific signal; high-true input. When high, P-CRE enables access to the Refresh Control Register (P-RCR) or Bus Control Register (P-BCR). When low, P-CRE enables normal Read or Write operations. If PSRAM not present, treat as RFU. PSRAM MODE#: Asynchronous only PSRAM-specific signal; low-true input. When low, P-MODE# enables access to the configuration register, and to enter or exit Low-Power mode. When high, P-MODE# enables normal Read or Write operations. If PSRAM not present, treat as RFU. PSRAM CHIP SELECT: PSRAM-specific signal; low-true input. When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT outputs are placed in a High-Z state. • P1-CS# is dedicated to PSRAM die #1. If PSRAM not present, treat as RFU. • P2-CS# is dedicated to PSRAM die #2. If PSRAM not present, treat as RFU. SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input. When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or S-CS2 is deasserted, the SRAM die is deselected. • S-CS1# and S-CS2 are dedicated to SRAM when present. If SRAM not present, treat as RFU. RAM UPPER/LOWER BYTE ENABLES: PSRAM- and SRAM-specific signals; low-true inputs. When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read and Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0]. If device not present, treat as RFU./ 2 Note s WAIT Output F-WE# Input R-WE# Input F-WP# Input P-CRE Input 3 P-MODE# Input 3 P[2:1]CS# Input S-CS1# S-CS2 Input 2 R-UB# R-LB# Input 2 Power Signals F-VPP F[2:1]VCC VCCQ P-VCC S-VCC Power FLASH PROGRAM/ERASE VOLTAGE: Flash specific. F-VPP supplies program or erase power to the flash die. FLASH CORE POWER SUPPLY: Flash specific. F[2:1]-VCC supplies the core power to the flash die. F2-VCC is recommended to be tied to F1-VCC, else it is an RFU. I/O POWER SUPPLY: Global device I/O power. VCCQ supplies the device input/output driver voltage. PSRAM CORE POWER SUPPLY: PSRAM specific. P-VCC supplies the core power to the PSRAM die. If PSRAM not present, treat as RFU. SRAM POWER SUPPLY: SRAM specific. S-VCC supplies the core power to the SRAM die. If SRAM not present, treat as RFU. 2 2 Power Power Power Power Datasheet 14 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 2: Symbol VSS Signal Descriptions (Sheet 3 of 3) Type Groun d — Signal Descriptions DEVICE GROUND: Global ground reference for all signals and power supplies. Connect all VSS balls to system ground. Do not float any VSS connections. DO NOT USE: This ball should not be connected to any power supplies, signals, or other balls. This ball can be left floating. RESERVED for FUTURE USE: Reserved by Intel for future device functionality and enhancement. This ball must be left floating. Note s DU RFU — Notes: 1. Only used when AD-Mux I/O flash is present. 2. Only available on stacked device combinations with PSRAM, and/or SRAM die. Otherwise treated as RFU. 3. P-CRE and P-MODE# share the same package ball at location K8. Only one signal function is available, depending on the stacked device combination. 4.2 Memory Map The 64Mb and 128Mb memory array is divided into multiple 8-Mbit partitions. Each device density contains one parameter partition and several main partitions. The 8-Mbit top parameter partition contains four 16K-Word blocks and seven 64K-Word blocks. There are multiple 8-Mbit main partitions. The 8-Mbit main partitions each contains eight 64K-Word blocks. The device multi-partition architecture is divided as follow: • The 64-Mbit device contains eight partitions: one 8-Mbit parameter partition, seven 8-Mbit main partitions. • The 128-Mbit device contains sixteen partitions: one 8-Mbit parameter partition, fifteen 8-Mbit main partitions. The 256Mb memory array is divided into multiple 16-Mbit partitions. Each device contains one parameter partition and fifteen main partitions. The 16-Mbit top parameter partition contains four 16K-Word blocks and fifteen 64K-Word blocks. There are fifteen 16-Mbit main partitions. The 16-Mbit main partitions each contains sixteen 64K-Word blocks. Table 3: Top Parameter Memory Map, 128-Mbit (Sheet 1 of 2) Size (KW) Blk 43 16 66 65 64 63 62 … 3FC000-3FFFFF 8-Mbit Parameter Partition 3F8000-3FBFFF 3F4000-3F7FFF 3F0000-3F3FFF 3E0000-3EFFFF … One Partition 16 16 16 16 64 … 130 129 128 127 126 … 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF … 780000-78FFFF Datasheet 15 64-Mbit Size (KW) Blk 128-Mbit 8-Mbit Parameter Partition 16 One Partition 16 16 64 … 64 56 380000-38FFFF 64 120 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 3: Top Parameter Memory Map, 128-Mbit (Sheet 2 of 2) Size (KW) Blk 43 Seven Partitions 8-Mbit Main Partitions Fifteen Partitions 64-Mbit Size (KW) Blk 128-Mbit 8-Mbit Main Partition 64 … 55 … 370000-37FFFF … 64 … 119 770000-77FFFF 64 0 000000-00FFFF 64 64 … 0 000000-00FFFF Sixteen Partitions 64 Table 4: Top Parameter Memory Map, 256-Mbit Size (KW) Blk 256-Mbit 16 16-Mbit Parameter Partition 16 One Partition 16 16 64 … 258 257 256 253 254 … FFC000-FFFFFF FF8000-FFBFFF FF4000-FF7FFF FF0000-FF3FFF FE0000-FEFFFF … F00000-FFFFFF EF0000-EFFFFF 800000-80FFFF 7F0000-7FFFFF 000000-00FFFF November 2007 Order Number: 313295-04 64 16-Mbit Main Partitions Seven Partitions 64 … 240 239 64 64 … 128 127 Eight Partitions 64 0 Datasheet 16 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 5.0 5.1 Warning: Table 5: Maximum Ratings and Operating Conditions Absolute Maximum Ratings Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Absolute Maximum Ratings Table Parameter Maximum Rating –25 °C –65 °C Notes Temperature under bias Storage temperature Voltage on any signal (except VCC, VPP) VPP voltage VCC voltage VCCQ voltage Output short circuit current to +85 °C to +125 °C –0.5 V to +2.5 V –0.2 V to +10 V –0.2 V to +2.5 V –0.2 V to +2.5 V 100 mA 1 1,2,3 1 1 4 Notes: 1. Voltages shown are specified with respect to VSS. Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0 V for periods One CLK Period (ns), data hold setting of 2 clock periods must be used. Figure 18: Data Hold Timing CLK [C] 1 CLK Data Hold 2 CLK Data Hold 10.3.5 AD[15:0] [Q] Valid Output Valid Output Valid Output AD[15:0] [Q] WAIT Delay Valid Output Valid Output The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst reads. WAIT can be asserted either during or one data cycle before valid data is output on AD[15:0]. When WD is set, WAIT is de-asserted one data cycle before valid data (default). When WD is cleared, WAIT is de-asserted during valid data. Datasheet 46 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 10.3.6 Burst Sequence The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. Table 23 shows the synchronous burst sequence for all burst lengths, as well as the effect of the Burst Wrap (BW) setting. Table 23: Burst Sequence Word Ordering Burst Addressing Sequence (DEC) Start Addr. (DEC) 0 1 2 3 4 5 6 7 … Burst Wrap (RCR[3]) 0 0 0 0 0 0 0 0 … … 4-Word Burst (BL[2:0] = 0b001) 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8-Word Burst (BL[2:0] = 0b010) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 … 16-Word Burst (BL[2:0] = 0b011) 0-1-2-3-4…14-15 1-2-3-4-5…15-0 2-3-4-5-6…15-0-1 3-4-5-6-7…15-0-1-2 4-5-6-7-8…15-0-1-2-3 5-6-7-8-9…15-0-1-2-3-4 6-7-8-9-10…15-0-1-2-34-5 7-8-9-10…15-0-1-2-3-45-6 … 14-15-0-1-2…12-13 15-0-1-2-3…13-14 … … … Continuous Burst (BL[2:0] = 0b111) 0-1-2-3-4-5-6-… 1-2-3-4-5-6-7-… 2-3-4-5-6-7-8-… 3-4-5-6-7-8-9-… 4-5-6-7-8-9-10… 5-6-7-8-9-10-11… 6-7-8-9-10-11-12-… 7-8-9-10-11-12-13… … 14-15-16-17-18-19-20-… 15-16-17-18-19-20-21-… … 14 15 … 0 1 2 3 4 5 6 7 … 14 15 0 0 … 1 1 1 1 1 1 1 1 … 1 1 … 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-1314 … 0-1-2-3-4…14-15 1-2-3-4-5…15-16 2-3-4-5-6…16-17 3-4-5-6-7…17-18 4-5-6-7-8…18-19 5-6-7-8-9…19-20 6-7-8-9-10…20-21 7-8-9-10-11…21-22 … 14-15-16-17-18…28-29 15-16-17-18-19…29-30 0-1-2-3-4-5-6-… 1-2-3-4-5-6-7-… 2-3-4-5-6-7-8-… 3-4-5-6-7-8-9-… 4-5-6-7-8-9-10… 5-6-7-8-9-10-11… 6-7-8-9-10-11-12-… 7-8-9-10-11-12-13… … 14-15-16-17-18-19-20-… 15-16-17-18-19-20-21-… 10.3.7 Clock Edge The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT. November 2007 Order Number: 313295-04 Datasheet 47 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 10.3.8 Burst Wrap The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross over to the next burst-length segment. When BW is set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs. When performing synchronous burst reads with BW set (no wrap), an output delay may occur when the burst sequence crosses its first device-row (16-word) boundary. If the burst sequence’s start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT informs the system of this delay when it occurs. 10.3.9 Burst Length The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 23, “Burst Sequence Word Ordering” on page 47). When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the “burstable” address space. Datasheet 48 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 11.0 Programming Operations The device supports three programming methods: word programming, buffered programming, and Buffered Enhanced Factory Programming (Buffered EFP). See Section 9.0, “Device Operations” on page 36 for details on the various programming commands issued to the device. Successful programming requires the addressed block to be unlocked. If the block is locked down, WP# must be deasserted and the block unlocked before attempting to program the block. Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and termination of the operation. See Section 13.0, “Security Modes” on page 57 for details on locking and unlocking blocks. The following sections describe device programming in detail. 11.1 Word Programming Word programming operations are initiated by writing the Word Program Setup command to the device (see Section 9.0, “Device Operations” on page 36). This is followed by a second write to the device with the address and data to be programmed. The partition accessed during both write cycles outputs Status Register data when read. The partition accessed during the second cycle (the data cycle) of the program command sequence is the location where the data is written. See Figure 31, “Word Program Flowchart” on page 76. Programming can occur in only one partition at a time; all other partitions must be in a read state or in erase suspend. VPP must be above VPPLK, and within the specified VPPL min/max values (nominally 1.8 V). During programming, the Write State Machine (WSM) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. Programming the flash memory array changes “ones” to “zeros.” Memory array bits that are zeros can be changed to ones only by erasing the block (see Section 12.0, “Erase Operations” on page 55). The Status Register can be examined for programming progress and errors by reading any address within the partition that is being programmed. The partition remains in the Read Status Register state until another command is written to that partition. Issuing the Read Status Register command to another partition address sets that partition to the Read Status Register state, allowing programming progress to be monitored at that partition’s address. Status Register bit SR[7] indicates the programming status while the sequence executes. Commands that can be issued to the programming partition during programming are Program Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read Array (this returns unknown data). In asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV# must be toggled to update status data. When programming has finished, Status Register bit SR[4] (when set) indicates a programming failure. If SR[3] is set, the WSM could not perform the word programming operation because VPP was outside of its acceptable limits. If SR[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow, when word programming has completed. November 2007 Order Number: 313295-04 Datasheet 49 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 11.1.1 Factory Word Programming Factory word programming is similar to word programming in that it uses the same commands and programming algorithms. However, factory word programming enhances the programming performance with VPP = VPPH. This can enable faster programming times during OEM manufacturing processes. Factory word programming is not intended for extended use. See Section 5.2, “Operating Conditions” on page 17 for limitations when VPP = VPPH. Note: When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is driven by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH, the device draws programming current from the VPP supply. Figure 19, “Example VPP Supply Connections” on page 54 shows examples of device power supply configurations. 11.2 Buffered Programming The device features a 32-word buffer to enable optimum programming performance. For buffered programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. When the Buffered Programming Setup command is issued (see Section 9.2, “Device Commands” on page 37), Status Register information is updated and reflects the availability of the write buffer. SR[7] indicates buffer availability: if set, the buffer is available; if cleared, the write buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is set, the buffer is ready for loading. (see Figure 33, “Buffer Program Flowchart” on page 78). On the next write, a word count is written to the device at the buffer address. This tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address plus the word count. Optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will double the total programming time. After the last data is written to the buffer, the Buffered Programming Confirm command is issued to the original block address. The WSM begins to program buffer contents to the flash memory array. If a command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4] are set, indicating a programming failure. Reading from another partition is allowed while data is being programmed into the array from the write buffer (see Section 14.0, “Dual-Operation Considerations” on page 62). Additional buffer writes can be initiated by issuing another Buffered Programming Setup command and repeating the buffered program sequence. Buffered programming may be performed with VPP = VPPL or VPPH (see Section 5.2, “Operating Conditions” on page 17 for limitations when operating the device with VPP = VPPH). Datasheet 50 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) If an attempt is made to program past an erase-block boundary using the Buffered Program command, the device aborts the operation. This generates a command sequence error, and Status Register bits SR[5,4] are set. If Buffered programming is attempted while VPP is below VPPLK, Status Register bits SR[4,3] are set. If any errors are detected that have set Status Register bits, the Status Register should be cleared using the Clear Status Register command. 11.3 Buffered Enhanced Factory Programming Buffered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC) flash programming for today's beat-rate-sensitive manufacturing environments. The enhanced programming algorithm used in Buffered EFP eliminates traditional programming elements that drive up overhead in device programmer systems. Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 34, “Buffered EFP Flowchart” on page 79). It uses a write buffer to spread MLC program performance across 32 data words. Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. A single command sequence is used to program a block of data. This enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. Host programmer bus cycles fill the device’s write buffer followed by a status check. SR[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. Following the buffer-to-flash array programming sequence, the Write State Machine (WSM) increments internal addressing to automatically select the next 32-word array boundary. This aspect of Buffered EFP saves host programming equipment the addressbus setup overhead. With adequate continuity testing, programming equipment can rely on the WSM’s internal verification to ensure that the device has programmed properly. This eliminates the external post-program verification and its associated overhead. 11.3.1 Buffered EFP Requirements and Considerations Buffered EFP requirements: • Ambient temperature: TC = 25°C, ±5°C • VCC within specified operating range. • VPP driven to VPPH. • Target block unlocked before issuing the Buffered EFP Setup and Confirm commands. • The first-word address (WA0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired. • WA0 must align with the start of an array buffer boundary1. Buffered EFP considerations: • For optimum performance, cycling must be limited below 100 erase cycles per block2. • Buffered EFP programs one block at a time; all buffer data must fall within a single block3. • Buffered EFP cannot be suspended. • Programming to the flash memory array can occur only when the buffer is full4. November 2007 Order Number: 313295-04 Datasheet 51 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Notes: 1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00. 2. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 3. If the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. If the number of words is less than 32, remaining locations must be filled with 0xFFFF. • Read operation while performing Buffered EFP is not supported. 11.3.2 Buffered EFP Setup Phase After receiving the Buffered EFP Setup and Confirm command sequence, Status Register bit SR[7] (Ready) is cleared, indicating that the WSM is busy with Buffered EFP algorithm startup. A delay before checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR[4] is set and Buffered EFP operation terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred due to an incorrect VPP level. Note: Reading from the device after the Buffered EFP Setup and Confirm command sequence outputs Status Register data. Do not issue the Read Status Register command; it will be interpreted as data to be loaded into the buffer. 11.3.3 Buffered EFP Program/Verify Phase After the Buffered EFP Setup Phase has completed, the host programming system must check SR[7,0] to determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device is busy and the Buffered EFP program/verify phase is activated. SR[0] indicates the write buffer is available. Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. For Buffered EFP, the count value for buffer loading is always the maximum buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF. Caution: The buffer must be completely filled for programming to occur. Supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any data previously loaded into the buffer during the fill cycle is not programmed into the array. The starting address for data entry must be buffer size aligned, if not the Buffered EFP algorithm will be aborted and the program fail (SR[4]) flag will be set. Data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. The host programming system must poll SR[0] to determine when the buffer program sequence completes. SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set indicates that the buffer is not available yet for the next fill cycle. The host system may check full status for errors at any time, but it is only necessary on a block basis after Buffered EFP exit. The host programming system continues the Buffered EFP algorithm by providing the next group of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the block address to one outside of the current block’s range. The Program/Verify phase concludes when the programmer writes to a different block address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the Buffered EFP Exit phase. Datasheet 52 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 11.3.4 Buffered EFP Exit Phase When SR[7] is set, the device has returned to normal operating conditions. A full status check should be performed at this time to ensure the entire block programmed successfully. After Buffered EFP exit, any valid command can be issued to the device. 11.4 Program Suspend Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from memory locations other than the one being programmed. The Program Suspend command can be issued to any device address; the corresponding partition is not affected. A program operation can be suspended to perform reads only. Additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see Figure 32, “Program Suspend/Resume Flowchart” on page 77). When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at predetermined points. The partition that is suspended continues to output Status Register data after the Program Suspend command is issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend latency is specified in Section 7.7, “Program and Erase Characteristics” on page 32. To read data from blocks within the suspended partition, the Read Array command must be issued to that partition. Read Array, Read Status Register, Read Device Identifier, CFI Query, program RCR and Program Resume are valid commands during a program suspend. A program operation does not need to be suspended in order to read data from a block in another partition that is not programming. If the other partition is already in a Read Array, Read Device Identifier, or CFI Query state, issuing a valid address returns corresponding read data. If the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. During a program suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at its programming level, and WP# must remain unchanged while in program suspend. If RST# is asserted, the device is reset. 11.5 Program Resume The Resume command instructs the device to continue programming, and automatically clears Status Register bits SR[7,2]. This command can be written to any partition. When read at the partition that’s programming, the device outputs data corresponding to the partition’s last state. If error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 32, “Program Suspend/Resume Flowchart” on page 77). 11.6 Program Protection When VPP = VIL, absolute hardware write protection is provided for all device blocks. If VPP is below VPPLK, programming operations halt and SR[3] is set indicating a VPP-level error. Block lock registers are not affected by the voltage level on VPP; they may still be programmed and read, even if VPP is less than VPPLK. November 2007 Order Number: 313295-04 Datasheet 53 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 19: Example VPP Supply Connections VCC VPP ≤ 10K Ω VCC VPP VCC PROT # VCC VPP • Factory Programming with VPP = VPPH • Complete write/Erase Protection when VPP ≤ VPPLK • Low-voltage Programming only • Logic Control of Device Protection VCC VPP=VPPH VCC VPP VCC VCC VPP • Low Voltage and Factory Programming • Low Voltage Programming Only • Full Device Protection Unavailable Datasheet 54 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 12.0 Erase Operations Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail. 12.1 Block Erase Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to be erased (see Section 9.2, “Device Commands” on page 37). Next, the Block Erase Confirm command is written to the address of the block to be erased. Erasing can occur in only one partition at a time; all other partitions must be in a read state. If the device is placed in standby (CE# deasserted) during an erase operation, the device completes the erase operation before entering standby.VPP must be above VPPLK and the block must be unlocked (see Figure 35, “Block Erase Flowchart” on page 80). During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes “zeros” to “ones.” Memory array bits that are ones can be changed to zeros only by programming the block (see Section 11.0, “Programming Operations” on page 49). The Status Register can be examined for block erase progress and errors by reading any address within the partition that is being erased. The partition remains in the Read Status Register state until another command is written to that partition. Issuing the Read Status Register command to another partition address sets that partition to the Read Status Register state, allowing erase progress to be monitored at that partition’s address. SR[0] indicates whether the addressed partition or another partition is erasing. The partition’s Status Register bit SR[7] is set upon erase completion. Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would indicate that the WSM could not perform the erase operation because VPP was outside of its acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. CE# or OE# must be toggled to update Status Register contents. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow once the block erase operation has completed. 12.2 Erase Suspend Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address; the corresponding partition is not affected. A block erase operation can be suspended to perform a word or write-buffer program operation, or a read operation within any block except the block that is erase suspended (see Figure 32, “Program Suspend/Resume Flowchart” on page 77). When a block erase operation is executing, issuing the Erase Suspend command requests the WSM to suspend the erase algorithm at predetermined points. The partition that is suspended continues to output Status Register data after the Erase Suspend command is issued. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 7.7, “Program and Erase Characteristics” on page 32. November 2007 Order Number: 313295-04 Datasheet 55 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) To read data from blocks within the suspended partition (other than an erasesuspended block), the Read Array command must be issued to that partition first. During Erase Suspend, a Program command can be issued to any block other than the erase-suspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. To read data from a block in a partition that is not erasing, the erase operation does not need to be suspended. If the other partition is already in Read Array, Read Device Identifier, or CFI Query, issuing a valid address returns corresponding data. If the other partition is not in a read state, one of the read commands must be issued to the partition before data can be read. During an erase suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at a valid level, and WP# must remain unchanged while in erase suspend. If RST# is asserted, the device is reset. 12.3 Erase Resume The Erase Resume command instructs the device to continue erasing, and automatically clears status register bits SR[7,6]. This command can be written to any partition. When read at the partition that’s erasing, the device outputs data corresponding to the partition’s last state. If status register error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 32, “Program Suspend/Resume Flowchart” on page 77). 12.4 Erase Protection When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If VPP is below VPPLK, erase operations halt and SR[3] is set indicating a VPP-level error. Datasheet 56 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 13.0 Security Modes The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail. 13.1 Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power up in a locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. Software-controlled security is implemented using the Block Lock and Block Unlock commands. Hardware-controlled security can be implemented using the Block LockDown command along with asserting WP#. Also, VPP data security can be used to inhibit program and erase operations (see Section 11.6, “Program Protection” on page 53 and Section 12.4, “Erase Protection” on page 56). 13.1.1 Lock Block To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command issued to the desired block’s address (see Section 9.2, “Device Commands” on page 37 and Figure 37, “Block Lock Operations Flowchart” on page 82). If the Set Read Configuration Register command is issued after the Block Lock Setup command, the device configures the RCR instead. Block lock and unlock operations are not affected by the voltage level on VPP. The block lock bits may be modified and/or read even if VPP is below VPPLK. Table 24: Block Locking V PP X ≤ VPPLK ≤ VPPLK > VPPLK > VPPLK WP# X VIL VIH VIL VIH RST# VIL VIH VIH VIH VIH Block Write Protection All blocks write/erase protected All blocks write/erase protected All blocks write/erase protected All Lock-Down and Locked blocks write/ erase protected All Lock-Down and Locked blocks write/ erase protected Block Lock Bits Block lock bits may not be changed Lock-Down block states may not be changed All Lock-Down block states may be changed Lock-Down block states may not be changed All Lock-Down block states may be changed 13.1.2 Unlock Block The Unlock Block command is used to unlock blocks (see Section 9.2, “Device Commands” on page 37). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a locked state when the device is reset or powered down. If a block is in a lock-down state, WP# must be deasserted before it can be unlocked (see Figure 20, “Block Locking State Diagram” on page 58). 13.1.3 Lock-Down Block A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence (see Section 9.2, “Device Commands” on page 37). Blocks in a lock-down state cannot be programmed or erased; they can only be read. However, unlike locked blocks, their locked state cannot be changed by software commands November 2007 Order Number: 313295-04 Datasheet 57 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) alone. A locked-down block can only be unlocked by issuing the Unlock Block command with WP# deasserted. To return an unlocked block to locked-down state, a Lock command (60h/01h) must be issued prior to changing WP# to VIL. A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence. Locked-down blocks revert to the locked state upon reset or power up the device (see Figure 20, “Block Locking State Diagram” on page 58). 13.1.4 Block Lock Status The Read Device Identifier command is used to determine a block’s lock status (see Section 15.2, “Read Device Identifier” on page 67). Data bits AD[1:0] display the addressed block’s lock status; AD0 is the addressed block’s lock bit, while AD1 is the addressed block’s lock-down bit. Figure 20: Block Locking State Diagram Unlocked Unlock Cmd Lock Cmd Locked Unlocked [000] Locked [001] Power-Up/ Reset Default Lock-Down Cmd WP# Asserted Lock-Down Cmd Locked -Down [011] WP# De-Asserted WP# A/DQ1 A/DQ0 Unlocked [110] Unlock Cmd Lock-Down Cmd Locked [111] x x 0 1 1 0 0 1 1 1 0 1 1 0 1 Block Status Unlocked Locked Locked-Down Unlocked Locked Lock-Down Cmd Lock-Down Cmd Unlock Cmd Lock Cmd Power-Up/ Reset Default Unlocked [100] Locked [101] 13.1.5 Block Locking During Suspend Block lock and unlock changes can be performed during an erase suspend. To change block locking during an erase operation, first issue the Erase Suspend command. Monitor the Status Register until SR[7] and SR[6] are set, indicating the device is suspended and ready to accept another command. Next, write the desired lock command sequence to a block, which changes the lock state of that block. After completing block lock or unlock operations, resume the erase operation using the Erase Resume command. Datasheet 58 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block, or Lock-Down Block produces a command sequence error and set Status Register bits SR[4] and SR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set, even after the erase operation is resumed. Unless the Status Register is cleared using the Clear Status Register command before resuming the erase operation, possible erase errors may be masked by the command sequence error. If a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. However, the erase operation completes when it is resumed. Block lock operations cannot occur during a program suspend. See Appendix A, “Write State Machine” on page 69, which shows valid commands during an erase suspend. 13.2 Protection Registers The device contains 17 Protection Registers (PRs) that can be used to implement system security measures and/or device identification. Each Protection Register can be individually locked. The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64-bit segment is pre-programmed at the factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the Protection Register(s) to prevent additional bit programming (see Figure 21, “Protection Register Map” on page 60). The user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot be erased. Each Protection Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each Protection Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated Protection Register can only be read; it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be unlocked. November 2007 Order Number: 313295-04 Datasheet 59 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 21: Protection Register Map 0x109 128-bit Protection Register 16 (User-Programmable) 0x102 0x91 128-bit Protection Register 1 (User-Programmable) 0x8A Lock Register 1 0x89 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x88 0x85 0x84 0x81 0x80 64-bit Segment (User-Programmable) 128-Bit Protection Register 0 64-bit Segment (Factory-Programmed) Lock Register 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 . 13.2.1 Reading the Protection Registers The Protection Registers can be read from within any partition’s address space. To read the Protection Register, first issue the Read Device Identifier command at any partitions’ address to place that partition in the Read Device Identifier state (see Section 9.2, “Device Commands” on page 37). Next, perform a read operation at that partition’s base address plus the address offset corresponding to the register to be read. Table 27, “Device Identifier Information” on page 67 shows the address offsets of the Protection Registers and Lock Registers. Register data is read 16 bits at a time. Note: If a program or erase operation occurs within the device while it is reading a Protection Register, certain restrictions may apply. See Table 25, “Simultaneous Operation Restrictions” on page 65 for details. Datasheet 60 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 13.2.2 Programming the Protection Registers To program any of the Protection Registers, first issue the Program Protection Register command at the parameter partition’s base address plus the offset to the desired Protection Register (see Section 9.2, “Device Commands” on page 37). Next, write the desired Protection Register data to the same Protection Register address (see Figure 21, “Protection Register Map” on page 60). The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at a time (see Figure 38, “Protection Register Programming Flowchart” on page 83). Issuing the Program Protection Register command outside of the Protection Register’s address space causes a program error (SR[4] set). Attempting to program a locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1] set). Note: If a program or erase operation occurs when programming a Protection Register, certain restrictions may apply. See Table 25, “Simultaneous Operation Restrictions” on page 65 for details. 13.2.3 Locking the Protection Registers Each Protection Register can be locked by programming its respective lock bit in the Lock Register. To lock a Protection Register, program the corresponding bit in the Lock Register by issuing the Program Lock Register command, followed by the desired Lock Register data (see Section 9.2, “Device Commands” on page 37). The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock registers (see Table 27, “Device Identifier Information” on page 67). Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, preprogrammed 64-bit region of the first 128-bit Protection Register containing the unique identification number of the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit Protection Register. The other bits in Lock Register 0 are not used. Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register. Caution: After being locked, the Protection Registers cannot be unlocked. November 2007 Order Number: 313295-04 Datasheet 61 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 14.0 Dual-Operation Considerations The multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. 14.1 Memory Partitioning The flash memory array is divided into multiple 8-Mbit partitions, which allows simultaneous read-while-write operations. Simultaneous program and erase is not allowed. Only one partition at a time can be in program or erase mode. The flash device supports read-while-write operations with bus cycle granularity and not command granularity. In other words, it is not assumed that both bus cycles of a two cycle command (an erase command for example) will always occur as back to back bus cycles to the flash device. In practice, code fetches (reads) may be interspersed between write cycles to the flash device, and they will likely be directed to a different partition than the one being written. This is especially true when a processor is executing code from one partition that instructs the processor to program or erase in another partition. 14.2 Read-While-Write Command Sequences When issuing commands to the device, a read operation can occur between 2-cycle Write command’s (Figure 22, and Figure 23). However, a write operation issued between a 2-cycle commands write sequence causes a command sequence error. (See Figure 24) When reading from the same partition after issuing a Setup command, Status Register data is returned, regardless of the read mode of the partition prior to issuing the Setup command. Figure 22: Operating Mode with Correct Command Sequence Example Address/Data [A/D] ADV# CE# WE# [W] OE# [G] Partition A Data: 0x20 Partition A Data: 0xD0 Partition B Data: 0xFF Datasheet 62 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 23: Operating Mode with Correct Command Sequence Example Addr/Data [A/D] ADV# CE# WE# [W] OE# [G] P artition A Data: 0x20 Partition B Array Data Partition A Data: 0xD0 Figure 24: Operating Mode with Illegal Command Sequence Example A ddr/Data [A/D] ADV# CE# WE# [W] OE# [G] Part. A Data: 0x20 Part. B Data: 0xFF Part. A Data: 0xD0 Part. A Data: S R 14.2.1 Simultaneous Operation Details The L18 device supports simultaneous read from one partition while programming or erasing in any other partition. Certain features like the Protection Registers and CFI Query data have special requirements with respect to simultaneous operation capability. (Table 25 provides details on restrictions during simultaneous operations.) 14.2.2 Synchronous and Asynchronous Read-While-Write Characteristics and Waveforms This section describes the transitions of write operation to asynchronous read, write to synchronous read, and write operation with clock active. 14.2.2.1 Write operation to asynchronous read transition W18 - tWHAV The AC parameter W18 (tWHAV-WE# High to Address Valid) is required when transitioning from a write cycle (WE# going high) to perform an asynchronous read (only address valid is required). 14.2.2.2 Write to synchronous read operation transition W19 and W20 - tWHCV and tWHVH The AC parameters W19 or W20 (tWHCV-WE# High to Clock Valid, and tWHVH - WE# High to ADV# High) is required when transitioning from a write cycle (WE# going high) to perform a synchronous burst read. A delay from WE# going high to a valid clock edge or ADV# going high to latch a new address must be met. November 2007 Order Number: 313295-04 Datasheet 63 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 14.2.2.3 Write Operation with Clock Active W21 - tVHWL W22 - tCHWL The AC parameters W21 (tVHWL- ADV# High to WE# Low) and W22 (tCHWL -Clock high to WE# low) are required when the device is in a synchronous mode and clock is active. A write bus cycle consists of two parts: • the host provides an address to the flash device; and • the host then provides data to the flash device. The flash device in turn binds the received data with the received address. When operating synchronously (RCR.15 = 0), the address of a write cycle may be provided to the flash by the first active clock edge with ADV# low, or rising edge of ADV# as long as the applicable cycle separation conditions are met between each cycle. If neither a clock edge nor a rising ADV# edge is used to provide a new address at the beginning of a write cycle (the clock is stopped and ADV# is low), the address may also be provided to the flash device by holding the address bus stable for the required amount of time (W5, tAVWH) before the rising WE# edge. Alternatively, the host may choose not to provide an address to the flash device during subsequent write cycles (if ADV# is high and only CE# or WE# is toggled to separate the prior cycle from the current write cycle). In this case, the flash device will use the most recently provided address from the host. Refer to Figure 11, “Write to Asynchronous Read Timing” on page 28, Figure 12, “Synchronous Read to Write Timing” on page 29, and Figure 13, “Write to Synchronous Read” on page 30, for representation of these timings. 14.2.3 Read Operation During Buffered Programming Flowchart The multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. To perform a read while buffered programming operation, first issue a Buffered Program set up command in a partition. When a read operation occurs in the same partition after issuing a setup command, Status Register data will be returned, regardless of the read mode of the partition prior to issuing the setup command. To read data from a block in other partition and the other partition already in read array mode, a new block address must be issued. However, if the other partition is not already in read array mode, issuing a read array command will cause the buffered program operation to abort and a command sequence error would be posted in the Status Register. See Figure 33, “Buffer Program Flowchart” on page 78 for more details. Note: Simultaneous read-while-Buffered EFP is not supported. 14.2.4 Simultaneous Operation Restrictions The Protection Registers share some of the same internal flash resources as the parameter partition. Therefore, simultaneous read-while-write is only allowed between the protection register and main partitions. Table 25 describes the operation allowed using read-while-write/erase with the protection register. Datasheet 64 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 25: Simultaneous Operation Restrictions Protection Register or CFI data Parameter Partition Array Data Other Partitions Notes While programming or erasing in a main partition, the Protection Register or CFI data may be read from any other partition. Reading the parameter partition array data is not allowed if the Protection Register or Query data is being read from addresses within the parameter partition. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the Protection Registers or CFI data from parameter partition addresses is not allowed when reading array data from the parameter partition. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the Protection Registers or CFI data in a partition that is different from the one being programed/erased, and also different from the parameter partition is allowed. While programming the Protection Register, reads are only allowed in the other main partitions. Access to array data in the parameter partition is not allowed. Programming of the Protection Register can only occur in the parameter partition, which means this partition is in Read Status. While programming or erasing the parameter partition, reads of the Protection Registers or CFI data are not allowed in any partition. Reads in partitions other than the parameter partition are supported. Read (See Notes) Write/Erase (See Notes) Read Write/Erase Read Read Write/Erase Write No Access Allowed Read No Access Allowed Write/Erase Read November 2007 Order Number: 313295-04 Datasheet 65 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 15.0 Special Read States The following sections describe non-array read states. Non-array reads can be performed in asynchronous read or synchronous burst mode. A non-array read operation is exactly the same as an array read. However, when using synchronous burst mode for non-array reads, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. The “flowthrough” feature also applies to synchronous non-array reads. Refer to Section 10.3.1, “Read Mode” on page 43 for details. 15.1 Read Status Register The status of any partition is determined by reading the Status Register from the address of that particular partition. To read the Status Register, issue the Read Status Register command within the desired partition’s address range. Status Register information is available at the partition address to which the Read Status Register, Word Program, or Block Erase command was issued. Status Register data is automatically made available following a Word Program, Block Erase, or Block Lock command sequence. Reads from a partition after any of these command sequences outputs that partition’s status until another valid command is written to that partition (e.g. Read Array command). Status Register data is output on AD[7:0], while 0x00 is output on AD[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV# must be toggled to update status data. Status Register read operations do not affect the read state of the other partitions. The Device Write Status bit (SR[7]) provides overall status of the device. The Partition Status bit (SR[0]) indicates whether the addressed partition or some other partition is actively programming or erasing. Status register bits SR[6:1] present status and error information about the program, erase, suspend, VPP, and block-locked operations. Table 26: Status Register Description (Sheet 1 of 2) Status Register (SR) Device Write Status DWS 7 Bit 7 6 5 4 3 Erase Suspend Status ESS 6 Name Device Write Status (DWS) Erase Suspend Status (ESS) Erase Status (ES) Program Status (PS) VPP Status (VPPS) Erase Status ES 5 Program Status PS 4 VPP Status VPPS 3 Program Suspend Status PSS 2 Description 0 = Device is busy; program or erase cycle in progress; SR[0] valid. 1 = Device is ready; SR[6:1] are valid. 0 = Erase suspend not in effect. 1 = Erase suspend in effect. 0 = Erase successful. 1 = Erase fail or program sequence error when set with SR[4,7]. 0 = Program successful. 1 = Program fail or program sequence error when set with SR[5,7]. 0 = VPP within acceptable limits during program or erase operation. 1 = VPP < VPPLK during program or erase operation. Default Value = 0x80 Block-Locked Status BLS 1 Partition Status PWS 0 Datasheet 66 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 26: Status Register Description (Sheet 2 of 2) Status Register (SR) 2 1 Program Suspend Status (PSS) Block-Locked Status (BLS) Default Value = 0x80 0 = Program suspend not in effect. 1 = Program suspend in effect. 0 = Block not locked during program or erase. 1 = Block locked during program or erase; operation aborted. DWS PWS 0 0 = Program or erase operation in addressed partition. 0 1 = Program or erase operation in other partition. 1 0 = No active program or erase operations. 1 1 = Reserved. (Non-buffered EFP operation. For Buffered EFP operation, see Section 0 Partition Write Status (PWS) 11.3, “Buffered Enhanced Factory Programming” on page 51). Always clear the Status Register prior to resuming erase operations. Avoid Status Register ambiguity when issuing commands during Erase Suspend. If a command sequence error occurs during an erase-suspend state, the Status Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the Status Register because it contains the previous error status. 15.1.1 Clear Status Register The Clear Status Register command clears the status register, leaving all partition read states unchanged. It functions independent of VPP. The Write State Machine (WSM) sets and clears SR[7,6,2,0], but it sets bits SR[5:3,1] without clearing them. The Status Register should be cleared before starting a command sequence to avoid any ambiguity. A device reset also clears the Status Register. 15.2 Read Device Identifier The Read Device Identifier command instructs the addressed partition to output manufacturer code, device identifier code, block-lock status, protection register data, or configuration register data when that partition’s addresses are read (see Section 9.2, “Device Commands” on page 37 for details on issuing the Read Device Identifier command). Table 27, “Device Identifier Information” on page 67 and Table 28, “Device ID codes” on page 68 show the address offsets and data values for this device. Issuing a Read Device Identifier command to a partition that is programming or erasing places that partition in the Read Identifier state while the partition continues to program or erase in the background. Table 27: Device Identifier Information (Sheet 1 of 2) Item Manufacturer Code Device ID Code Block Lock Configuration: • Block Is Unlocked • Block Is Locked • Block Is not Locked-Down • Block Is Locked-Down Configuration Register PBA + 0x05 BBA + 0x02 Address(1,2) PBA + 0x00 PBA + 0x01 Data 0089h ID (see Table 28) Lock Bit: AD0 = 0b0 AD0 = 0b1 AD1 = 0b0 AD1 = 0b1 Configuration Register Data November 2007 Order Number: 313295-04 Datasheet 67 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 27: Device Identifier Information (Sheet 2 of 2) Item Lock Register 0 64-bit Factory-Programmed Protection Register 64-bit User-Programmable Protection Register Lock Register 1 128-bit User-Programmable Protection Registers Notes: 1. PBA = Partition Base Address. 2. BBA = Block Base Address. Address(1,2) PBA + 0x80 PBA + 0x81–0x84 PBA + 0x85–0x88 PBA + 0x89 PBA + 0x8A–0x109 Data Protection Register Lock Bits Factory Protection Register Data User Protection Register Data Protection Register Lock Bits User Protection Register Data Table 28: Device ID codes Device Identifier Codes ID Code Type Device Density –T (Top Parameter) 8808 8809 880A –B (Bottom Parameter) 8834 8835 8836 64 Mbit Device Code 128 Mbit 256 Mbit 15.3 CFI Query The CFI Query command instructs the device to output Common Flash Interface (CFI) data when partition addresses are read. See Section 9.2, “Device Commands” on page 37 for details on issuing the CFI Query command. Appendix B, “Common Flash Interface (CFI)” on page 83 shows CFI information and address offsets within the CFI database. Issuing the CFI Query command to a partition that is programming or erasing places that partition’s outputs in the CFI Query state, while the partition continues to program or erase in the background. The CFI Query command is subject to read restrictions dependent on parameter partition availability, as described in Table 25. Datasheet 68 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Appendix A Write State Machine Figure 25 through Figure 30 show the command state transitions (Next State Table) based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read Array, Read Device ID, CFI Query or Read Status Register) until a new command changes it. The next WSM state does not depend on the partition’s output state. Figure 25: Write State Machine—Next State Table (Sheet 1 of 6) Command Input to Chip and resulting Chip Next State Current Chip (7) State Read Array ( 2) W ord Program (3,4) Buffered Program (BP) Erase Setup (3,4) Buffered Enhanced Factory Pgm Setup (3, 4) BE Confirm, P/E Resume, ULB, Confirm (D0H) ( 8) BP / Prg / Erase Suspend Read Status Clear Status Register ( 5) Read ID/Query Lock, Unlock, Lock-down, CR setup (4) (FFH) Ready Ready (10H/40H) Program Setup (E8H) BP Setup (20H) Erase Setup (80H) BEFP Setup (B0H) (70H) Ready (50H) (90H, 98H) (60H) Lock/CR Setup Lock/CR Setup Setup Busy Setup Word Program Busy Ready (Lock Error) Ready (Unlock Block) OTP Busy Word Program Busy Ready (Lock Error) OTP Program Busy Word Program Busy BP Load 1 BP Load 2 Word Program Suspend Word Program Busy Suspend Setup BP Load 1 Word Program Suspend Word Program Suspend BP Load 2 BP BP Confirm BP Busy BP Suspend Setup Busy Erase Suspend Erase Suspend Word Program Setup in Erase Suspend Ready (Error) BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 BP Busy Ready (Error) BP Busy BP Suspend Ready (Error) Erase Busy BP Setup in Erase Suspend BP Busy Erase Busy BP Suspend BP Busy BP Suspend Ready (Error) Erase Suspend Erase Busy Lock/CR Setup in Erase Suspend Erase Suspend Erase Busy Erase Suspend November 2007 Order Number: 313295-04 Datasheet 69 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 26: Write State Machine—Next State Table (Sheet 2 of 6) Command Input to Chip and resulting Chip Next State Current Chip (7) State Read Array (2) W ord Program (3,4) Buffered Program (BP) Buffered Erase Enhanced (3,4) Factory Pgm Setup Setup (3, 4) (20H) (80H) BE Confirm, P/E Resume, ULB, Confirm (8) (D0H) (B0H) (70H) BP / Prg / Erase Suspend Read Status Clear Status Register (5) Read ID/Query Lock, Unlock, Lock-down, CR setup (4) (FFH) Setup (10H/40H) (E8H) (50H) (90H, 98H) (60H) Word Program Busy in Erase Suspend Word Program Suspend in Erase Suspend Word Program Busy in Erase Suspend BP Load 1 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 Word Program in Erase Suspend Busy Word Program Busy in Erase Suspend Word Program Busy in Erase Suspend Busy Suspend Word Program Suspend in Erase Suspend Word Program Suspend in Erase Suspend Setup BP Load 1 BP Load 2 BP in Erase Suspend BP Confirm Erase Suspend (Error) BP Busy in Erase Suspend BP Suspend in Erase Suspend BP Busy in Erase Suspend Erase Suspend (Unlock Block) BEFP Loading Data (X=32) Ready (Error in Erase Suspend) BP Busy BP Busy in Erase Suspend BP Busy in Erase Suspend BP Suspend BP Suspend in Erase Suspend BP Suspend in Erase Suspend Lock/CR Setup in Erase Suspend Erase Suspend (Lock Error) Erase Suspend (Lock Error [Botch]) Buffered Enhanced Factory Program Mode Setup Ready (Error) Ready (Error) BEFP Busy BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7) Datasheet 70 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 27: Write State Machine—Next State Table (Sheet 3 of 6) Command Input to Chip and resulting Chip Next State OTP Setup (4) Lock Block Confirm (8) Current Chip (7) State Lock-Down Block Confirm (8) Write RCR Confirm (8) Block Address (?WA0) 9 Illegal Cmds or BEFP Data (1) WSM Operation Completes (C0H) (01H) (2FH) (03H) Ready (XXXXH) (all other codes) Ready OTP Setup Ready (Lock Error) Ready (Lock Block) Ready (Lock Down Blk) Lock/CR Setup Setup Busy Setup Word Program Busy Ready (Set CR) OTP Busy Ready (Lock Error) N/A OTP Ready N/A Ready Word Program Busy Word Program Busy Suspend Setup BP Load 1 BP Load 2 Word Program Suspend BP Load 1 Ready (BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; ELSE BP Load 2 Ready (Error) N/A BP Load 2 BP BP Confirm BP Busy BP Suspend Setup Busy Erase Suspend BP Confirm if Data load into Program Buffer is complete; ELSE BP load 2 Ready Ready (Error) Ready (Error) (Proceed if unlocked or lock error) BP Busy BP Suspend Ready N/A Ready (Error) Erase Busy Ready Erase Suspend N/A November 2007 Order Number: 313295-04 Datasheet 71 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 28: Write State Machine—Next State Table (Sheet 4 of 6) Command Input to Chip and resulting Chip Next State Current Chip State (7) OTP Setup (4) Lock Block Confirm (8) Lock-Down Block Confirm (8) Write RCR Confirm (8) Block Address (?WA0) 9 Illegal Cmds or BEFP Data (1) WSM Operation Completes (C0H) (01H) (2FH) (03H) (XXXXH) (all other codes) Setup Word Program Busy in Erase Suspend NA Word Program in Erase Suspend Busy Word Program Busy in Erase Suspend Busy Erase Suspend Suspend Word Program Suspend in Erase Suspend N/A Setup BP Load 1 BP Load 2 BP Load 1 Ready (BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 Ready (Error) BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 Ready N/A BP in Erase Suspend BP Confirm Ready (Error in Erase Suspend) Ready (Error) (Proceed if unlocked or lock error) BP Busy BP Busy in Erase Suspend Erase Suspend BP Suspend Erase Suspend (Lock Error) Erase Suspend (Lock Block) BP Suspend in Erase Suspend Erase Suspend (Lock Down Block) Lock/CR Setup in Erase Suspend Erase Suspend (Set CR) Erase Suspend (Lock Error) N/A Buffered Enhanced Factory Program Mode Setup Ready (Error) Ready (BEFP Loading Data) Ready (Error) BEFP Busy BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7) Ready BEFP Busy Ready Datasheet 72 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 29: Write State Machine—Next State Table (Sheet 5 of 6) Output Next State Table Command Input to Chip and resulting Output Mux Next State W ord Program Setup (3,4) BE Confirm, Buffered P/E Enhanced Erase Resume, Setup (3,4) Factory Pgm ULB Confirm Setup (3, 4) ( 8) (20H) (30H) (D0H) Program/ Erase Suspend Clear Status Register ( 5) Current chip state Read Array (2) BP Setup Read Status Read ID/Query Lock, Unlock, Lock-down, CR setup (4) (FFH) (10H/40H) (E8H) (B0H) (70H) (50H) (90H, 98H) (60H) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Lock/CR Setup, Lock/CR Setup in Erase Susp OTP Busy Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Erase Busy, BP Busy BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend Status Read Status Read Status Read Read Array Status Read Output does not change. Status Read Output mux does not change. Status Read ID Read November 2007 Order Number: 313295-04 Datasheet 73 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 30: Write State Machine—Next State Table (Sheet 6 of 6) Output Next State Table Command Input to Chip and resulting Output Mux Next State Lock Block Confirm (8) OTP Current chip state Setup (4) Lock-Down Block Confirm (8) Write CR Confirm (8) Block Address (?WA0) Illegal Cmds or BEFP Data (1) WSM Operation Completes (C0H) (01H) (2FH) (03H) (FFFFH) (all other codes) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Lock/CR Setup, Lock/CR Setup in Erase Susp OTP Busy Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Erase Busy, BP Busy BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend Status Read Status Read Array Read Status Read Output does not change. Status Read Output does not change. Array Read Output does not change. Notes: 1. "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase], etc.) 2. If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query data are located at different locations in the address map. 3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will occur. 4. To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle command sequence in which the second cycle will be ignored. For example, when the device is program suspended and an erase setup command (0x20) is given followed by a confirm/resume command (0xD0), the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation. 5. The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes). Datasheet 74 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) 6. 7. 8. 9. BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output mux is presently pointing to. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then move to the Ready State. WA0 refers to the block address latched during the first write cycle of the current operation. November 2007 Order Number: 313295-04 Datasheet 75 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Appendix B Flowcharts Figure 31: Word Program Flowchart WORD PROGRAM PROCEDURE Start Bus Operation Command Write (Setup) Comments Write 0x40, Word Address Write Data, Word Address Read Status Register Program Data = 0x40 Setup Addr = Location to program Data Data = Data to program Addr = Location to program Status register data Check SR[7] 1 = WSM Ready 0 = WSM Busy Write (Confirm) Read Program Suspend Loop No 0 Yes None Idle None SR[7] = 1 Suspend? Repeat for subsequent Word Program operations. Full Status Register check can be done after each program, or after a sequence of program operations. Write 0xFF after the last operation to set to the Read Array state. Full Status Check (if desired) Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Bus Command Operation Idle SR[3] = 0 1 1 Comments Check SR[3]: 1 = VPP Error Check SR[4]: 1 = Data Program Error Check SR[1]: 1 = Block locked; operation aborted None VPP Range Error Idle Program Error None SR[4] = 0 Idle None SR[1] = 0 1 Device Protect Error If an error is detected, clear the Status Register before continuing operations - only the Clear Staus Register command clears the Status Register error bits. Program Successful Datasheet 76 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 32: Program Suspend/Resume Flowchart PROGRAM SUSPEND / RESUME PROCEDURE Start Program Suspend Write B0h Any Address Read Status Bus Operation Command Write Comments Program Data = B0h Suspend Addr = Block to suspend (BA) Read Status Data = 70h Addr = Same partition Status register data Addr = Suspended block (BA) Check SR.7 1 = WSM ready 0 = WSM busy Check SR.2 1 = Program suspended 0 = Program completed Read Array Data = FFh Addr = Any address within the suspended partition Read array data from block other than the one being programmed Program Data = D0h Resume Addr = Suspended block (BA) Write 70h Same Partition Read Status Register Write Read SR.7 = 1 0 Standby SR.2 = Read 1 Array 0 Program Completed Standby Write Write FFh Susp Partition Read Read Array Data Write No Done Reading Yes Program Resume If the suspended partition was placed in Read Array mode: Write Read Array Read Status Return partition to Status mode: Data = 70h Addr = Same partition Write D0h Any Address Program Resumed Read Status Write FFh Pgm'd Partition Read Array Data Write 70h Same Partition PGM_SUS.WMF November 2007 Order Number: 313295-04 Datasheet 77 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 33: Buffer Program Flowchart Buffer Programming Procedure Start Bus Operation Device Supports Buffer Writes? Yes Set Timeout or Loop Counter Get Next Target Address Issue Buffer Prog. Cmd. 0xE8, Word Address No Use Single Word Programming Write Read Command Buffer Prog. Setup None Comments Data = 0xE8 Addr = Word Address SR[7] = Valid Addr = Word Address Check SR[7]: 1 = Write Buffer available 0 = No Write Buffer available Data = N-1 = Word Count N = 0 corresponds to count = 1 Addr = Word Address Data = Write Buffer Data Addr = Start Word Address Data = Write Buffer Data Addr = Word Address Data = 0xD0 Addr = Original Word Address Status register Data Addr = Note 7 Check SR[7]: 1 = WSM Ready 0 = WSM Busy Idle None Write (Notes 1, 2) Write (Notes 3, 4) Write (Note 3) Write (Notes 5, 6) Read Yes Idle None None None Buffer Prog. Conf. None Other partitions of the device can be read by addressing those partitions and driving OE# low. (Any write commands are not allowed during this period.) Read Status Register at Word Address No Write Buffer Available? SR[7] = 1 = Yes Write Word Count, Word Address Buffer Program Data, Start Word Address 0 = No Timeout or Count Expired? None X=X+1 X= 0 Write Buffer Data, Word Address No X = N? No Abort Buffer Program? Yes Yes Write Confirm 0xD0 and Word Address (Note 5) Write to another Block Address Issue Read Status Register Command 1. Word count value on D[7:0] is loaded into the word count register. Count ranges for this device are N = 0x00 to 0x1F. 2. The device outputs the Status Register when read. 3. Write Buffer contents will be programmed at the issued word address. 4. Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A[4:0] of the Start Word Address = 0x00). 5. The Buffered Programming Confirm command must be issued to an address in the same block, for example, the original Start Word Address, or the last address used during the loop that loaded the buffer data. 6. The Status Register indicates an improper command sequence if the Buffer Program command is aborted; use the Clear Status Register command to clear error bits. 7. The Status Register can be read from any addresses within the programming partition. Full status check can be done after all erase and write sequences complete. Write 0xFF after the last operation to place the partition in the Read Array state. 0xFF commands can be issued to read from any blocks in other partitions Buffer Program Aborted Read Status Register (Note 7) No 0=No Suspend Program? Yes Suspend Program Loop Is BP finished? SR[7] = 1=Yes Full Status Check if Desired Program Complete Datasheet 78 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 34: Buffered EFP Flowchart BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE Setup Phase Start Program & Verify Phase Read Status Reg. Exit Phase Read Status Reg. VPP applied, Block unlocked No (SR[0]=1) Data Stream Ready? Yes (SR[0]=0) Initialize Count: X=0 No (SR[7]=0) BEFP Exited? Yes (SR[7]=1) Full Status Check Procedure Write 0x80 @ 1ST Word Address Write 0xD0 @ 1ST Word Address Write Data @ 1ST Word Address Program Complete BEFP setup delay Increment Count: X = X+1 Read Status Reg. N Yes (SR[7]=0) X = 32? Y Read Status Reg. No (SR[0]=1) Program Done? Yes (SR[0]=0) N Last Data? Y Write 0xFFFF, Address Not within Current Block BEFP Setup Bus State Write Write (Note 1) Write Read Standby Operation Unlock Block BEFP Setup BEFP Confirm Status Register BEFP Setup Done? Comments V PPH applied to VPP ST Data = 0x80 @ 1 Word Address BEFP Setup Done? No (SR[7]=1) Check VPP, Lock Errors (SR[3,1]) Exit BEFP Program & Verify Bus State Operation Read Standby Status Register Comments Data = Status Register Data ST Address = 1 Word Addr. Bus State Read Standby BEFP Exit Operation Status Register Comments Data = Status Reg. Data Address = 1ST Word Addr Data = 0xD0 @ ST Word Address1 Data = Status Reg. Data Address = 1ST Word Addr Check SR[7]: 0 = BEFP Ready 1 = BEFP Not Ready Check SR[0]: Data Stream 0 = Ready for Data Ready? 1 = Not Ready for Data Initialize Count Load Buffer Increment Count Buffer Full? Status Register Program Done? Last Data? X=0 Data = Data to Program ST Address = 1 Word Addr. X = X+1 X = 32? Yes = Read SR[0] No = Load Next Data Word Data = Status Reg. data ST Address = 1 Word Addr. Check SR[0]: 0 = Program Done 1 = Program in Progress No = Fill buffer again Yes = Exit Check SR[7]: Check Exit 0 = Exit Not Completed Status 1 = Exit Completed Standby Write (Note 2) Standby Repeat for subsequent blocks; After BEFP exit, a full Status Register check can determine if any program error occurred; See full Status Register check procedure in the Word Program flowchart. Write 0xFF to enter Read Array state. Error If SR[7] is set, check: Standby Condition SR[3] set = VPP Error SR[1] set = Locked Block Check Standby Read Standby Standby Write Exit Prog & Data = 0xFFFF @ address not in Verify Phase current block NOTES: 1. First-word address to be programmed within the target block must be aligned on a write-buffer boundary. 2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address; WSM internally increments addressing. November 2007 Order Number: 313295-04 Datasheet 79 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 35: Block Erase Flowchart BLOCK ERASE PROCEDURE Start Bus Comments Operation Command Block Data = 0x20 Write Erase Addr = Block to be erased (BA) Setup Write Write 0xD0, (Erase Confirm) Block Address Read Read Status Register No Write 0x20, (Block Erase) Block Address Erase Data = 0xD0 Confirm Addr = Block to be erased (BA) None Status Register data. Check SR[7]: 1 = WSM ready 0 = WSM busy Suspend Erase Loop 0 Idle None SR[7] = 1 Suspend Erase Yes Repeat for subsequent block erasures. Full Status register check can be done after each block erase or after a sequence of block erasures. Write 0xFF after the last operation to enter read array mode. Full Erase Status Check (if desired) Block Erase Complete FULL ERASE STATUS CHECK PROCEDURE Read Status Register 1 Bus Command Operation VPP Range Error Command Sequence Error Block Erase Error Block Locked Error Idle Idle Idle Idle None None None None Comments Check SR[3]: 1 = VPP Range Error Check SR[4,5]: Both 1 = Command Sequence Error Check SR[5]: 1 = Block Erase Error Check SR[1]: 1 = Attempted erase of locked block; erase aborted. SR[3] = 0 SR[4,5] = 0 1,1 SR[5] = 0 1 Only the Clear Status Register command clears SR[1, 3, 4, 5]. 1 SR[1] = 0 If an error is detected, clear the Status register before attempting an erase retry or other error recovery. Block Erase Successful Datasheet 80 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 36: Erase Suspend/Resume Flowchart ERASE SUSPEND / RESUME PROCEDURE Start Bus Command Operation (Read Status) Comments Data = 0x70 Addr = Any partition address Data = 0xB0 Addr = Same partition address as above Status Register data. Addr = Same partition Check SR[7]: 1 = WSM ready 0 = WSM busy Check SR[6]: 1 = Erase suspended 0 = Erase completed Write 0x70, Same Partition Write 0xB0, Any Address Read Status Register Write Read Status Erase Suspend None (Erase Suspend) Write Read Idle SR[7] = 1 0 0 None Idle Erase Completed Write Read or Write Write None SR[6] = 1 Read Array Data = 0xFF or 0x40 Addr = Any address within the or Program suspended partition None Read array or program data from/to block other than the one being erased Read Read or Program? No Program Read Array Data Program Loop Program Data = 0xD0 Resume Addr = Any address If the suspended partition was placed in Read Array mode or a Program Loop: Read Status Register Return partition to Status mode: Data = 0x70 Addr = Same partition Done (Erase Resume) Write 0xD0, Any Address Erase Resumed Write 0x70, Same Partition Write Write 0xFF, (Read Array) Erased Partition Read Array Data (Read Status) November 2007 Order Number: 313295-04 Datasheet 81 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 37: Block Lock Operations Flowchart LOCKING OPERATIONS PROCEDURE Start Bus Command Operation (Lock Setup) Comments Data = 0x60 Addr = Block to lock/unlock/lock-down Write 0x60, Block Address Write Lock Setup Write either 0x01/0xD0/0x2F, (Lock Confirm) Block Address Write Lock, Data = 0x01 (Block Lock) Unlock, or 0xD0 (Block Unlock) Lock-Down 0x2F (Lock-Down Block) Confirm Addr = Block to lock/unlock/lock-down Write 0x90 (Read Device ID) Write Read Data = 0x90 (Optional) Device ID Addr = Block address + offset 2 Read Block Lock Block Lock status data (Optional) Status Addr = Block address + offset 2 Optional Read Block Lock Status Locking Change? Yes No Idle None Confirm locking change on D[1,0]. Write Read Array Data = 0xFF Addr = Block address Write 0xFF (Read Array) Partition Address Lock Change Complete Datasheet 82 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Figure 38: Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Start Bus Command Operation Write (Program Setup) Comments Write 0xC0, PR Address Program Data = 0xC0 PR Setup Addr = First Location to Program Protection Data = Data to Program Program Addr = Location to Program None Status Register Data. Check SR[7]: 1 = WSM Ready 0 = WSM Busy Write Write PR Address & Data (Confirm Data) Read Read Status Register Idle None SR[7] = 1 0 Program Protection Register operation addresses must be within the Protection Register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. Full Status Register check can be done after each program, or after a sequence of program operations. Write 0xFF after the last operation to set Read Array state. Full Status Check (if desired) Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data Bus Command Operation Idle SR[3] = 0 1 Comments Check SR[3]: 1 =VPP Range Error Check SR[4]: 1 =Programming Error Check SR[1]: 1 =Block locked; operation aborted None VPP Range Error Idle None SR[4] = 0 1 Program Error Idle None Only the Clear Staus Register command clears SR[1, 3, 4]. 1 SR[1] = 0 Register Locked; Program Aborted If an error is detected, clear the Status register before attempting a program retry or other error recovery. Program Successful B.1 Common Flash Interface (CFI) Common Flash Interface (CFI) is part of an overall specification for multiple commandset and control-interface descriptions. This appendix describes the database structure containing the data returned by a read operation after issuing the CFI Query command (see Section 9.2, “Device Commands” on page 37). System software can parse this November 2007 Order Number: 313295-04 Datasheet 83 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. B.2 Query Structure Output The Query database allows system software to obtain information for controlling the flash device. This section describes the device’s CFI-compliant interface that allows access to Query data. Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ7-0) and 00h in the high byte (DQ15-8). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. Table 29: Summary of Query Structure Output as a Function of Device and Mode Device Hex Offset 00010 Device Addresses 00011 00012 51 52 59 Hex Code “Q” “R” “Y” ASCII Value Table 30: Example of Query Structure Output of x16- Devices Word Addressing: Hex Code D15–D0 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Byte Addressing: Hex Code D7–D0 51 52 59 P_IDLO P_IDLO P_IDHI ... Offset AX–A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ... Value "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... Offset AX–A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ... Value "Q" "R" "Y" PrVendor ID # ID # ... B.3 Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized below. Datasheet 84 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 31: Query Structure Offset 00001-Fh 00010h 0001Bh 00027h P(3) Description Reserved Reserved for vendor-specific information CFI query identification string Command set ID and vendor data offset System interface information Device timing & voltage information Device geometry definition Flash device layout Primary Intel-specific Extended Query Table Vendor-defined additional information specific Sub-Section Name (1) Notes: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 16K-word). 3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table. B.4 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table 32: CFI Identification Offset 10h Length 3 Description Query-unique ASCII string “QRY“ Hex Add. Code 10: --51 11: --52 12: --59 13: --01 14: --00 15: --0A 16: --01 17: --00 18: --00 19: --00 1A: --00 Value "Q" "R" "Y" 13h 15h 17h 19h 2 2 2 2 Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists November 2007 Order Number: 313295-04 Datasheet 85 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 33: System Interface Information Hex Add. Code 1B: --17 Offset 1Bh Length 1 Description VCC logic supply minimum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 BCD volts VCC logic supply maximum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 HEX volts “n” such that typical single word program time-out = 2n μ-sec “n” such that typical max. buffer write time-out = 2n μ-sec “n” such that typical block erase time-out = 2n m-sec “n” such that typical full chip erase time-out = 2n m-sec “n” such that maximum word program time-out = 2n times typical “n” such that maximum buffer write time-out = 2n times typical “n” such that maximum block erase time-out = 2n times typical “n” such that maximum chip erase time-out = 2n times typical Value 1.7V 1Ch 1 1C: --20 2.0V 1Dh 1 1D: --85 8.5V 1Eh 1 1E: --95 9.5V 1Fh 20h 21h 22h 23h 24h 25h 26h 1 1 1 1 1 1 1 1 1F: 20: 21: 22: 23: 24: 25: 26: --08 --09 --0A --00 --01 --01 --02 --00 256μs 512μs 1s NA 512μs 1024μs 4s NA Datasheet 86 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) B.5 Device Geometry Definition Table 34: Device Geometry Definition Offset 27h Length Description “n” such that device size = 2n in number of bytes 1 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: 7 6 5 4 3 2 1 0 Code 27: See table below 28h 2 — 15 — 14 — 13 — 12 x64 11 x32 10 x16 9 x8 8 28: 29: 2A: 2B: 2C: --01 --00 --06 --00 x16 2Ah 2Ch 2 1 — — — — — — — — “n” such that maximum number of bytes in write buffer = 2n Number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region Erase Block Region 1 Information bits 0–15 = y, y+1 = number of identical-size erase blocks bits 16–31 = z, region erase block(s) size are z x 256 bytes Erase Block Region 2 Information bits 0–15 = y, y+1 = number of identical-size erase blocks bits 16–31 = z, region erase block(s) size are z x 256 bytes Reserved for future erase block region information 64 See table below 2Dh 4 31h 4 35h 4 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38: See table below See table below See table below Address 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38: 64 Mbit –B –T --17 --17 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --3E --00 --00 --80 --00 --00 --02 --03 --3E --00 --00 --80 --00 --00 --02 --00 --00 --00 --00 --00 --00 --00 --00 128 Mbit –B –T --18 --18 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --7E --00 --00 --80 --00 --00 --02 --7E --03 --00 --00 --00 --80 --02 --00 --00 --00 --00 --00 --00 --00 --00 --00 256 Mbit –B –T --19 --19 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --FE --00 --00 --80 --00 --00 --02 --FE --03 --00 --00 --00 --80 --02 --00 --00 --00 --00 --00 --00 --00 --00 --00 November 2007 Order Number: 313295-04 Datasheet 87 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) B.6 Intel-Specific Extended Query Table Table 35: Primary Vendor-Specific Extended Query Offset P= 10Ah (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h (1) Length 3 Description (Optional flash features and commands) Primary extended query table Unique ASCII string “PRI“ Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 10–31 are reserved; undefined bits are “0.” If bit 31 is “1” then another 31 bit field of Optional features follows at the end of the bit–30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode read supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported bit 10 Reserved bit 30 CFI Link(s) to follow bit 31 Another "Optional Features" field to follow Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1–7 reserved; undefined bits are “0” bit 0 Program supported after erase suspend Block status register mask bits 2–15 are Reserved; undefined bits are “0” bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0–3 BCD value in 100 mV bits 4–7 BCD value in volts VPP optimum program/erase supply voltage bits 0–3 BCD value in 100 mV bits 4–7 HEX value in volts 1 1 4 (P+9)h 1 Hex Add. Code 10A --50 10B: --52 10C: --49 10D: --31 10E: --33 10F: --E6 110: --03 111: --00 112: --00 bit 0 = 0 bit 1 = 1 bit 2 = 1 bit 3 = 0 bit 4 = 0 bit 5 = 1 bit 6 = 1 bit 7 = 1 bit 8 = 1 bit 9 = 1 bit 10 = 0 bit 30 = 0 bit 31 = 0 113: --01 Value "P" "R" "I" "1" "3" No Yes Yes No No Yes Yes Yes Yes Yes No No No (P+A)h (P+B)h 2 (P+C)h 1 bit 0 114: 115: bit 0 bit 1 116: =1 --03 --00 =1 =1 --18 Yes Yes Yes 1.8V (P+D)h 1 117: --90 9.0V Datasheet 88 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 36: Protection Register Information Offset P= 10Ah (P+E)h (P+F)h (P+10)h (P+11)h (P+12)h (1) Length 1 4 Description (Optional flash features and commands) Number of Protection register fields in JEDEC ID space. “00h,” indicates that 256 protection fields are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with device-unique serial numbers. Others are user programmable. Bits 0–15 point to the Protection register Lock byte, the section’s first byte. The following bytes are factory pre-programmed and user-programmable. bits bits bits bits 0–7 = Lock/bytes Jedec-plane physical low address 8–15 = Lock/bytes Jedec-plane physical high address 16–23 = “n” such that 2n = factory pre-programmed bytes 24–31 = “n” such that 2n = user programmable bytes Hex Add. Code 118: --02 119: 11A: 11B: 11C: --80 --00 --03 --03 Value 2 80h 00h 8 byte 8 byte (P+13)h (P+14)h (P+15)h (P+16)h (P+17)h (P+18)h (P+19)h (P+1A)h (P+1B)h (P+1C)h 10 Protection Field 2: Protection Description Bits 0–31 point to the Protection register physical Lock-word address in the Jedec-plane. Following bytes are factory or user-programmable. bits 32–39 = “n” ∴ n = factory pgm'd groups (low byte) bits 40–47 = “n” ∴ n = factory pgm'd groups (high byte) bits 48–55 = “n” \ 2n = user programmable bytes/group bits 56–63 = “n” ∴ n = user pgm'd groups (low byte) bits 64–71 = “n” ∴ n = user pgm'd groups (high byte) bits 72–79 = “n” ∴ 2n = user programmable bytes/group 11D: 11E: 11F: 120: 121: 122: 123: 124: 125: 126: --89 --00 --00 --00 --00 --00 --00 --10 --00 --04 89h 00h 00h 00h 0 0 0 16 0 16 November 2007 Order Number: 313295-04 Datasheet 89 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 37: Burst Read Information Offset P= 10Ah (P+1D)h (1) Length 1 (P+1E)h (P+1F)h 1 1 (P+20)h (P+21)h (P+22)h 1 1 1 Description (Optional flash features and commands) Page Mode Read capability bits 0–7 = “n” such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Synchronous mode read capability configuration 1 Bits 3–7 = Reserved bits 0–2 “n” such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device’s burstable address space. This field’s 3-bit value can be written directly to the Read Configuration Register bits 0–2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4 Hex Add. Code Value 127: --00 0 byte 128: 129: --04 --01 4 4 12A: 12B: 12C: --02 --03 --07 8 16 Cont Table 38: Partition and Erase-block Region Information Offset P= 10Ah Description Bottom Top (Optional flash features and commands) (P+23)h (P+23)h Number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions. (1) See table below Address Bot Top Len 1 12D: 12D: Datasheet 90 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 39: Partition Region 1 Information Offset P= 10Ah Description Bottom (Optional flash features and commands) Top (P+24)h (P+24)h Number of identical partitions within the partition region (P+25)h (P+25)h (P+26)h (P+26)h Number of program or erase operations allowed in a partition bits 0–3 = number of simultaneous Program operations bits 4–7 = number of simultaneous Erase operations (P+27)h (P+27)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Program mode bits 0–3 = number of simultaneous Program operations bits 4–7 = number of simultaneous Erase operations (P+28)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0–3 = number of simultaneous Program operations bits 4–7 = number of simultaneous Erase operations (P+29)h Types of erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+ (Type n blocks)x(Type n block sizes) (P+2A)h Partition Region 1 Erase Block Type 1 Information (P+2B)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition (P+2C)h bits 16–31 = z, region erase block(s) size are z x 256 bytes (P+2D)h (P+2E)h Partition 1 (Erase Block Type 1) Minimum block erase cycles x 1000 (P+2F)h (P+30)h Partition 1 (erase block Type 1) bits per cell; internal ECC bits 0–3 = bits per cell in erase region bit 4 = reserved for “internal ECC used” (1=yes, 0=no) bits 5–7 = reserve for future use (P+31)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3–7 = reserved for future use Partition Region 1 Erase Block Type 2 Information bits 0–15 = y, y+1 = # identical-size erase blks in a partition bits 16–31 = z, region erase block(s) size are z x 256 bytes (bottom parameter device only) Partition 1 (Erase block Type 2) Minimum block erase cycles x 1000 Partition 1 (Erase block Type 2) bits per cell bits 0–3 = bits per cell in erase region bit 4 = reserved for “internal ECC used” (1=yes, 0=no) bits 5–7 = reserve for future use Partition 1 (Erase block Type 2) pagemode and synchronous mode capabilities defined in Table 10 bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3–7 = reserved for future use (1) See table below Address Bot Top Len 2 12E: 12E: 12F: 12F: 1 130: 130: 1 131: 131: (P+28)h 1 132: 132: (P+29)h 1 133: 133: (P+2A)h (P+2B)h (P+2C)h (P+2D)h (P+2E)h (P+2F)h (P+30)h 4 2 1 134: 135: 136: 137: 138: 139: 13A: 134: 135: 136: 137: 138: 139: 13A: (P+31)h 1 13B: 13B: (P+32)h (P+33)h (P+34)h (P+35)h (P+36)h (P+37)h (P+38)h 4 2 1 13C: 13D: 13E: 13F: 140: 141: 142: (P+39)h 1 143: November 2007 Order Number: 313295-04 Datasheet 91 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 40: Partition Region 2 Information Offset(1) P= 10Ah Description Bottom Top (Optional flash features and commands) (P+3A)h (P+32)h Number of identical partitions within the partition region (P+3B)h (P+33)h (P+3C)h (P+34)h Number of program or erase operations allowed in a partition bits 0–3 = number of simultaneous Program operations bits 4–7 = number of simultaneous Erase operations (P+3D)h (P+35)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Program mode bits 0–3 = number of simultaneous Program operations bits 4–7 = number of simultaneous Erase operations (P+3E)h (P+36)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0–3 = number of simultaneous Program operations bits 4–7 = number of simultaneous Erase operations (P+3F)h (P+37)h Types of erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+ (Type n blocks)x(Type n block sizes) (P+40)h (P+38)h Partition Region 2 Erase Block Type 1 Information (P+41)h (P+39)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition (P+42)h (P+3A)h bits 16–31 = z, region erase block(s) size are z x 256 bytes (P+43)h (P+3B)h (P+44)h (P+3C)h Partition 2 (Erase block Type 1) (P+45)h (P+3D)h Minimum block erase cycles x 1000 (P+46)h (P+3E)h Partition 2 (Erase block Type 1) bits per cell bits 0–3 = bits per cell in erase region bit 4 = reserved for “internal ECC used” (1=yes, 0=no) bits 5–7 = reserve for future use (P+47)h (P+3F)h Partition 2 (erase block Type 1) pagemode and synchronous mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3–7 = reserved for future use (P+40)h Partition Region 2 Erase Block Type 2 Information (P+41)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition (P+42)h bits 16–31 = z, region erase block(s) size are z x 256 bytes (P+43)h (P+44)h Partition 2 (Erase block Type 2) (P+45)h Minimum block erase cycles x 1000 (P+46)h Partition 2 (Erase block Type 2) bits per cell bits 0–3 = bits per cell in erase region bit 4 = reserved for “internal ECC used” (1=yes, 0=no) bits 5–7 = reserve for future use (P+47)h Partition 2 (erase block Type 2) pagemode and synchronous mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3–7 = reserved for future use See table below Address Bot Top Len 2 144: 13C: 145: 13D: 1 146: 13E: 1 147: 13F: 1 148: 140: 1 149: 141: 4 2 1 14A: 14B: 14C: 14D: 14E: 14F: 150: 142: 143: 144: 145: 146: 147: 148: 1 151: 149: 4 2 1 14A: 14B: 14C: 14D: 14E: 14F: 150: 1 151: Datasheet 92 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 41: Partition and Erase Block Information Address 12D : 12E: 12F: 130: 131: 132: 133: 134: 135: 136: 137: 138: 139: 13A: 13B: 13C : 13D : 13E: 13F: 140: 141: 142: 143: 144: 145: 146: 147: 148: 149: 14A: 14B: 14C : 14D : 14E: 14F: 150: 151: –B --02 --01 --00 --11 --00 --00 --02 --03 --00 --80 --00 --64 --00 --02 --02 --06 --00 --00 --02 --64 --00 --02 --02 --07 --00 --11 --00 --00 --01 --07 --00 --00 --02 --64 --00 --02 --02 64 M bit –T --02 --07 --00 --11 --00 --00 --01 --07 --00 --00 --02 --64 --00 --02 --02 --01 --00 --11 --00 --00 --02 --06 --00 --00 --02 --64 --00 --02 --02 --03 --00 --80 --00 --64 --00 --02 --02 128 M bit –B –T --02 --02 --01 --0F --00 --00 --11 --11 --00 --00 --00 --00 --02 --01 --03 --07 --00 --00 --80 --00 --00 --02 --64 --64 --00 --00 --02 --02 --02 --02 --06 --01 --00 --00 --00 --11 --02 --00 --64 --00 --00 --02 --02 --06 --02 --00 --0F --00 --00 --02 --11 --64 --00 --00 --00 --02 --01 --02 --07 --03 --00 --00 --00 --80 --02 --00 --64 --64 --00 --00 --02 --02 --02 --02 256 M bit –B –T --02 --02 --01 --0F --00 --00 --11 --11 --00 --00 --00 --00 --02 --01 --03 --0F --00 --00 --80 --00 --00 --02 --64 --64 --00 --00 --02 --02 --02 --02 --0E --01 --00 --00 --00 --11 --02 --00 --64 --00 --00 --02 --02 --0E --02 --00 --0F --00 --00 --02 --11 --64 --00 --00 --00 --02 --01 --02 --0F --03 --00 --00 --00 --80 --02 --00 --64 --64 --00 --00 --02 --02 --02 --02 November 2007 Order Number: 313295-04 Datasheet 93 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 42: Electrical Traceability 76h 76h 1 76h Bits 0 – 2: Stepping (See Table 3 and 4) Bit 3: Production Bit (See Table 3 and 4) Bits 4 – 7: Memory clock rate 0000 = 40MHz 0001 = 54MHz 0010 = 66MHz 1XXX = DDR Bits 8 – 9: Process Bit 10: Mass memory 0 = No 1 = Yes Bits 11 - 12: Ram Type 00 = No 01 = SRAM 10 = PSRAM 11 = DRAM Bits 13 – 15: RAM density 000 = no SRAM 001 = 4 Mb 010 = 8 Mb 011 = 16 Mb 100 = 32 Mb… Reserved for future use Resv'd 152: 76h (P+48)h (P+48)h 152: Table 43: Density CFI Revision History for Engineering Sample at Address 76h CFI Field Data xxxxh Revision Comments OMPU 64 Mbit - Bin 1 OMPU 64 Mbit - Bin 1 64 Mbit - Bin 1 64 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 2 128 Mbit - Bin 2 128 Mbit - Bin 2 128 Mbit - Bin 2 256 Mbit - Bin 1 256 Mbit - Bin 1 256 Mbit - Bin 2 256 Mbit - Bin 2 000 00 0 00 0001 1100 001Ch Revision 2 A2 Silicon (128Mb A2 Silicon) 000 00 0 00 0001 1011 000 00 0 00 0001 1110 000 00 0 00 0001 1101 000 00 0 00 0001 1110 000 00 0 00 0001 1101 000 00 0 00 0001 1100 000 00 0 00 0001 1011 000 00 0 00 0000 1110 000 00 0 00 0000 1101 000 00 0 00 0000 1100 000 00 0 00 0000 1011 000 00 0 00 0001 1110 000 00 0 00 0001 1101 000 00 0 00 0000 1110 000 00 0 00 0000 1101 001Bh 001Eh 001Dh 001Eh 001Dh 001Ch 001Bh 000Eh 000Dh 000Ch 000Bh 001Eh 001Dh 000Eh 000Dh Revision 3 Revision 0 Revision 1 Revision 0 Revision 1 Revision 2 Revision 3 Revision 0 Revision 1 Revision 2 Revision 3 Revision 0 Revision 1 Revision 0 Revision 1 A3 Silicon (128Mb A3 Silicon) A0 Silicon A1 Silicon A0 Silicon A1 Silicon A2 Silicon A3 Silicon A0 Silicon A1 Silicon A2 Silicon A3 Silicon A0 Silicon A1 Silicon A0 Silicon A1 Silicon Datasheet 94 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 44: CFI Revision History for Production Materials at Address 76h CFI Field Data 000 00 0 00 0001 0001 000 00 0 00 0001 0010 000 00 0 00 0001 0001 000 00 0 00 0001 0010 000 00 0 00 0001 0011 000 00 0 00 0001 0001 000 00 0 00 0001 0010 000 00 0 00 0001 0011 000 00 0 00 0000 0001 000 00 0 00 0000 0010 000 00 0 00 0000 0011 000 00 0 00 0001 0001 000 00 0 00 0001 0010 000 00 0 00 0001 0011 000 00 0 00 0000 0001 000 00 0 00 0000 0010 000 00 0 00 0000 0011 xxxxh 0011h 0012h 0011h 0012h 0013h 0011h 0012h 0013h 0001h 0002h 0003h 0011h 0012h 0013h 0001h 0002h 0003h Revision Revision 1 Revision 2 Revision 1 Revision 2 Revision 3 Revision 1 Revision 2 Revision 3 Revision 1 Revision 2 Revision 3 Revision 1 Revision 2 Revision 3 Revision 1 Revision 2 Revision 3 Comments Production Silicon (128Mb Prod Silicon Rev) Rev 2 If Errata Production Silicon Rev 2 If Errata Rev 3 If Errata Production Silicon Rev 2 If Errata Rev 3 If Errata Production Silicon Rev 2 If Errata Rev 3 If Errata Production Silicon Rev 2 If Errata Rev 3 If Errata Production Silicon Rev 2 If Errata Rev 3 If Errata Density OMPU 64 Mbit - Bin 1 OMPU 64 Mbit - Bin 1 64 Mbit - Bin 1 64 Mbit - Bin 1 64 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 2 128 Mbit - Bin 2 128 Mbit - Bin 2 256 Mbit - Bin 1 256 Mbit - Bin 1 256 Mbit - Bin 1 256 Mbit - Bin 2 256 Mbit - Bin 2 256 Mbit - Bin 2 November 2007 Order Number: 313295-04 Datasheet 95 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Appendix C Ordering Information To order samples, obtain datasheets or inquire about any stack combination, please contact your local Intel representative. Table 45: 38F Type Stacked Components PF Package Designator 38F Product Line Designator 5070 Product Die/ Density Configuration Char 1 = Flash die #1 Char 2 = Flash die #2 PF = SCSP, RoHS RD = SCSP, Leaded Stacked NOR Flash + RAM Char 3 = RAM die #1 Char 4 = RAM die #2 (See First character applies to Flash die #1 Second character applies to Flash die #2 (See M0 NOR Flash Product Family Y Voltage/NOR Flash CE# Configuration 0 Parameter / Mux Configuration B Ballout Identifier 0 Device Details V= 1.8 V Core and I/O; Separate Chip Enable per die (See 0= No parameter blocks; NonMux I/O interface (See B= x16D Ballout (See for details) Table 47, “38F / 48F Density Decoder” on page 97 details) Table 48, “NOR Flash Family Decoder” on page 97 for for details) Table 49, “Voltage / NOR Flash CE# Configurati on Decoder” on page 97 for details) Table 50, “Parameter / Mux Configurati on Decoder” on page 98 for details) Table 51 , “Ballout Decoder ” on page 98 0= Original released version of this product Table 46: 48F Type Stacked Components PC Package Designator PC = Easy BGA, RoHS RC = Easy BGA, Leaded JS = TSOP, RoHS TE = TSOP, Leaded PF = SCSP, RoHS RD = SCSP, Leaded Stacked NOR Flash only 48F Product Line Designator 4400 Product Die/ Density Configuration Char 1 = Flash die #1 Char 2 = Flash die #2 Char 3 = Flash die #3 Char 4 = Flash die #4 (See First character applies to Flash dies #1 and #2 Second character applies to Flash dies #3 and #4 (See Table 48, “NOR Flash Family Decoder” on page 97 for V= 1.8 V Core and 3 V I/O; Virtual Chip Enable (See B= Bottom parameter; Non-Mux I/O interface (See 0= Discrete Ballout (See P0 NOR Flash Product Family V Voltage/NOR Flash CE# Configuration B Parameter / Mux Configuration 0 Ballout Identifier 0 Device Details details) Table 47, “38F / 48F Density Decoder” on page 97 for details) for details) Table 49, “Voltage / NOR Flash CE# Configurati on Decoder” on page 97 for details) Table 50, “Parameter / Mux Configurati on Decoder” on page 98 Table 51 , “Ballout Decoder ” on page 98 0= Original released version of this product f or details) Datasheet 96 November 2007 Order Number: 313295-04 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 47: 38F / 48F Density Decoder Code 0 1 2 3 4 5 6 7 8 9 A B C D E F No Die 32-Mbit 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit 2-Gbit 4-Gbit 8-Gbit 16-Gbit 32-Gbit 64-Gbit 128-Gbit 256-Gbit 512-Gbit Flash Density No Die 4-Mbit 8-Mbit 16-Mbit 32-Mbit 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit 2-Gbit 4-Gbit 8-Gbit 16-Gbit 32-Gbit 64-Gbit RAM Density Table 48: NOR Flash Family Decoder Code C C3 J3v.D L18 / L30 M18 P30 / P33 W18 / W30 Family Marketing Name Intel Advanced+ Boot Block Flash Memory Intel Embedded Flash Memory Intel StrataFlash® Wireless Memory Intel StrataFlash® Cellular Memory Intel StrataFalsh® Embedded Memory Intel Wireless Flash Memory No Die J L M P W 0(zero) Table 49: Voltage / NOR Flash CE# Configuration Decoder (Sheet 1 of 2) Code Z I/O Voltage (Volt) 3.0 1.8 3.0 3.0 1.8 3.0 1.8 1.8 3.0 1.8 1.8 3.0 Core Voltage (Volt) CE# Configuration Seperate Chip Enable per die Seperate Chip Enable per die Seperate Chip Enable per die Virtual Chip Enable Virtual Chip Enable Virtual Chip Enable Y X V U T November 2007 Order Number: 313295-04 Datasheet 97 Numonyx™ StrataFlash® Wireless Memory (L18 AD-Mux) Table 49: Voltage / NOR Flash CE# Configuration Decoder (Sheet 2 of 2) Code R Q P I/O Voltage (Volt) 3.0 1.8 3.0 1.8 1.8 3.0 Core Voltage (Volt) Virtual Address Virtual Address Virtual Address CE# Configuration Table 50: Parameter / Mux Configuration Decoder Code, Mux Identification 0 = Non Mux 1 = AD Mux1 2= AAD Mux 3 =Full" AD Mux2 Number of Flash Die Bus Width Flash Die 1 Flash Die 2 Flash Die 3 Flash Die 4 Any NA Notation used for stacks that contain no parameter blocks 1 B = Non Mux C = AD Mux F = "Full" Ad Mux 2 3 4 2 4 1 T = Non Mux U = AD Mux W = "Full" Ad Mux 2 3 4 2 4 X32 X16 X32 X16 Bottom Bottom Bottom Bottom Bottom Bottom Top Top Top Top Top Top Top Bottom Top Bottom Bottom Bottom Top Bottom Top Top Top Bottom Top Bottom Top Bottom Top Top Bottom Bottom 1. Only Flash is Muxed and RAM is non-Muxed 2. Both Flash and RAM are AD-Muxed Table 51: Ballout Decoder Code 0 (Zero) B C Q U V W SDiscrete ballout (Easay BGA and TSOP) x16D ballout, 105 ball (x16 NOR + NAND + DRAM Share Bus) x16C ballout, 107 ball (x16 NOR + NAND + PSRAM Share Bus) QUAD/+ ballout, 88 ball (x16 NOR + PSRAM Share Bus) x32SH ballout, 106 ball (x32 NOR only Share Bus) x16SB ballout, 165 ball (x16 NOR / NAND + x16 DRAM Split Bus x48D ballout, 165 ball (x16/x32 NOR + NAND + DRAM Split Bus Ballout Definition Datasheet 98 November 2007 Order Number: 313295-04