M36L0R7060T1ZAQE

M36L0R7060T1 M36L0R7060B1 128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package Features ■ Multichip package – 1 die of 128 Mbit (8 Mb x16, Multiple Bank, Multilevel, Burst) Flash memory – 1 die of 64 Mbit (4 Mb x16) Pseudo SRAM Supply voltage – VDDF = VCCP = VDDQF = 1.7 to 1.95 V – VPPF = 9 V for fast program Electronic signature – Manufacturer Code: 20h – Top Device Code M36L0R7060T1: 88C4h – Bottom Device Code M36L0R7060B1: 88C5h Package – ECOPACK® FBGA ■ ■ TFBGA88 (ZAQ) 8 x 10 mm ■ ■ Security – 64 bit unique device number – 2112 bit user programmable OTP Cells Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency – WPF for Block Lock-Down – Absolute Write Protection with VPPF = VSS ■ Flash memory ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 54 MHz, 66 MHz – Random Access: 70 ns, 85 ns Synchronous Burst Read Suspend Programming time – 2.5 µs typical word program time using Buffer Enhanced Factory Program command Memory organization – Multiple Bank memory array: 8 Mbit banks – Parameter Blocks (top or bottom location) Common Flash Interface (CFI) 100 000 program/erase cycles per block Dual operations – program/erase in one Bank while read in others – No delay between read and write operations ■ ■ ■ ■ ■ PSRAM Access time: 70 ns Asynchronous Page Read – Page Size: 4, 8 or 16 words – Subsequent read within page: 20 ns Low power features – Automatic Temperature-compensated SelfRefresh (TCR) – Partial Array Self-Refresh (PASR) – Deep Power-Down (DPD) mode Synchronous Burst Read/Write ■ ■ ■ ■ ■ November 2007 Rev 2 1/22 www.numonyx.com 1 Contents M36L0R7060T1, M36L0R7060B1 Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 Address inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM Chip Enable input (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . 11 VDDF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VCCP supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VDDQF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VPPF Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 4 5 6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/22 M36L0R7060T1, M36L0R7060B1 Contents 7 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3/22 List of tables M36L0R7060T1, M36L0R7060B1 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4/22 M36L0R7060T1, M36L0R7060B1 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TFBGA88 8 × 10 mm, 8 × 10 ball array - 0.8 mm pitch, package outline . . . . . . . . . . . . . . 18 5/22 Description M36L0R7060T1, M36L0R7060B1 1 Description The M36L0R7060T1 and M36L0R7060B1 combine two memory devices in a multichip package: ● ● a 128-Mbit, Multiple Bank Flash memory, the M58LR128HT or M58LR128HB a 64-Mbit PseudoSRAM, the M69KB096AM The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58LR128HTB and M69KB096AM datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from your local Numonyx distributor. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 × 10 mm, 8 × 10 ball array, 0.8 mm pitch) package. The memory is supplied with all the bits erased (set to ‘1’). Figure 1. Logic diagram VDDQF VPPF VCCP 16 DQ0-DQ15 EF GF WF RPF WPF L K EP GP WP CRP UBP LBP M36L0R7060T1 M36L0R7060B1 WAIT VDDF 23 A0-A22 VSS AI13200 6/22 M36L0R7060T1, M36L0R7060B1 Table 1. Signal names Function Address inputs Common Data input/output Latch Enable input for Flash memory and PSRAM Burst Clock for Flash memory and PSRAM Wait Data in Burst Mode for Flash memory and PSRAM Flash memory power supply Flash power supply for I/O buffers Flash optional supply voltage for Fast Program & Erase Ground PSRAM power supply Not connected internally Do not use as internally connected Inputs I/O Input Input Output Description Signal name A0-A22 DQ0-DQ15 L K WAIT VDDF VDDQF VPPF VSS VCCP NC DU Flash memory EF GF WF RPF WPF PSRAM EP GP WP CRP UBP LBP Chip Enable input Output Enable input Write Enable input Chip Enable input Output Enable Input Write Enable input Reset input Write Protect input Direction Input Input Input Input Input Input Input Input Input Input Input Configuration Register Enable input Upper Byte Enable input Lower Byte Enable input 7/22 Description Figure 2. M36L0R7060T1, M36L0R7060B1 TFBGA connections (top view through package) 1 2 3 4 5 6 7 8 A DU DU DU DU B A4 A18 A19 VSS VDDF NC A21 A11 C A5 LBP NC VSS NC K A22 A12 D A3 A17 NC VPPF WP EP A9 A13 E A2 A7 NC WPF L A20 A10 A15 F A1 A6 UBP RPF WF A8 A14 A16 G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT NC H GP DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 NC J NC GF DQ9 DQ11 DQ4 DQ6 DQ15 VDDQF K EF DU DU NC VCCP NC VDDQF CRP L VSS VSS VDDQF VDDF VSS VSS VSS VSS M DU DU DU DU AI12023 8/22 M36L0R7060T1, M36L0R7060B1 Signal descriptions 2 Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connect-ed to this device. 2.1 Address inputs (A0-A22) Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. The other lines (A22) is an input for the Flash memory component only. The Address inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable signal (EF) and through the Write Enable signal (WF), while the PSRAM is accessed through the Chip Enable signal (EP) and the Write Enable signal (WP). 2.2 Data input/output (DQ0-DQ15) The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. For the PSRAM component, the upper Byte Data inputs/outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UBP) is driven Low. The lower Byte Data inputs/outputs (DQ0-DQ7) carry the data to or from the lower part of the selected address when Lower Byte Enable (LBP) is driven Low. When both UBP and LBP are disabled, the Data inputs/outputs are high impedance. 2.3 Latch Enable (L) The Latch Enable pin is common to the Flash memory and PSRAM components. For details of how the Latch Enable signal behaves, please refer to the datasheets of the respective memory components: M69KB096AM for the PSRAM and M58LR128HTB for the Flash memory. 2.4 Clock (K) The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AM for the PSRAM and M58LR128HTB for the Flash memory. 9/22 Signal descriptions M36L0R7060T1, M36L0R7060B1 2.5 Wait (WAIT) WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of how it behaves, please refer to the M69KB096AM datasheet for the PSRAM and to the M58LR128HTB datasheet for the Flash memory. 2.6 Flash Chip Enable (EF) The Flash Chip Enable input activates the control logic, input buffers, decoders and sense amplifiers of the Flash memory component. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.7 Flash Output Enable (GF) The Output Enable pin controls the data outputs during Flash memory Bus Read operations. 2.8 Flash Write Enable (WF) The Write Enable controls the Bus Write operation of the Flash memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. 2.9 Flash Write Protect (WPF) Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0R7000T1/B1 datasheet). 2.10 Flash Reset (RPF) The Reset input provides a hardware reset of the Flash memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to the M58LR128HTB datasheet, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied to VRPH (refer to the M58LR128HTB datasheet). 10/22 M36L0R7060T1, M36L0R7060B1 Signal descriptions 2.11 PSRAM Chip Enable input (EP) The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep Power-down mode, according to the RCR settings. 2.12 PSRAM Write Enable (WP) Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array. 2.13 PSRAM Output Enable (GP) When held Low, VIL, the Output Enable, GP, enables the Bus Read operations of the memory. 2.14 PSRAM Upper Byte Enable (UBP) The Upper Byte En-able, UBP, gates the data on the Upper Byte Data inputs/outputs (DQ8DQ15) to or from the upper part of the selected address during a Write or Read operation. 2.15 PSRAM Lower Byte Enable (LBP) The Lower Byte Enable, LBP, gates the data on the Lower Byte Data inputs/outputs (DQ0DQ7) to or from the lower part of the selected address during a Write or Read operation. If both LBP and UBP are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as EP remains Low. 2.16 PSRAM Configuration Register Enable (CRP) When this signal is driven High, VIH, bus read or write operations access either the value of the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to the value of A19. 2.17 VDDF supply voltage VDDF provides the power supply to the internal core of the Flash memory. It is the main power supply for all Flash memory operations (Read, Program and Erase). 2.18 VCCP supply voltage VCCP provides the power supply to the internal core of the PSRAM device. It is the main power supply for all PSRAM operations. 11/22 Signal descriptions M36L0R7060T1, M36L0R7060B1 2.19 VDDQF supply voltage VDDQF provides the power supply for the Flash I/O pins. This allows all outputs to be powered independently of the Flash core power supplies, VDDF and VCCP. 2.20 VPPF Program supply voltage VPPF is both a Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQF) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against Program or Erase, while VPP in the VPP1 range enables these functions (see the M58LR128HTB datasheet for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. 2.21 VSS ground VSS is the common ground reference for all voltage measurements in the Flash (core and I/O buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in a system should have their supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1 µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents. 12/22 M36L0R7060T1, M36L0R7060B1 Functional description 3 Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: EF for the Flash memory and EP for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is simultaneous read operations on one of the Flash memory and the PSRAM components which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. Figure 3. Functional block diagram A22 EF WF RPF WPF GF 128 Mbit Flash Memory WAIT K L A0-A21 VDDF VDDQF VPPF VCCP VSS DQ0-DQ15 EP GP WP CRP UBP LBP AI12024 64 Mbit PSRAM 13/22 Functional description Table 2. Main operating modes(1) (2)(3) M36L0R7060T1, M36L0R7060B1 Operation EF GF WF LF RPF WAITF(4) EP CRP GP A0A17 WP LBP,UBP A19 A18 A20A21 DQ15-DQ0 Flash Read Flash Write Flash Address Latch Flash Output Disable Flash Standby Flash Reset PSRAM Read PSRAM Write PSRAM Program Configuration Register (CR Controlled)(7) PSRAM Standby VIL VIL VIH VIL(5) VIH VIL VIH VIL VIL(5) VIH VIL X VIH VIL X X X VIH VIH VIH VIL Hi-Z Hi-Z Hi-Z VIL VIL The Flash memory must be disabled. VIL VIH X VIL X 00(RCR) BCR/ 10(BCR) RCR (8) Data VIL VIL VIL X VIH VIL VIL VIL Valid Valid Any PSRAM mode is allowed. PSRAM must be disabled. Flash Data Out Flash Data In Flash Data Out or Hi-Z(6) Hi-Z Hi-Z Hi-Z PSRAM data out PSRAM data in VIL VIH VIH VIH X X X X X Hi-Z VIH Any Flash mode is allowed. VIH VIL X X X X X X X X X X X X X Hi-Z Hi-Z PSRAM Deep Power-Down(9) 1. X = Don't care. 2. In the PSRAM, the Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in Standby and Deep Power-Down modes. 3. The PSRAM must have been configured to operate in asynchronous mode by setting BCR15 to ‘1’ (default value). 4. WAIT signal polarity is configured using the Set Configuration Register command. See the M58LR128HTB datasheet for details. 5. LF can be tied to VIH if the valid address has been previously latched. 6. Depends on GF. 7. BCR and RCR only. 8. A18 and A19 are used to select the BCR, RCR or DIDR registers. 9. Bit 4 of the Refresh Configuration Register must be set to ‘0’ and E must be maintained High, VIH, during Deep PowerDown mode. 14/22 M36L0R7060T1, M36L0R7060B1 Maximum rating 4 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 3. Symbol TA TBIAS TSTG VIO Absolute maximum ratings Value Parameter Min Ambient operating temperature Temperature under bias Storage temperature Input or output voltage –25 –25 –55 –0.2 –0.2 –0.2 Max 85 85 125 2.45 2.45 10 100 100 °C °C °C V V V mA hours Unit VDDF, VDDQF, Core and input/output supply VCCP voltages VPPF IO tVPPFH Flash program voltage Output short circuit current Time for VPPF at VPPFH 15/22 DC and AC parameters M36L0R7060T1, M36L0R7060B1 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC measurement conditions Flash memory Parameter Min VDDF supply voltage VCCP supply voltage VDDQF supply voltage VPPF supply voltage (Factory environment) VPPF supply voltage (Application PSRAM Unit Min – 1.7 – – – –25 30 16.7 Max – 1.95 – – – 85 V V V V V °C pF kΩ 2 0 to VCCP/2 VCCP/2 ns V V Max 1.95 – 1.95 9.5 VDDQF +0.4 85 30 16.7 5 1.7 – 1.7 8.5 –0.4 –25 environment) Ambient operating temperature Load capacitance (CL) Output circuit resistors (R1, R2) Input rise and fall times Input pulse voltages Input and output timing ref. voltages 0 to VDDQF VDDQF/2 Figure 4. AC measurement I/O waveform VDDQF VDDQF/2 0V AI06161b 16/22 M36L0R7060T1, M36L0R7060B1 Figure 5. AC measurement load circuit VDDQF DC and AC parameters VDDF VDDQF R1 DEVICE UNDER TEST 0.1µF 0.1µF CL R2 CL includes JIG capacitance AI08364c Table 5. Symbol CIN COUT Device capacitance Parameter Input capacitance Output capacitance Test Condition VIN = 0 V VOUT = 0 V Min Max(1) 14 18 Unit pF pF 1. Sampled only, not 100% tested. Please refer to the M58LR128HTB and M69KB096AM datasheets for further DC and AC characteristics values and illustrations. 17/22 Package mechanical M36L0R7060T1, M36L0R7060B1 6 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 6. TFBGA88 8 × 10 mm, 8 × 10 ball array - 0.8 mm pitch, package outline D D1 e SE E E2 E1 b BALL "A1" ddd FE FE1 A A1 FD SD A2 BGA-Z42 1. Drawing is not to scale. 18/22 M36L0R7060T1, M36L0R7060B1 Table 6. Package mechanical Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch, package mechanical data millimeters inches Max 1.200 0.200 0.850 0.350 8.000 5.600 0.100 10.000 7.200 8.800 0.800 1.200 1.400 0.600 0.400 0.400 – – 9.900 10.100 0.3937 0.2835 0.3465 0.0315 0.0472 0.0551 0.0236 0.0157 0.0157 – – 0.3898 0.300 7.900 0.400 8.100 0.0335 0.0138 0.3150 0.2205 0.0039 0.3976 0.0118 0.3110 0.0157 0.3189 0.0079 Typ Min Max 0.0472 Symbol Typ A A1 A2 b D D1 ddd E E1 E2 e FD FE FE1 SD SE Min 19/22 Part numbering M36L0R7060T1, M36L0R7060B1 7 Part numbering Table 7. Example: Device Type M36 = Multichip package (Multiple Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture 0 = No Die Operating Voltage R = VDDF = VCCP = VDDQF = 1.7 to 1.95V Flash 1 Density 7 = 128 Mbits Flash 2 Density 0 = No Die RAM 1 Density 6 = 64 Mbits RAM 0 Density 0 = No Die Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash Product Version 1 = 90 nm Flash technology Multilevel Design, 70 and 85 ns speed 0.11 µm PSRAM, 70 ns speed, burst mode Package ZAQ = Stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch Option E = ECOPACK® Standard packing F = ECOPACK® Tape & Reel packing Ordering information scheme M36 L 0 R 7 0 6 0 T 1 ZAQ E Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 20/22 M36L0R7060T1, M36L0R7060B1 Revision history 8 Revision history Table 8. Date 23-May-2006 31-Aug-2006 07-May-2007 13-Nov-2007 Document revision history Revision 0.1 0.2 1 2 First release. PSRAM changed to M69KM096AM. Blank and T removed below Option in Table 7: Ordering information scheme. Document status promoted from Target Specification to full Datasheet. 70 ns speed class and 66 MHz frequency added. Applied Numonyx branding. Changes 21/22 M36L0R7060T1, M36L0R7060B1 Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. 22/22