13192DSK-A0E

Freescale Semiconductor Technical Data Document Number: MC13192 Rev. 3.3, 04/2008 ed nd me . om 0x ec 32 t R C1 No e M Us MC13192 MC13192 Package Information Plastic Package Case 1311-03 (QFN-32) 2.4 GHz Low Power Transceiver for the IEEE® 802.15.4 Standard Ordering Information 1 Introduction Device Device Marking Package MC13192FC 13192 QFN-32 MC13192FCR2 (Tape and reel) 13192 QFN-32 Contents 1 2 3 4 5 6 7 8 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 4 Data Transfer Modes . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . 7 Functional Description . . . . . . . . . . . . . . . . 11 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 14 Applications Information . . . . . . . . . . . . . . . 17 Packaging Information . . . . . . . . . . . . . . . . . 23 for The MC13192 is a short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13192 contains a complete 802.15.4 physical layer (PHY) modem designed for the IEEE® 802.15.4 Standard which supports peer-to-peer, star, and mesh networking. . ns sig De When combined with an appropriate microcontroller (MCU), the MC13192 provide a cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor can be scaled to fit applications ranging from simple point-to-point systems, through complete ZigBee™ networking. w Ne The MC13192 includes the 802.15.4 PHY/MAC for use with the HCS08 Family of MCUs. The MC13192 can be used with Freescale’s IEEE 802.15.4 MAC and BeeStack, which is Freescale’s ZigBee 2006 compliant protocol stack. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007, 2008. All rights reserved. Features For more detailed information about MC13192 operation, refer to the MC13192 Reference Manual, (MC13192RM). ed nd me . om 0x ec 32 t R C1 No e M Us Applications include, but are not limited to, the following: • Remote control and wire replacement in industrial systems such as wireless sensor networks • Factory automation and motor control • Energy Management (lighting, HVAC, etc.) • Asset tracking and monitoring Potential consumer applications include: • Home automation and control (lighting, thermostats, etc.) • Human interface devices (keyboard, mice, etc.) • Remote control • Wireless toys The transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), PLL with internal voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with 5.0 MHz channel spacing per the 802.15.4 Standard. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control. 2 Features • . ns sig De • • • w Ne • • • for • • • • • • Supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode (compatible with the 802.15.4 Standard) Operates on one of 16 selectable channels in the 2.4 GHz band RX sensitivity of = 15 MHz - 25 31 42 41 49 - dB dB dB dB dB Frequency Error Tolerance - - 200 kHz Symbol Rate Error Tolerance - - 80 ppm Sensitivity for 1% Packet Error Rate (PER) (-40 to +85 °C) Sensitivity for 1% Packet Error Rate (PER) (+25 °C) Saturation (maximum input level) SENSmax for Table 5. Transmitter AC Electrical Characteristics (VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted. Parameters measured at connector J5 of evaluation circuit.) w Ne Characteristic Symbol Power Spectral Density (-40 to +85 °C) Absolute limit Power Spectral Density (-40 to +85 °C) Relative limit Pout Maximum Output Power2 EVM Output Power Control Range (-27 dBm to +4 dBm typical) Over the Air Data Rate 2nd Harmonic 3rd Harmonic 2 Max Unit - -47 - dBm - 47 - -3 0 3 4 Error Vector Magnitude 1 Typ . ns sig De Nominal Output Power1 Min dBm dBm - 20 35 % - 31 - dB - 250 - kbps - -42 - dBc - -44 - dBc SPI Register 12 programmed to 0x00BC which sets output power to nominal (0 dBm typical). SPI Register 12 programmed to 0x00FF which sets output power to maximum. MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 9 Electrical Characteristics Table 6. Digital Timing Specifications (VBATT, VDDINT = 2.7 V, TA = 25 °C, frequency = 16 MHz, unless otherwise noted. SPI timing parameters are referenced to Figure 8. Symbol T1 T2 T3 T4 T5 T6 T7 Min Typ Max Unit SPICLK period 125 nS Pulse width, SPICLK low 50 nS Pulse width, SPICLK high 50 nS ed nd me . om 0x ec 32 t R C1 No e M Us T0 Parameter Delay time, MISO data valid from falling SPICLK 15 nS Setup time, CE low to rising SPICLK 15 nS Delay time, MISO valid from CE low 15 nS Setup time, MOSI valid to rising SPICLK 15 nS Hold time, MOSI valid from rising SPICLK 15 nS RST minimum pulse width low (asserted) 250 nS Figure 6 shows a typical AC parameter evaluation circuit. J5 SMA J6 SMA 2 Y1 TSX-10A@16Mhz 1 1 2 4 2 3 T2 + C1 220pF + C2 220pF L1 8.2nH 1 2 3 4 5 6 7 8 RFINRFIN+ GND GND PAO+ PAOGND GPIO4 GPIO6 GPIO5 VDDINT VDDD IRQ CE MISO MOSI 24 23 22 21 20 19 18 17 J1 R1 47k GPIO1 R3 10k + IRQ w Ne MC13192 GPIO3 GPIO2 GPIO1 RST RXTXEN ATTN CLKO SPICLK 6.8nH R2 200 C6 0.1uF for L2 VDDA VBATT VDDVCO VDDLO1 VDDLO2 XTAL2 XTAL1 GPIO7 U1 32 31 30 29 28 27 26 25 C8 10pF C3 220pF Baud SEL 9 10 11 12 13 14 15 16 C7 10pF C5 9pF 5 1 5 T1 2450BL15B200 4 3 2450BL15B200 2 1 C4 9pF RTXENi RTXENi GPIO2 GPIO1 MOSI CE VCC R4 47k 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 J3 PA2 GPIO2 2 1 MCU RESET ATTN SPI_CLK MISO CLOCK Sel J7 1 2 3 MCU Interface ABEL RESET CLKO RESET . ns sig De 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 HEADER 10X2 Wake Up J4 16 MHz CLK R6 47k J2 1 2 RXD R5 47k Figure 6. Parameter Evaluation Circuit MC13192 Technical Data, Rev. 3.3 10 Freescale Semiconductor Functional Description 6 Functional Description 6.1 MC13192 Operational Modes ed nd me . om 0x ec 32 t R C1 No e M Us The MC13192 has a number of operational modes that allow for low-current operation. Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along with the transition times, in Table 7. Current drain in the various modes is listed in Table 3, DC Electrical Characteristics. Table 7. MC13192 Mode Definitions and Transition Times Mode Off Transition Time To or From Idle Definition All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated including 10 - 25 ms to Idle IRQ Hibernate Doze Idle Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is retained. 7 - 20 ms to Idle Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and can be programmed to enter Idle Mode through an internal timer comparator. (300 + 1/CLKO) µs to Idle Crystal Reference Oscillator On with CLKO output available. SPI active. Receive Crystal Reference Oscillator On. Receiver On. 144 µs from Idle Transmit Crystal Reference Oscillator On. Transmitter On. 144 µs from Idle for 6.2 Serial Peripheral Interface (SPI) w Ne The host microcontroller directs the MC13192, checks its status, and reads/writes data to the device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between the host and the MC13192 occurs as multiple 8-bit bursts on the SPI. The SPI signals are: 1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts. 2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13192. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK. . ns sig De NOTE For Freescale microcontrollers, the SPI clock format is the clock phase control bit CPHA = 0 and the clock polarity control bit CPOL = 0. 3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input. 4. Master In/Slave Out (MISO) - The MC13192 presents data to the master on the MISO output. A typical interconnection to a microcontroller is shown in Figure 7. MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 11 Functional Description MCU MC13192 Shift Register MISO TxD MOSI Sclk SPICLK ed nd me . om 0x ec 32 t R C1 No e M Us RxD Baud Rate Generator Chip Enable (CE) Shift Register CE Figure 7. SPI Interface Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock (CLKcore), derived from the crystal reference oscillator, to communicate from the SPI registers to internal registers and memory. 6.2.1 SPI Burst Operation The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master (MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the master on the MISO line. Although an MC13192 transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in Figure 8. SPI Burst 1 2 3 4 for CE 5 T4 Valid T6 T5 T1 T3 Valid Valid T0 . ns sig De MOSI 8 T2 T7 MISO 7 w Ne SPICLK 6 Figure 8. SPI Single Burst Timing Diagram SPI digital timing specifications are shown in Table 6. MC13192 Technical Data, Rev. 3.3 12 Freescale Semiconductor Functional Description 6.2.2 SPI Transaction Operation ed nd me . om 0x ec 32 t R C1 No e M Us Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13192 requires that a complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and identifies the access as being a read or write operation. In this context, a write is data written to the MC13192 and a read is data written to the SPI master. The following SPI bursts will be either the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid). Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13192 never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. After the final SPI burst, CE is negated to high to signal the end of the transaction. Refer to the MC13192 Reference Manual, (MC13192RM) for more details on SPI registers and transaction types. An example SPI read transaction with a 2-byte payload is shown in Figure 9. CE Clock Burst SPICLK MISO MOSI Valid Valid Valid for Header Read data Figure 9. SPI Read Transaction Diagram w Ne . ns sig De MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 13 Pin Connections 7 Pin Connections Table 8. Pin Function Description Pin # 2 3 4 5 6 7 Type Description RFIN- RF Input LNA negative differential input. RFIN+ RF Input LNA positive differential input. Functionality ed nd me . om 0x ec 32 t R C1 No e M Us 1 Pin Name Not Used Tie to Ground. Not Used Tie to Ground. PAO+ RF Output /DC Input Power Amplifier Positive Output. Open drain. Connect to VDDA. PAO- RF Output/DC Input Power Amplifier Negative Output. Open drain. Connect to VDDA. SM Test mode pin. Tie to Ground Tie to Ground for normal operation Digital Input/ Output General Purpose Input/Output 4. See Footnote 1 GPIO31 Digital Input/ Output General Purpose Input/Output 3. See Footnote 1 GPIO21 Digital Input/ Output General Purpose Input/Output 2. When gpio_alt_en, Register 9, Bit 7 = 1, GPIO2 functions as a “CRC Valid” indicator. See Footnote 1 GPIO11 Digital Input/ Output General Purpose Input/Output 1. When gpio_alt_en, Register 9, Bit 7 = 1, GPIO1 functions as an “Out of Idle” indicator. See Footnote 1 12 RST Digital Input Active Low Reset. While held low, the IC is in Off Mode and all internal information is lost from RAM and SPI registers. When high, IC goes to IDLE Mode, with SPI in default state. 13 RXTXEN2 Digital Input Active High. Low to high transition initiates RX or TX See Footnote 2 sequence depending on SPI setting. Should be taken high after SPI programming to start RX or TX sequence and should be held high through the sequence. After sequence is complete, return RXTXEN to low. When held low, forces Idle Mode. 14 ATTN2 Digital Input Active Low Attention. Transitions IC from either Hibernate or Doze Modes to Idle. 15 CLKO Digital Output Clock output to host MCU. Programmable frequencies of: 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5 kHz, 32.786+ kHz (default), and 16.393+ kHz. 16 SPICLK2 Digital Clock Input External clock input for the SPI interface. See Footnote 2 17 MOSI2 Digital Input Master Out/Slave In. Dedicated SPI data input. See Footnote 2 18 MISO3 Digital Output Master In/Slave Out. Dedicated SPI data output. See Footnote 3 19 CE2 Digital Input Active Low Chip Enable. Enables SPI transfers. See Footnote 2 9 10 11 for GPIO41 8 w Ne . ns sig De See Footnote 2 MC13192 Technical Data, Rev. 3.3 14 Freescale Semiconductor Pin Connections Table 8. Pin Function Description (continued) Pin # 20 IRQ Type Description Digital Output Functionality Active Low Interrupt Request. Open drain device. Programmable 40 kΩ internal pull-up. Interrupt can be serviced every 6 µs with 4 kΩ. ed nd me . om 0x ec 32 t R C1 No e M Us 21 Pin Name Power Output Digital regulated supply bypass. Decouple to ground. VDDINT Power Input Digital interface supply & digital regulator input. Connect to Battery. 2.0 to 3.4 V. Decouple to ground. GPIO51 Digital Input/Output General Purpose Input/Output 5. See Footnote 1 GPIO61 Digital Input/Output General Purpose Input/Output 6. See Footnote 1 GPIO71 Digital Input/Output General Purpose Input/Output 7. See Footnote 1 XTAL1 Input Crystal Reference oscillator input. Connect to 16 MHz crystal and load capacitor. XTAL2 Input/Output Crystal Reference oscillator output Note: Do not load this pin by using it as a 16 MHz source. Measure 16 MHz output at Pin 15, CLKO, programmed for 16 MHz. See the MC13192 Reference Manual for details. Connect to 16 MHz crystal and load capacitor. 28 VDDLO2 Power Input LO2 VDD supply. Connect to VDDA externally. 29 VDDLO1 Power Input LO1 VDD supply. Connect to VDDA externally. 30 VDDVCO Power Output VCO regulated supply bypass. Decouple to ground. 31 VBATT Power Input Analog voltage regulators Input. Connect to Battery. Decouple to ground. 32 VDDA Power Output Analog regulated supply Output. Connect to directly Decouple to ground. VDDLO1 and VDDLO2 externally and to PAO± through a frequency trap. Note: Do not use this pin to supply circuitry external to the chip. EP Ground 22 23 24 25 26 27 for VDDD w Ne 1 . ns sig De External paddle / flag ground. Connect to ground. The transceiver GPIO pins default to inputs at reset. There are no programmable pullups on these pins. Unused GPIO pins should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state. 2 During low power modes, input must remain driven by MCU. 3 By default MISO is tri-stated when CE is negated. For low power operation, miso_hiz_en (Bit 11, Register 07) should be set to zero so that MISO is driven low when CE is negated. MC13192 Technical Data, Rev. 3.3 Freescale Semiconductor 15 Pin Connections PAO+ GPIO7 IRQ MC13192 PAO- CE GPIO4 9 10 11 12 13 14 MISO 15 SPICLK SM CLKO 8 EP ATTN 7 VDDD RXTXEN 6 NC RST 5 GPIO5 VDDINT GPIO1 4 GPIO6 NC GPIO2 3 25 RFIN+ GPIO3 2 RFIN- 26 XTAL1 27 XTAL2 28 VDDLO2 29 VDDLO1 VDDVCO VBATT 30 ed nd me . om 0x ec 32 t R C1 No e M Us 1 31 VDDA 32 MOSI 24 23 22 21 20 19 18 17 16 for Figure 10. Pin Connections (Top View) w Ne . ns sig De MC13192 Technical Data, Rev. 3.3 16 Freescale Semiconductor Applications Information 8 Applications Information This section provides application specific information regarding crystal oscillator reference frequency, a basic design example for interfacing the MC13192 to an MCU and recommended crystal usage. Crystal Oscillator Reference Frequency ed nd me . om 0x ec 32 t R C1 No e M Us 8.1 The 802.15.4 Standard requires that several frequency tolerances be kept within ± 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13192 transceiver provides onboard crystal trim capacitors to assist in meeting this performance. for The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them: 1. The initial (or make) tolerance of the crystal resonant frequency itself. 2. The variation of the crystal resonant frequency with temperature. 3. The variation of the crystal resonant frequency with time, also commonly known as aging. 4. The variation of the crystal resonant frequency with load capacitance, also commonly known as pulling. This is affected by: a) The external load capacitor values - initial tolerance and variation with temperature. b) The internal trim capacitor values - initial tolerance and variation with temperature. c) Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. w Ne Freescale requires the use of a 16 MHz crystal with a