74ABT16240ADGG

74ABT16240A 16-bit inverting buffer/line driver; 3-state Rev. 04 — 25 March 2009 Product data sheet 1. General description The 74ABT16240A high-performance Bipolar CMOS (BiCMOS) device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16240A is an inverting 16-bit buffer that is ideal for driving bus lines. The device features four output enable inputs (1OE, 2OE, 3OE, 4OE), each controlling four of the 3-state outputs. 2. Features I I I I I I I I I I 16-bit bus interface Multiple VCC and GND pins minimize switching noise Power-up 3-state 3-state buffers TTL input and output switching levels Input and output interface capability to systems at 5 V supply Output capability: +64 mA and −32 mA Live insertion and extraction permitted Latch-up performance: JESD 78 Class II ESD protection: N MIL STD 883 method 3015: exceeds 2000 V N CDM JESD 22-C101-C exceeds 1000 V 3. Ordering information Table 1. Ordering information Package Temperature range Name 74ABT16240ADGG 74ABT16240ADL −40 °C to +85 °C −40 °C to +85 °C TSSOP48 SSOP48 Description plastic thin shrink small outline package; 48 leads; body width 6.1 mm Version SOT362-1 Type number plastic shrink small outline package; 48 leads; body SOT370-1 width 7.5 mm NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 4. Functional diagram 1 1OE 48 2OE 25 3OE 24 4OE 1A0 1A1 43 1A3 1OE 1Y3 6 32 3A3 3OE 3Y3 17 1A2 1A3 1 25 2Y0 2A0 2A1 41 40 2A0 8 9 30 29 4A0 4Y0 19 20 2A2 2A3 3A0 3A1 3A2 22 3A3 4A0 23 4A1 4A2 48 2OE 24 4OE 001aad261 47 46 1A0 1Y0 2 3 36 35 3A0 3Y0 13 14 1A1 1Y1 3A1 3Y1 EN1 EN2 EN3 EN4 1 1 2 3 5 6 1 2 8 9 11 12 1 3 13 14 16 17 1 4 19 20 22 23 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3 44 1A2 1Y2 5 33 3A2 3Y2 16 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 2A1 2Y1 4A1 4Y1 38 2A2 2Y2 11 27 4A2 4Y2 37 2A3 2Y3 12 26 4A3 4Y3 4A3 001aad262 Fig 1. Logic symbol Fig 2. IEC logic symbol 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 2 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 5. Pinning information 5.1 Pinning 1OE 1Y0 1Y1 GND 1Y2 1Y3 VCC 2Y0 2Y1 1 2 3 4 5 6 7 8 9 48 2OE 47 1A0 46 1A1 45 GND 44 1A2 43 1A3 42 VCC 41 2A0 40 2A1 39 GND 38 2A2 37 2A3 36 3A0 35 3A1 34 GND 33 3A2 32 3A3 31 VCC 30 4A0 29 4A1 28 GND 27 4A2 26 4A3 25 3OE 001aaj891 GND 10 2Y2 11 2Y3 12 3Y0 13 3Y1 14 GND 15 3Y2 16 3Y3 17 VCC 18 4Y0 19 4Y1 20 GND 21 4Y2 22 4Y3 23 4OE 24 74ABT16240A Fig 3. Pin configuration 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 3 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 5.2 Pin description Table 2. Symbol 1OE 1Y[0:3] GND VCC 2Y[0:3] GND 3Y[0:3] GND VCC 4Y[0:3] GND 4OE 3OE GND 4A[0:3] VCC GND 3A[0:3] GND 2A[0:3] VCC GND 1A[0:3] 2OE Pin description Pin 1 2, 3, 5, 6 4 7 8, 9, 11, 12 10 15 18 21 24 25 28 31 34 39 42 45 48 Description 1 output enable (LOW active) 1 data output 0 to output 3 ground (0 V) supply voltage 2 data output 0 to output 3 ground (0 V) ground (0 V) supply voltage ground (0 V) 4 output enable (LOW active) 3 output enable (LOW active) ground (0 V) supply voltage ground (0 V) ground (0 V) supply voltage ground (0 V) 2 output enable (LOW active) 13, 14, 16, 17 3 data output 0 to output 3 19, 20, 22, 23 4 data output 0 to output 3 30, 29, 27, 26 4 data input 0 to input 3 36, 35, 33, 32 3 data input 0 to input 3 41, 40, 38, 37 2 data input 0 to input 3 47, 46, 44, 43 1 data input 0 to input 3 6. Functional description Table 3. Control nOE L L H [1] Function table[1] Input nAx L H X Output nYx H L Z H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 4 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VO IIK IOK IO Tj Tstg [1] [2] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current junction temperature storage temperature Conditions [1] Min −0.5 −1.2 −0.5 −18 −50 [2] Max +7.0 +7.0 +5.5 128 −64 150 +150 Unit V V V mA mA mA mA °C °C output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state output in HIGH-state [1] −65 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 8. Recommended operating conditions Table 5. Operating conditions Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VIH VIL IOH IOL Parameter supply voltage input voltage HIGH-level input voltage LOW-level Input voltage HIGH-level output current LOW-level output current duty cycle ≤ 50 %; fi ≥ 1 kHz ∆t/∆V Tamb input transition rise and fall rate ambient temperature in free air Conditions Min 4.5 0 2.0 −32 −40 Typ Max 5.5 VCC 0.8 32 64 10 +85 Unit V V V V mA mA mA ns/V °C 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 5 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 9. Static characteristics Table 6. Symbol VIK VOH Static characteristics Parameter Conditions Min input clamping voltage VCC = 4.5 V; IIK = −18 mA HIGH-level output voltage VI = VIL or VIH VCC = 4.5 V; IOH = −3 mA VCC = 5.0 V; IOH = −3 mA VCC = 4.5 V; IOH = −32 mA VOL II IOFF IO(pu/pd) IOZ LOW-level output voltage input leakage current power-off leakage current VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH VCC = 5.5 V; VI = GND or 5.5 V VCC = 0 V; VI or VO ≤ 4.5 V [1] 25 °C Typ −0.9 2.9 3.4 2.4 0.42 Max −1.2 0.55 2.5 3.0 2.0 - −40 °C to +85 °C Unit Min 2.5 3.0 2.0 Max −1.2 0.55 ±1.0 ±100 ±50 V V V V V µA µA µA ±0.01 ±1.0 ±5.0 ±5.0 ±100 ±50 power-up/power-down VCC = 2.0 V; VO = 0.5 V; output current VI = GND or VCC; nOE = VCC OFF-state output current VCC = 5.5 V; VI = VIL or VIH output HIGH-state at VO = 5.5 V output LOW-state at VO = 0.5 V [2] 1.0 −1.0 1.0 −70 0.5 8 0.5 10 10 −10 50 −180 1.0 19 1.0 200 −50 - 10 −10 50 −180 1.0 19 1.0 200 µA µA µA mA mA mA mA µA ILO IO ICC output leakage current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC output current supply current VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; VI = GND or VCC outputs HIGH-state outputs LOW-state outputs 3-state −50 - ∆ICC additional supply current input capacitance input/output capacitance per input pin; VCC = 5.5 V; one input at 3.4 V and other inputs at VCC or GND VI = 0 V or VCC outputs disabled; VO = 0 V or VCC [1][3] - CI CI/O - 4 6 - - - pF pF [1] [2] [3] This is the increase in supply current for each input at 3.4 V. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This data sheet limit may vary among suppliers. 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 6 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V. For test circuit, see Figure 6. Symbol Parameter Conditions 25 °C; VCC = 5.0 V Min tPLH tPHL tPZH tPZL tPHZ tPLZ LOW to HIGH propagation delay HIGH to LOW propagation delay OFF-state to HIGH propagation delay OFF-state to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay nAx to nYx, see Figure 4 nAx to nYx, see Figure 4 nOE to nYx; see Figure 5 nOE to nYx; see Figure 5 nOE to nYx; see Figure 5 nOE to nYx; see Figure 5 1.0 1.0 1.2 1.2 1.3 1.3 Typ 2.0 1.5 2.4 2.3 2.7 2.5 Max 3.0 3.0 3.3 3.2 4.1 3.6 −40 °C to +85 °C; Unit VCC = 5.0 V ± 0.5 V Min 1.0 1.0 1.2 1.0 1.6 1.4 Max 3.7 3.5 4.2 4.2 4.7 4.1 ns ns ns ns ns ns 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 7 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 11. Waveforms VI input nAx 0V t PHL VOH output nYx VOL 001aad264 VM VM t PLH VM VM VM = 1.5 V; VOL and VOH are typical voltage output levels that occur with the output load. Fig 4. Input (nAx) to output (nYx) propagation delay VI nOE input GND tPZL 3.5 V nYx output VOL tPZH VOH nYx output 0V 001aaj892 VM tPLZ VM VOL + 0.3 V tPHZ VOH − 0.3 V VM VM = 1.5 V; VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. 3-state output enable and disable times 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 8 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 12. Test information tW 90 % VM 10 % tf tr VI positive pulse 0V 10 % tW 001aac221 VI negative pulse 0V 90 % VM tr tf 90 % VM VM 10 % VM = 1.5 V. a. Input pulse definition VEXT VCC VI DUT RT CL RL RL PULSE GENERATOR VO 001aac764 Test data is given in Table 8. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. b. Test circuit for 3-state outputs Fig 6. Table 8. Input VI 3.0 V fi 1 MHz tW 500 ns tr, tf 2.5 ns Load circuitry for switching times Test data Load CL 50 pF RL 500 Ω VEXT tPHZ, tPZH open tPLZ, tPZL 7.0 V tPLH, tPHL open 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 9 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 13. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c y HE vMA Z 48 25 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp 24 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 7. Package outline SOT362-1 (TSSOP48) 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 10 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE vM A Z 48 25 Q A2 A1 (A 3) θ Lp 1 bp 24 wM L detail X A pin 1 index e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 8. Package outline SOT370-1 (SSOP48) 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 11 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 14. Abbreviations Table 9. Acronym ESD TTL Abbreviations Description ElectroStatic Discharge Transistor-Transistor Logic 15. Revision history Table 10. Revision history Release date 20090325 Data sheet status Product data sheet Change notice Supersedes 74ABT16240A_3 Document ID 74ABT16240A_4 Modifications: • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Product specification Product specification Product specification 01-A15420 853-1880 19019 74ABT_H16240A_2 74ABT_H16240A - 74ABT16240A_3 (9397 750 12893) 74ABT_H16240A_2 (9397 750 03481) 74ABT_H16240A 20040212 19980225 19961001 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 12 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 13 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 March 2009 Document identifier: 74ABT16240A_4