74ABT374APW,118

74ABT374A Octal D-type flip-flop; positive-edge trigger; 3-state Rev. 2 — 18 December 2012 Product data sheet 1. General description The 74ABT374A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT374A is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The two sections of the device are controlled independently by the clock input (CP) and output enable input (OE) control gates. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active LOW output enable (OE) controls all eight 3-state buffers independent of the clock operation. When OE is LOW, the stored data appears at the outputs. When OE is HIGH, the outputs are in the high-impedance “OFF” state, which means they will neither drive nor load the bus. 2. Features and benefits        8-bit positive edge triggered register 3-state output buffers Power-on 3-state Power-on reset Output capability: +64 mA/32 mA Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Live insertion/extraction permitted 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT374AN 40 C to +85 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 74ABT374AD 40 C to +85 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74ABT374ADB 40 C to +85 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74ABT374APW 40 C to +85 C 4. Functional diagram 1 EN 11 C1 11 3 CP 3 4 7 8 13 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 14 18 D6 Q6 D7 Q7 5 6 7 6 9 8 9 12 13 12 14 15 17 16 18 19 15 Q5 16 19 OE mna891 1 Fig 1. mna196 Logic symbol D0 Fig 2. D1 D Q D2 D CP Q D3 D CP FF1 2 1D 4 5 Q4 D5 17 2 Q FF2 D4 D CP Q D5 D CP FF3 IEC logic symbol Q D CP FF4 D6 Q D CP FF5 D7 Q D CP FF6 Q CP FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aah077 Fig 3. Logic diagram 74ABT374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 2 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state 5. Pinning information 5.1 Pinning $%7$ $%7$ 2(   9&& 2(   9&& 4   4 4   4 '   ' '   ' '   ' '   ' 4   4 4   4 4   4 4   4 '   ' '   ' '   ' '   ' 4   4 4   4 *1'   &3 *1'   &3  Fig 4. DDD Pin configuration for DIP20 and SO20 Fig 5. Pin configuration for SSOP20 and TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 3-state output enable input (active LOW) D0, D1, D2, D3, D4, D5, D6, D7 3, 4, 7, 8, 13, 14, 17, 18 data input GND 10 ground (0 V) CP 11 clock pulse input (active rising edge) Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 5, 6, 9, 12, 15, 16, 19 3-state flip-flop output VCC 20 supply voltage 6. Functional description Table 3. Function table[1] Operating mode OE CP Dn Internal flip-flop Load and read register L  l L L  h H H Load register and disable output H  l L Z H  h H Z [1] Input Output L Qn H = HIGH voltage level h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition L = LOW voltage level l = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition Z = high-impedance OFF-state  = LOW-to-HIGH clock transition 74ABT374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 3 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7.0 V [1] 1.2 +7.0 V [1] 0.5 +5.5 V VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input clamping current VI < 0 V 18 - mA IOK output clamping current VO < 0 V 50 - mA IO output current output in LOW-state Tj junction temperature Tstg storage temperature [2] - 128 mA - 150 C 65 +150 C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 8. Recommended operating conditions Table 5. Operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC supply voltage 4.5 VI input voltage 0 VIH HIGH-level input voltage 2.0 VIL LOW-level input voltage Typ Max Unit - 5.5 V - VCC V - - V - - 0.8 V IOH HIGH-level output current 32 - - mA IOL LOW-level output current - - 64 mA t/V input transition rise and fall rate 0 - 10 ns/V Tamb ambient temperature 40 - +85 C in free air 9. Static characteristics Table 6. Static characteristics Symbol Parameter Min Typ Max Min Max VIK input clamping voltage VCC = 4.5 V; IIK = 18 mA 1.2 0.9 - 1.2 - V VOH HIGH-level output voltage VCC = 4.5 V; IOH = 3 mA 2.5 2.9 - 2.5 - V VCC = 5.0 V; IOH = 3 mA 3.0 3.4 - 3.0 - V VCC = 4.5 V; IOH = 32 mA 2.0 2.4 - 2.0 - V - 0.42 0.55 - 0.55 V VOL LOW-level output voltage 74ABT374A Product data sheet 25 C Conditions 40 C to +85 C Unit VI = VIL or VIH VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 4 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state Table 6. Static characteristics …continued Symbol Parameter 25 C Conditions [1] 40 C to +85 C Unit Min Typ Max Min Max - 0.13 0.55 - 0.55 V VOL(pu) power-up LOW-level output voltage VCC = 5.5 V; IO = 1 mA; VI = GND or VCC II input leakage current VCC = 5.5 V; VI = VCC or GND - 0.01 1.0 - 1.0 A IOFF power-off leakage current VCC = 0 V; VI or VO  4.5 V - 5.0 100 - 100 A IO(pu/pd) power-up/power-down VCC = 2.0 V; VO = 0.5 V; output current VI = GND or VCC; OE HIGH - 5.0 50 - 50 A IOZ OFF-state output current VO = 2.7 V - 5.0 50 - 50 A VO = 0.5 V 50 5.0 - 50 - A - 5.0 50 - 50 A 50 180 50 mA [2] VCC = 5.5 V; VI = VIL or VIH ILO output leakage current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC IO output current VCC = 5.5 V; VO = 2.5 V ICC supply current VCC = 5.5 V; VI = GND or VCC [3] 180 100 outputs HIGH-state - 110 250 - 250 A outputs LOW-state - 24 30 - 30 mA - 110 250 - 250 A - 0.5 1.5 - 1.5 mA outputs disabled ICC additional supply current per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND CI input capacitance VI = 0 V or VCC - 4 - - - pF CO output capacitance outputs disabled; VO = 0 V or VCC - 7 - - - pF [4] [1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. [2] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V  10 % a transition time of up to 100 s is permitted. [3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. [4] This is the increase in supply current for each input at 3.4 V. 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 9. Symbol Parameter 25 C; VCC = 5.0 V Conditions 40 C to +85 C; Unit VCC = 5.0 V  0.5 V Min Typ Max Min Max fmax maximum frequency see Figure 6 200 300 - 200 - tPLH LOW to HIGH propagation delay CP to Qn; see Figure 6 1.7 3.4 4.5 1.7 5.1 ns tPHL HIGH to LOW propagation delay CP to Qn; see Figure 6 2.0 3.8 4.9 2.0 5.2 ns tPZH OFF-state to HIGH propagation delay OE to Qn; see Figure 8 1.2 3.5 4.5 1.2 5.4 ns 74ABT374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 MHz © NXP B.V. 2012. All rights reserved. 5 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state Table 7. Dynamic characteristics …continued GND = 0 V; for test circuit, see Figure 9. Symbol Parameter 25 C; VCC = 5.0 V Conditions 40 C to +85 C; Unit VCC = 5.0 V  0.5 V Min Typ Max Min Max tPZL OFF-state to LOW propagation delay OE to Qn; see Figure 8 2.2 4.3 5.4 2.2 6.2 ns tPHZ HIGH to OFF-state propagation delay OE to Qn; see Figure 8 1.8 3.6 4.7 1.8 5.2 ns tPLZ LOW to OFF-state propagation delay OE to Qn; see Figure 8 1.5 3.0 4.1 1.5 4.3 ns tsu(H) set-up time HIGH Dn to CP; see Figure 7 1.5 0.6 - 1.5 - ns tsu(L) set-up time LOW Dn to CP; see Figure 7 1.2 0.3 - 1.2 - ns th(H) hold time HIGH CP to Dn; see Figure 7 1.0 0.3 - 1.0 - ns th(L) hold time LOW CP to Dn; see Figure 7 1.0 0.5 - 1.0 - ns tWH pulse width HIGH CP; see Figure 6 2.0 0.8 - 2.0 - ns tWL pulse width LOW CP; see Figure 6 2.8 1.0 - 2.8 - ns 11. Waveforms 1 / fmax VI CP input VM GND tWH tWL tPHL tPLH VOH VM Qn output VOL 001aac445 VM = 1.5 V VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and maximum clock (CP) frequency 74ABT374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 6 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state Vl VM Dn input VM VM VM GND t su(H) t h(H) t su(L) t h(L) Vl VM CP input VM GND 001aac738 VM = 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 7. Set-up and hold times data output (Dn) to clock (CP) VI OE input VM GND tPZL tPLZ 3.5 V VM Qn output VOL + 0.3 V VOL tPZH tPHZ VOH Qn output VM VOH − 0.3 V GND 001aac448 VM = 1.5 V VOL and VOH are typical output voltage levels that occur with the output load Fig 8. 3-state output (Qn) enable and disable times 74ABT374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 7 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state VI tW 90 % 90 % negative pulse VM 0V VCC 10 % tf tr tr tf VI 90 % positive pulse 0V VEXT VM 10 % VI VM DUT RT 90 % RL VO G CL RL VM 10 % mna616 10 % tW 001aai298 a. Input pulse definition b. Test circuit Test data is given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 8. Test circuit for measuring switching times Test data Input Load VEXT VI fi tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns  2.5 ns 50 pF 500  open open 7.0 V 74ABT374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 8 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state 12. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 D e e1 L ME MH w Z (1) max. 6.40 6.22 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2 0.25 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.078 (1) E (1) Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC JEITA MS-001 SC-603 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 10. Package outline SOT146-1 (DIP20) 74ABT374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 9 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT163-1 (SO20) 74ABT374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 10 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT339-1 (SSOP20) 74ABT374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 11 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT360-1 (TSSOP20) 74ABT374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 12 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state 13. Abbreviations Table 9. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ABT374A v.2 20121218 Product data sheet - 74ABT374A v.1 Modifications: 74ABT374A v.1 74ABT374A Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 19950906 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 - © NXP B.V. 2012. All rights reserved. 13 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74ABT374A Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 14 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74ABT374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 15 of 16 74ABT374A NXP Semiconductors Octal D-type flip-flop; positive-edge trigger; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 December 2012 Document identifier: 74ABT374A