74AHC126D

74AHC126; 74AHCT126 Quad buffer/line driver; 3-state Rev. 04 — 12 August 2009 Product data sheet 1. General description The 74AHC126; 74AHCT126 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC126; 74AHCT126 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state. The 74AHC126; 74AHCT126 is identical to the 74AHC125; 74AHCT125 but has active HIGH output enable inputs. 2. Features I I I I Balanced propagation delays All inputs have Schmitt-trigger action Inputs accept voltages higher than VCC Input levels: N For 74AHC126: CMOS level N For 74AHCT126: TTL level I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range 74AHC126D 74AHCT126D 74AHC126PW 74AHCT126PW 74AHC126BQ 74AHCT126BQ −40 °C to +125 °C −40 °C to +125 °C TSSOP14 −40 °C to +125 °C Name SO14 Description plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT108-1 SOT402-1 SOT762-1 Type number DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 4. Functional diagram 2 1 5 4 9 10 12 13 1A 1OE 2A 2OE 3A 3OE 4A 4OE 1Y 3 2Y 6 3Y 8 4Y 11 mna235 Fig 1. Functional diagram 2 1 5 EN1 1 3 6 4 9 8 10 nA nY 12 11 13 nOE mna234 mna236 Fig 2. Logic symbol Fig 3. IEC logic symbol 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 2 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state 5. Pinning information 5.1 Pinning 74AHC126 74AHCT126 1OE 1A 1Y 2OE 2A 2Y GND 1 2 3 4 5 6 7 001aac982 74AHC126 74AHCT126 1OE 2 3 4 5 6 7 GND 3Y 8 GND(1) 1 13 4OE 12 4A 11 4Y 10 3OE 9 8 3A 3Y 14 VCC terminal 1 index area 1A 1Y 2OE 2A 2Y 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 001aak180 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Symbol 1OE 1A 1Y 2OE 2A 2Y GND 3Y 3A 3OE 4Y 4A 4OE VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description output enable input 1 (active HIGH) data input 1 data output 1 output enable input 2 (active HIGH) data input 2 data output 2 ground (0 V) data output 3 data input 3 output enable input 3 (active HIGH) data output 4 data input 4 output enable input 4 (active HIGH) supply voltage 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 3 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state 6. Functional description Table 3. Control nOE H H L [1] H = HIGH voltage state; L = LOW voltage state; X = don’t care; Z = high-impedance OFF-state. Function table[1] Input nA L H X Output nY L H Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions Min −0.5 −0.5 Max +7.0 +7.0 +20 +25 +75 +150 500 Unit V V mA mA mA mA mA °C mW VI < −0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) [1] [1] −20 −20 −25 −75 −65 Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K. 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 4 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state 8. Recommended operating conditions Table 5. Symbol 74AHC126 VCC VI VO Tamb ∆t/∆V 74AHCT126 VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 4.5 V to 5.5 V 4.5 0 0 −40 5.0 +25 5.5 5.5 VCC +125 20 V V V °C ns/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 2.0 0 0 −40 5.0 +25 5.5 5.5 VCC +125 100 20 V V V °C ns/V ns/V Operating conditions Parameter Conditions Min Typ Max Unit 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74AHC126 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V IO = −50 µA; VCC = 3.0 V IO = −50 µA; VCC = 4.5 V IO = −4.0 mA; VCC = 3.0 V IO = −8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V IO = 50 µA; VCC = 3.0 V IO = 50 µA; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V 74AHC_AHCT126_4 Conditions Min 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 - 25 °C Typ 2.0 3.0 4.5 0 0 0 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 −40 °C to +85 °C −40 °C to +125 °C Unit Min 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.80 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 Min 1.5 2.1 3.85 1.9 2.9 4.4 2.40 3.70 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 V V V V V V V V V V V V V V V V © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 5 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter II IOZ input leakage current Conditions Min VI = 5.5 V or GND; VCC = 0 V to 5.5 V 25 °C Typ Max 0.1 ±0.25 −40 °C to +85 °C −40 °C to +125 °C Unit Min Max 1.0 ±2.5 Min Max 2.0 ±10.0 µA µA OFF-state VI = VIH or VIL; output current VO = VCC or GND; VCC = 5.5 V supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance output capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VCC or GND ICC CI CO - 3 4 2.0 10 - - 20 10 - - 40 10 - µA pF pF 74AHCT126 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 4.4 3.94 - 4.5 0 - 0.1 0.36 0.1 ±0.25 4.4 3.80 - 0.1 0.44 1.0 ±2.5 4.4 3.70 - 0.1 0.55 2.0 ±10.0 V V V V µA µA VOL II IOZ OFF-state VI = VIH or VIL; output current VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; supply current VI = VCC − 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V input capacitance output capacitance VI = VCC or GND ICC ∆ICC - - 2.0 1.35 - 20 1.5 - 40 1.5 µA mA CI CO - 3 4 10 - - 10 - - 10 - pF pF 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 6 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 74AHC126 tpd propagation delay nA to nY; see Figure 6 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF ten enable time nOE to nY; see Figure 7 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tdis disable time nOE to nY; see Figure 7 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power fi = 1 MHz; dissipation VI = GND to VCC capacitance propagation delay nA to nY; see Figure 6 CL = 15 pF CL = 50 pF ten enable time nOE to nY; see Figure 7 CL = 15 pF CL = 50 pF tdis disable time nOE to nY; see Figure 7 CL = 15 pF CL = 50 pF CPD power fi = 1 MHz; dissipation VI = GND to VCC capacitance [5] [4] [3] [5] [4] [3] [2] Conditions Min 25 °C Typ[1] Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 4.7 6.7 3.3 4.7 8.0 11.5 5.5 7.5 1.0 1.0 1.0 1.0 9.5 13.0 6.5 8.5 1.0 1.0 1.0 1.0 10.0 14.5 7.0 9.5 ns ns ns ns - 5.3 7.6 3.6 5.1 8.0 11.5 5.3 7.6 1.0 1.0 1.0 1.0 9.5 13.0 6.1 8.7 1.0 1.0 1.0 1.0 10.0 14.5 7.0 9.5 ns ns ns ns - 6.6 9.4 4.7 6.7 10 9.7 13.2 6.8 8.8 - 1.0 1.0 1.0 1.0 - 11.5 15.0 8.0 10.0 - 1.0 1.0 1.0 1.0 - 12.5 16.5 8.5 11.0 - ns ns ns ns pF 74AHCT126; VCC = 4.5 V to 5.5 V tpd [2] - 3.0 4.3 3.3 4.7 4.8 6.9 12 5.5 7.5 5.1 7.1 6.8 8.9 - 1.0 1.0 1.0 1.0 1.0 1.0 - 6.5 8.5 6.0 8.0 8.0 10.0 - 1.0 1.0 1.0 1.0 1.0 1.0 - 7.0 9.5 6.5 9.0 8.5 11.5 - ns ns ns ns ns ns pF 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 7 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state [1] [2] [3] [4] [5] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 11. Waveforms VI nA input VM GND tPHL tPLH VOH nY output VM VOL mna237 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Input to output propagation delays VI nOE input GND t PLZ VCC output LOW-to-OFF OFF-to-LOW VOL t PHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled mna949 VM t PZL VM VX t PZH VY VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Enable and disable times 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 8 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state Table 8. Type 74AHC126 Measurement points Input VM 0.5 × VCC 1.5 V Output VM 0.5 × VCC 0.5 × VCC VX VOL + 0.3 V VOL + 0.3 V VY VOH − 0.3 V VOH − 0.3 V 74AHCT126 VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC G VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. S1 = test selection switch. Fig 8. Table 9. Type Test circuitry for measuring switching times Test data Input VI tr, tf ≤ 3.0 ns ≤ 3.0 ns VCC 3.0 V Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 kΩ 1 kΩ S1 position tPHL, tPLH open open tPZH, tPHZ GND GND tPZL, tPLZ VCC VCC 74AHC126 74AHCT126 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 9 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index θ Lp 1 e bp 7 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT108-1 (SO14) 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 10 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Fig 10. Package outline SOT402-1 (TSSOP14) 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 11 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 vMCAB wM C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 11. Package outline SOT762-1 (DHVQFN14) 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 12 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state 13. Abbreviations Table 10. Acronym CDM CMOS DUT ESD HBM LSTTL MM Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model 14. Revision history Table 11. Revision history Release date 20090812 Data sheet status Product data sheet Product data sheet Product specification Preliminary specification Change notice Supersedes 74AHC_AHCT126_3 74AHC_AHCT126_2 74AHC_AHCT126_N_1 Document ID 74AHC_AHCT126_4 Modifications: 74AHC_AHCT126_3 74AHC_AHCT126_2 74AHC_AHCT126_N_1 • Added type numbers 74AHC126BQ and 74AHCT126BQ (DHVQFN14 package) 20080425 19990929 19990112 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 13 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AHC_AHCT126_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 12 August 2009 14 of 15 NXP Semiconductors 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 August 2009 Document identifier: 74AHC_AHCT126_4