74AHC132D,118

74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Rev. 06 — 4 May 2009 Product data sheet 1. General description The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC132; 74AHCT132 contains four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter free output signals. The gate switches at different points for positive-going and negative-going signals. The difference between the positive voltage VT+ and the negative VT− is defined as the hysteresis voltage VH. 2. Features n Balanced propagation delays n Inputs accept voltages higher than VCC n Input levels: u For 74AHC132: CMOS level u For 74AHCT132: TTL level n ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V u CDM EIA/JESD22-C101C exceeds 1000 V n Multiple package options n Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC132D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74AHC132PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74AHC132BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 74AHC132 SOT762-1 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger Table 1. Ordering information …continued Type number Package Temperature range Name Description Version 74AHCT132D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74AHCT132PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74AHCT132BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 74AHCT132 SOT762-1 4. Functional diagram 1 1A 1Y 2 4 2A 2Y 5 3 1B 1 6 2B 4 9 3A 3Y 10 & 3 & 6 & 8 & 11 2 5 8 3B 9 10 12 4A 4Y 13 12 11 13 4B mna407 Fig 1. mna408 Logic symbol Fig 2. IEC logic symbol A Y B mna409 Fig 3. Logic diagram (one Schmitt trigger) 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 2 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 5. Pinning information 5.1 Pinning terminal 1 index area 2 1Y 3 12 4A 2A 4 1 14 VCC 1B 2 13 4B 3 2A 4 11 4Y 2B 5 2B 5 10 3B 2Y 6 2Y 6 9 3A GND 7 8 3Y 132 12 4A 132 GND(1) 11 4Y 10 3B 9 7 1Y 13 4B 3A 8 1B 1A 14 1 1A VCC GND 3Y 001aac439 Transparent top view mna406 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A 1 data input A 1B 2 data input B 1Y 3 data output Y 2A 4 data input A 2B 5 data input B 2Y 6 data output Y GND 7 ground (0 V) 3Y 8 data output Y 3A 9 data input A 3B 10 data input B 4Y 11 data output Y 4A 12 data input A 4B 13 data input B VCC 14 supply voltage 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 3 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 6. Functional description Table 3. Function table[1] Input Output nA nB nY L L H L H H H L H H H L [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI Conditions Min Max Unit supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V −20 - mA −20 +20 mA input clamping current VI < −0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] VO = −0.5 V to (VCC + 0.5 V) IIK IO output current −25 +25 mA ICC supply current - +75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C - 500 mW total power dissipation Ptot Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K. 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 4 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 2.0 5.0 5.5 V 74AHC132 VCC supply voltage VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V VCC = 4.5 V to 5.5 V - - 20 ns/V 74AHCT132 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate - - 20 ns/V VCC = 4.5 V to 5.5 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max HIGH-level VI = VT+ or VT− output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 2.2 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 3.15 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 3.85 4.4 - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V LOW-level VI = VT+ or VT− output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 µA 74AHC132 VOH VOL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 µA CI input capacitance - 3 10 - 10 - 10 pF VI = VCC or GND 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 5 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CO 25 °C Conditions output capacitance −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 4 - - - - - pF 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.80 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 µA 74AHCT132 VOH HIGH-level VI = VT+ or VT−; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA VOL LOW-level VI = VT+ or VT−; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 µA ∆ICC additional per input pin; supply current VI = VCC − 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4 - - - - - pF VI = VCC or GND 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter 25 °C Conditions Min −40 °C to +85 °C −40 °C to +125 °C Unit Typ[1] Max Min Max Min Max 74AHC132 tpd [2] propagation nA, nB to nY; see Figure 6 delay VCC = 3.0 V to 3.6 V CL = 15 pF - 4.4 11.9 1.0 14.0 1.0 15.0 ns CL = 50 pF - 6.2 15.4 1.0 17.5 1.0 19.5 ns CL = 15 pF - 3.3 7.7 1.0 9.0 1.0 10.0 ns CL = 50 pF - 4.7 9.7 1.0 11.0 1.0 12.5 ns - 11 - - - - - pF VCC = 4.5 V to 5.5 V CPD power fi = 1 MHz; VI = GND to VCC dissipation capacitance [3] 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 6 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max - 3.5 7.0 1.0 8.0 1.0 9.0 ns - 5.0 8.0 1.0 9.0 1.0 10.0 ns - 14 - - - - - pF 74AHCT132; VCC = 4.5 V to 5.5 V [2] propagation nA, nB to nY; see Figure 6 delay CL = 15 pF tpd CL = 50 pF power fi = 1 MHz; VI = GND to VCC dissipation capacitance CPD [3] [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 11. Waveforms VI VM nA, nB input GND t PHL t PLH VOH VM nY output VOL 001aaa662 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Input to output propagation delays Table 8. Measurement points Type Input Output VM VM 74AHC132 0.5 × VCC 0.5 × VCC 74AHCT132 1.5 V 0.5 × VCC 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 7 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger VI negative pulse tW 90 % VM VM 10 % GND tr tf tr VI positive pulse GND tf 90 % VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Load circuitry for measuring switching times Table 9. Test data Type Input Load Test VI tr, tf CL 74AHC132 VCC ≤ 3.0 ns 50 pF, 15 pF tPLH, tPHL 74AHCT132 3.0 V ≤ 3.0 ns 50 pF, 15 pF tPLH, tPHL 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 8 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 12. Transfer characteristics Table 10. Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 3.0 V - - 2.2 - 2.2 - 2.2 V VCC = 4.5 V - - 3.15 - 3.15 - 3.15 V VCC = 5.5 V - - 3.85 - 3.85 - 3.85 V 74AHC132 VT+ VT− VH positive-going threshold voltage negative-going threshold voltage hysteresis voltage VCC = 3.0 V 0.9 - - 0.9 - 0.9 - V VCC = 4.5 V 1.35 - - 1.35 - 1.35 - V VCC = 5.5 V 1.65 - - 1.65 - 1.65 - V VCC = 3.0 V 0.3 - 1.2 0.3 1.2 0.25 1.2 V VCC = 4.5 V 0.4 - 1.4 0.4 1.4 0.35 1.4 V VCC = 5.5 V 0.5 - 1.6 0.5 1.6 0.45 1.6 V VCC = 4.5 V - - 1.9 - 1.9 - 1.9 V 74AHCT132 VT+ positive-going threshold voltage VT− negative-going threshold voltage VH hysteresis voltage VCC = 5.5 V - - 2.1 - 2.1 - 2.1 V VCC = 4.5 V 0.5 - - 0.5 - 0.5 - V VCC = 5.5 V 0.6 - - 0.6 - 0.6 - V VCC = 4.5 V 0.3 - 1.4 0.3 1.4 0.3 1.4 V VCC = 5.5 V 0.3 - 1.5 0.3 1.5 0.3 1.5 V 13. Transfer characteristics waveforms VO VT+ VI VT− VI VH VT− Fig 8. VT+ Transfer characteristics VO mna207 mna208 Fig 9. 74AHC_AHCT132_6 Product data sheet VH Definition of VT+, VT− and VH © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 9 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger mna411 1.5 mna412 5 I CC I CC (mA) (mA) 4 1 3 2 0.5 1 0 0 0 1 2 VI (V) 3 1 0 a. VCC = 3.0 V 2 3 4 V (V) 5 I b. VCC = 4.5 V mna413 6 I CC (mA) 4 2 0 0 c. 2 4 VI (V) 6 VCC = 5.5 V Fig 10. Typical 74AHC132 transfer characteristics 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 10 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger mna414 6 mna415 8 I CC I CC (mA) (mA) 6 4 4 2 2 0 0 0 1 2 3 4 V (V) 5 I 0 a. VCC = 4.5 V. 2 4 VI (V) 6 b. VCC = 5.5 V. Fig 11. Typical 74AHCT132 transfer characteristics 14. Application information VCC R VCC A Y B C 001aac440 1 T 1 0.55 × RC For 74AHC132: f = --- ≈ ------------------------- 1 T 1 0.60 × RC For 74AHCT132: f = --- ≈ ------------------------- Fig 12. Relaxation oscillator 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 11 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 15. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT108-1 (SO14) 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 12 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 14. Package outline SOT402-1 (TSSOP14) 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 13 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.18 mm c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 15. Package outline SOT762-1 (DHVQFN14) 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 14 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 16. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 17. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT132_6 20090504 Product data sheet - 74AHC_AHCT132_5 Modifications: • Table 6: the conditions for HIGH-level output voltage and LOW-level output voltage have been changed. 74AHC_AHCT132_5 20080509 Product data sheet - 74AHC_AHCT132_4 74AHC_AHCT132_4 20050207 Product data sheet - 74AHC_AHCT132_3 74AHC_AHCT132_3 20040415 Product specification - 74AHC_AHCT132_2 74AHC_AHCT132_2 19990924 Product specification - 74AHC_AHCT132_1 74AHC_AHCT132_1 19990531 Product specification - - 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 15 of 17 74AHC132; 74AHCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AHC_AHCT132_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 4 May 2009 16 of 17 NXP Semiconductors 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger 20. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Transfer characteristics. . . . . . . . . . . . . . . . . . . 9 Transfer characteristics waveforms. . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 May 2009 Document identifier: 74AHC_AHCT132_6