74AHC1G79GW

74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger Rev. 05 — 2 July 2007 Product data sheet 1. General description 74AHC1G79 and 74AHCT1G79 are high-speed Si-gate CMOS devices. They provide a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. 2. Features I I I I I I Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays SOT353-1 and SOT753 package options ESD protection: N HBM JESD22-A114E: exceeds 2000 V N MM JESD22-A115-A: exceeds 200 V N CDM JESD22-C101C: exceeds 1000 V I Specified from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AHC1G79GW 74AHCT1G79GW 74AHC1G79GV 74AHCT1G79GV −40 °C to +125 °C SC-74A −40 °C to +125 °C TSSOP5 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm plastic surface-mounted package; 5 leads Version SOT353-1 SOT753 Type number NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 4. Marking Table 2. Marking codes Marking AP A79 CP C79 Type number 74AHC1G79GW 74AHC1G79GV 74AHCT1G79GW 74AHCT1G79GV 5. Functional diagram 1 D Q 4 1 4 D CP mna441 2 CP mna440 2 Fig 1. Logic symbol Fig 2. IEC logic symbol CP C C C C D TG C TG C Q C C TG TG C C mna442 Fig 3. Logic diagram 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 2 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 6. Pinning information 6.1 Pinning 74AHC1G79 74AHCT1G79 D CP 1 2 5 VCC GND 3 001aaf091 4 Q Fig 4. Pin configuration 6.2 Pin description Table 3. Symbol D CP GND Q VCC Pin description Pin 1 2 3 4 5 Description data input clock pulse input ground (0 V) data output supply voltage 7. Functional description Table 4. Inputs CP ↑ ↑ L [1] Function table[1] Output D L H X Q+1 L H Q H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; X = don’t care; Q + 1 = state after the next LOW-to-HIGH CP transition. 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 3 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions Min −0.5 −0.5 Max +7.0 +7.0 ±20 ±25 75 +150 250 Unit V V mA mA mA mA mA °C mW VI < −0.5 V VO < −0.5 V or VO > VCC + 0.5 V −0.5 V < VO < VCC + 0.5 V [1] −20 −75 −65 Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For both TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Conditions Min 2.0 0 0 −40 74AHC1G79 Typ 5.0 +25 Max 5.5 5.5 VCC +125 100 20 4.5 0 0 −40 74AHCT1G79 Min Typ 5.0 +25 Max 5.5 5.5 VCC +125 20 V V V °C ns/V ns/V Unit 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter For type 74AHC1G79 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V 1.5 2.1 3.85 0.5 0.9 1.65 1.5 2.1 3.85 0.5 0.9 1.65 1.5 2.1 3.85 0.5 0.9 1.65 V V V V V V Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 4 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH Conditions Min HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V IO = −50 µA; VCC = 3.0 V IO = −50 µA; VCC = 4.5 V IO = −4.0 mA; VCC = 3.0 V IO = −8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V IO = 50 µA; VCC = 3.0 V IO = 50 µA; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V II ICC CI input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 1.9 2.9 4.4 2.58 3.94 25 °C Typ 2.0 3.0 4.5 0 0 0 1.5 Max 0.1 0.1 0.1 0.36 0.36 0.1 1.0 10 −40 °C to +85 °C −40 °C to +125 °C Unit Min 1.9 2.9 4.4 2.48 3.8 Max 0.1 0.1 0.1 0.44 0.44 1.0 10 10 Min 1.9 2.9 4.4 2.40 3.70 Max 0.1 0.1 0.1 0.55 0.55 2.0 40 10 V V V V V V V V V V µA µA pF supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V For type 74AHCT1G79 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 4.4 3.94 - 4.5 0 - 0.1 0.36 0.1 1.0 1.35 4.4 3.8 - 0.1 0.44 1.0 10 1.5 4.4 3.70 - 0.1 0.55 2.0 40 1.5 V V V V µA µA mA VOL II ICC ∆ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; VI = 3.4 V; supply current other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance CI - 1.5 10 - 10 - 10 pF 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 5 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; tr = tf = ≤ 3.0 ns. For test circuit see Figure 6. For waveforms see Figure 5. Symbol Parameter For type 74AHC1G79 tpd propagation delay CP to Q VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tsu th tW fmax CPD set-up time hold time pulse width maximum frequency power per buffer; dissipation CL = 50 pF; f = 1 MHz; capacitance VI = GND to VCC propagation delay CP to Q VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tsu th tW fmax CPD set-up time hold time pulse width maximum frequency power per buffer; dissipation CL = 50 pF; f = 1 MHz; capacitance VI = GND to VCC tpd is the same as tPLH and tPHL. Typical values are measured at VCC = 3.3 V. Typical values are measured at VCC = 5.0 V. CPD is used to determine the dynamic power dissipation PD (µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. [4] [4] [3] [1] [2] Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max 3.0 +2.0 3.0 90 - 4.9 6.9 3.5 5.1 1.0 −1.0 15 8.4 12.0 5.6 8.0 - 1.0 1.0 1.0 1.0 3.0 2.0 3.0 90 - 9.8 14.0 7.0 10.0 - 1.0 1.0 1.0 1.0 4.0 3.0 4.0 70 - 11.5 15.5 8.0 11.0 - ns ns ns ns ns ns ns MHz pF D to CP D to CP clock HIGH or LOW For type 74AHCT1G79 tpd [1] [3] 3.0 +2.0 3.0 90 - 3.5 5.0 1.0 −1.0 16 5.0 8.0 - 1.0 1.0 3.0 2.0 3.0 90 - 6.0 10.0 - 1.0 1.0 4.0 3.0 4.0 70 - 8.0 11.0 - ns ns ns ns ns MHz pF D to CP D to CP clock HIGH or LOW [1] [2] [3] [4] 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 6 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 12. Waveforms VI D input GND th t su 1/fmax VI CP input GND tW t PHL VOH Q output VOL VM mna647 VM th t su VM t PLH Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output. Fig 5. Clock (CP) to output (Q) propagation delay times, clock pulse width, D to set-up times, the CP to D hold times and maximum clock pulse frequency Table 9. Type 74AHC1G79 74AHCT1G79 Measurement points Inputs VI GND to VCC GND to 3.0 V VM 0.5 × VCC 1.5 V Output VM 0.5 × VCC 0.5 × VCC VCC PULSE GENERATOR VI DUT RT CL VO mna101 Test data is given in Table 8. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. Load circuitry for switching times 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 7 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 D E A X c y HE vMA Z 5 4 A2 A1 (A3) θ A 1 e e1 bp 3 wM detail X Lp L 0 1.5 scale 3 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.1 0 A2 1.0 0.8 A3 0.15 bp 0.30 0.15 c 0.25 0.08 D(1) 2.25 1.85 E(1) 1.35 1.15 e 0.65 e1 1.3 HE 2.25 2.0 L 0.425 Lp 0.46 0.21 v 0.3 w 0.1 y 0.1 Z(1) 0.60 0.15 θ 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC MO-203 JEITA SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 7. Package outline SOT353-1 (TSSOP5) 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 8 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger Plastic surface-mounted package; 5 leads SOT753 D B E A X y HE vMA 5 4 Q A A1 c 1 2 3 detail X Lp e bp wM B 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.100 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT753 REFERENCES IEC JEDEC JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Fig 8. Package outline SOT753 (SC-74A) 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 9 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 14. Abbreviations Table 10. Acronym CDM DUT ESD HBM MM TTL Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 11. Revision history Release date 20070702 Data sheet status Product data sheet Change notice Supersedes 74AHC_AHCT1G79_4 Document ID 74AHC_AHCT1G79_5 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Package SOT353 changed to SOT353-1 in Section 3 and Section 13. Figure 5 updated to include waveform definitions for set-up, hold, pulse width and maximum frequency. Quick reference data and Soldering sections removed. Product specification Product specification Product specification Product specification 74AHC_AHCT1G79_3 74AHC_AHCT1G79_2 74AHC_AHCT1G79_1 - 74AHC_AHCT1G79_4 74AHC_AHCT1G79_3 74AHC_AHCT1G79_2 74AHC_AHCT1G79_1 20020606 20020218 20010222 19990518 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 10 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 11 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 July 2007 Document identifier: 74AHC_AHCT1G79_5