74AHC541

74AHC541; 74AHCT541 Octal buffer/line driver; 3-state Rev. 03 — 12 November 2007 Product data sheet 1. General description The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device. The 74AHC541; 74AHCT541 are octal non-inverting buffer/line drivers with 3-state bus compatible outputs. The 3-state outputs are controlled by the output enable inputs OE0 and OE1. A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. 2. Features s s s s s s Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accepts voltages higher than VCC For 74AHC541 only: operates with CMOS input levels For 74AHCT541 only: operates with TTL input levels ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101C exceeds 1000 V s Multiple package options s Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range 74AHC541D 74AHCT541D 74AHC541PW 74AHCT541PW 74AHC541BQ 74AHCT541BQ −40 °C to +125 °C DHVQFN20 −40 °C to +125 °C TSSOP20 −40 °C to +125 °C Name SO20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT163-1 SOT360-1 Type number plastic dual-in-line compatible thermal enhanced SOT764-1 very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state 4. Functional diagram A0 Y0 2 18 3 A1 Y1 17 4 A2 Y2 16 5 A3 Y3 15 6 A4 Y4 14 1 19 & EN 18 17 16 15 14 13 12 11 mna180 7 A5 Y5 13 2 3 8 A6 Y6 12 4 5 9 A7 Y7 11 6 7 OE0 1 19 OE1 mna179 8 9 Fig 1. Logic symbol Fig 2. IEC logic symbol 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 2 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state 5. Pinning information 5.1 Pinning 74AHC541 74AHCT541 OE0 2 3 4 5 6 7 8 9 GND 10 Y7 11 GND(1) 1 terminal 1 index area 20 VCC 19 OE1 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 74AHC541 74AHCT541 OE0 A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 20 VCC 19 OE1 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 11 Y7 001aah038 A0 A1 A2 A3 A4 A5 A6 A7 GND 10 001aah039 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 3. Pin configuration SO20, TSSOP20 Fig 4. Pin configuration DHVQFN20 5.2 Pin description Table 2. Symbol OE0 A[0:7] GND Y[0:7] OE1 VCC Pin description Pin 1 2, 3, 4, 5, 6, 7, 8, 9 10 19 20 Description output enable input (active LOW) data input ground (0 V) output enable input (active LOW) supply voltage 18, 17, 16, 15, 14, 13, 12, 11 data output 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 3 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state 6. Functional description Table 3. Control OE0 L L X H [1] Functional table[1] Input OE1 L L H X An L H X X Output Yn L H Z Z H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation SO20 package TSSOP20 package DHVQFN20 package [1] [2] [3] [4] Conditions Min −0.5 −0.5 Max +7.0 +7.0 ±20 ±25 75 +150 500 500 500 Unit V V mA mA mA mA mA °C mW mW mW VI < −0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) [1] [1] −20 −75 −65 Tamb = −40 °C to +125 °C [2] [3] [4] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 8 mW/K above 70 °C. Ptot derates linearly with 5.5 mW/K above 60 °C. Ptot derates linearly with 4.5 mW/K above 60 °C. 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 4 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Conditions 74AHC541 Min 2.0 0 0 −40 Typ 5.0 +25 Max 5.5 5.5 VCC +125 100 20 74AHCT541 Min 4.5 0 0 −40 Typ 5.0 +25 Max 5.5 5.5 VCC +125 20 V V V °C ns/V ns/V Unit 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter For type 74AHC541 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V IO = −50 µA; VCC = 3.0 V IO = −50 µA; VCC = 4.5 V IO = −4.0 mA; VCC = 3.0 V IO = −8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V IO = 50 µA; VCC = 3.0 V IO = 50 µA; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V IOZ OFF-state VI = VIH or VIL; output current VO = VCC or GND; VCC = 5.5 V input leakage current VI = VCC or GND; VCC = 0 V to 5.5 V 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 2.0 3.0 4.5 0 0 0 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 ±0.25 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.8 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 ±2.5 1.5 2.1 3.85 1.9 2.9 4.4 2.40 3.70 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 ±10.0 V V V V V V V V V V V V V V V V µA Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max II ICC - - 0.1 4.0 - 1.0 40 - 2.0 80 µA µA supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 5 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter CI CO input capacitance output capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V Conditions Min 25 °C Typ 3.0 4.0 Max 10 −40 °C to +85 °C −40 °C to +125 °C Unit Min Max 10 Min Max 10 pF pF For type 74AHCT541 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA OFF-state per input pin; VI = VIH or VIL; output current VCC = 5.5 V; IO = 0 A; VO = VCC or GND; other pins at VCC or GND input leakage current VI = VCC or GND; VCC = 0 V to 5.5 V 4.4 3.94 - 4.5 0 - 0.1 0.36 ±0.25 4.4 3.8 - 0.1 0.44 ±2.5 4.4 3.70 - 0.1 0.55 ±10.0 V V V V µA VOL IOZ II ICC ∆ICC - - 0.1 4.0 1.35 - 1.0 40 1.5 - 2.0 80 1.5 µA µA mA supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; supply current VI = VCC − 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V input capacitance output capacitance CI CO - 3 4.0 10 - - 10 - - 10 - pF pF 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 6 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V. For test circuit see Figure 7. Symbol Parameter For type 74AHC541 tpd propagation delay An to Yn; see Figure 5 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF ten enable time OEn to Yn; see Figure 6 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tdis disable time OEn to Yn; see Figure 6 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power CL = 50 pF; fi = 1 MHz; dissipation VI = GND to VCC capacitance [3] [2] [2] [2] Conditions Min 25 °C Typ[1] Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 5.0 7.0 3.5 5.0 7.0 10.5 5.0 7.0 1.0 1.0 1.0 1.0 8.5 12.0 6.0 8.0 1.0 1.0 1.0 1.0 9.0 13.5 6.5 9.0 ns ns ns ns - 5.5 7.5 3.5 5.0 10.5 14.0 7.2 9.2 1.0 1.0 1.0 1.0 11.0 16.0 8.5 10.5 1.0 1.0 1.0 1.0 13.5 17.5 9.0 11.5 ns ns ns ns - 6.0 9.5 4.5 6.5 10 11.0 15.4 7.5 8.8 - 1.0 1.0 1.0 1.0 - 12.0 17.5 8.0 10.0 - 1.0 1.0 1.0 1.0 - 14.0 19.5 9.5 11.0 - ns ns ns ns pF 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 7 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state Table 7. Dynamic characteristics …continued GND = 0 V. For test circuit see Figure 7. Symbol Parameter For type 74AHCT541 tpd propagation delay An to Yn; see Figure 5 VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF ten enable time OEn to Yn; see Figure 6 VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tdis disable time OEn to Yn; see Figure 6 VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power per buffer; dissipation CL = 50 pF; f = 1 MHz; capacitance VI = GND to VCC [3] [2] [2] Conditions Min 25 °C Typ[1] Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 3.5 5.0 5.5 8.5 1.0 1.0 6.5 9.5 1.0 1.0 7.0 11.0 ns ns - 4.0 5.5 7.0 10.0 1.0 1.0 8.0 12.0 1.0 1.0 9.0 12.5 ns ns - 5.0 7.0 12 7.0 10.0 - 1.0 1.0 - 8.0 12.0 - 1.0 1.0 - 9.0 12.5 - ns ns pF [1] [2] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation PD (µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. [3] 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 8 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state 11. Waveforms VI An input GND t PHL VOH Yn output VOL VM mna901 VM t PLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay input (An) to output (Yn) VI OEn input GND t PLZ VCC output LOW-to-OFF OFF-to-LOW VOL t PHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled mna902 VM t PZL VM VX t PZH VY VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Enable and disable times Table 8. Type 74AHC541 74AHCT541 Measurement points Input VM 0.5VCC 1.5 V Output VM 0.5VCC 0.5VCC VX VOL + 0.3 V VOL + 0.3 V VY VOH − 0.3 V VOH − 0.3 V 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 9 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC PULSE GENERATOR VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor S1 = Test selection switch Fig 7. Load circuitry for switching times Table 9. Type 74AHC541 74AHCT541 Test data Input VI VCC 3.0 V tr, tf 3.0 ns 3.0 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 kΩ 1 kΩ S1 position tPHL, tPLH open open tPZH, tPHZ GND GND tPZL, tPLZ VCC VCC 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 10 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 8. Package outline SOT163-1 (SO20) 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 11 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 10 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT360-1 (TSSOP20) 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 12 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 9 vMCAB wM C y1 C C y 1 Eh 20 10 e 11 19 Dh 0 12 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 10. Package outline SOT764-1 (DHVQFN20) 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 13 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state 13. Abbreviations Table 10. Acronym CDM CMOS DUT ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20071112 Data sheet status Product data sheet Change notice Supersedes 74AHC_AHCT541_2 Document ID 74AHC_AHCT541_3 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN20 package added. Section 8: derating values added for DHVQFN20 package. Section 12: outline drawing added for DHVQFN20 package. Product specification Product specification 74AHC_AHCT541_1 - 74AHC_AHCT541_2 (939775006301) 74AHC_AHCT541_1 (939775004256) 19991124 19980921 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 14 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74AHC_AHCT541_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 12 November 2007 15 of 16 NXP Semiconductors 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 November 2007 Document identifier: 74AHC_AHCT541_3