74AHC595D

74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches; 3-state Rev. 04 — 11 August 2009 Product data sheet 1. General description The 74AHC595; 74AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC595; 74AHCT595 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks. Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. 2. Features I I I I Balanced propagation delays All inputs have Schmitt-trigger action Inputs accept voltages higher than VCC Input levels: N The 74AHC595 operates with CMOS input levels N The 74AHCT595 operates with TTL input levels I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Applications I Serial-to-parallel data conversion I Remote control holding register NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 4. Ordering information Table 1. Ordering information Package Temperature range 74AHC595 74AHC595D 74AHC595PW 74AHC595BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO16 TSSOP16 DHVQFN16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 Name Description Version Type number plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm plastic small outline package; 16 leads; body width 3.9 mm SOT763-1 74AHCT595 74AHCT595D 74AHCT595PW 74AHCT595BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO16 TSSOP16 DHVQFN16 SOT109-1 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT763-1 5. Functional diagram 14 DS 11 SHCP 10 MR 8-STAGE SHIFT REGISTER Q7S 12 STCP 9 8-BIT STORAGE REGISTER 13 OE 3-STATE OUTPUTS Q 0 Q 1 Q 2 Q3 Q4 Q5 Q6 Q 7 15 1 2 3 4 5 6 7 mna554 Fig 1. Functional diagram 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 2 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 13 12 11 12 10 9 15 1 2 3 4 5 6 7 14 1D 11 R C1/ SRG8 SHCP STCP Q 7S Q0 Q1 Q2 14 DS Q3 Q4 Q5 Q6 Q7 MR 10 OE 13 mna552 EN3 C2 2D 3 15 1 2 3 4 5 6 7 9 mna553 Fig 2. Logic symbol Fig 3. IEC logic symbol STAGE 0 DS D FF0 CP SHCP R Q D STAGES 1 TO 6 Q STAGE 7 D FF7 CP R Q Q 7S MR D Q D Q LATCH CP STCP OE LATCH CP mna555 Q0 Q 1 Q2 Q3 Q4 Q5 Q6 Q7 Fig 4. Logic diagram 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 3 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 6. Pinning information 6.1 Pinning 74AHC595 74AHCT595 terminal 1 index area Q2 16 VCC 15 Q0 14 DS 13 OE 12 STCP 11 SHCP 10 MR 9 001aae538 74AHC595 74AHCT595 Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 GND Q7S 9 16 VCC 15 Q0 14 DS 13 OE 12 STCP 11 SHCP 10 MR Q3 Q4 Q5 Q6 Q7 1 Q1 Q7S 001aae483 Transparent top view Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16 6.2 Pin description Table 2. Symbol Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND Q7S MR SHCP STCP OE DS Q0 VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description parallel data output 1 parallel data output 2 parallel data output 3 parallel data output 4 parallel data output 5 parallel data output 6 parallel data output 7 ground (0 V) serial data output master reset (active LOW) shift register clock input storage register clock input output enable input (active LOW) serial data input parallel data output 0 supply voltage 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 4 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 7. Functional description Table 3. Control SHCP STCP OE X X X ↑ X ↑ X X L L H L MR L L L H Function table[1] Input DS X X X H Output Q7S L L L Q6S Qn NC L Z NC a LOW-level on MR only affects the shift registers empty shift register loaded into storage register shift register clear; parallel outputs in high-impedance OFF-state logic HIGH-level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages Function X ↑ ↑ ↑ L L H H X X NC Q6S QnS QnS [1] H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state. SHCP DS STCP MR OE Q0 Q1 Z-state Z-state Q6 Q7 Q7 S Z-state Z-state mna556 Fig 7. Timing diagram 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 5 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions Min −0.5 −0.5 Max +7.0 +7.0 +20 +25 +75 +150 500 Unit V V mA mA mA mA mA °C mW VI < −0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) [1] [1] −20 −20 −25 −75 −65 Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K. 9. Recommended operating conditions Table 5. Symbol 74AHC595 VCC VI VO Tamb ∆t/∆V 74AHCT595 VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 4.5 V to 5.5 V 4.5 0 0 −40 5.0 +25 5.5 5.5 VCC +125 20 V V V °C ns/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 2.0 0 0 −40 5.0 +25 5.5 5.5 VCC +125 100 20 V V V °C ns/V ns/V Operating conditions Parameter Conditions Min Typ Max Unit 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 6 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74AHC595 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V IO = −50 µA; VCC = 3.0 V IO = −50 µA; VCC = 4.5 V IO = −4.0 mA; VCC = 3.0 V IO = −8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V IO = 50 µA; VCC = 3.0 V IO = 50 µA; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V II IOZ ICC CI input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 2.0 3.0 4.5 0 0 0 3 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 0.1 ±0.25 4.0 10 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.80 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 1.0 ±2.5 40 10 1.5 2.1 3.85 1.9 2.9 4.4 2.40 3.70 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 2.0 ±10 80 10 V V V V V V V V V V V V V V V V µA µA µA pF Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max OFF-state VI = VIH or VIL; output current VO = VCC or GND; VCC = 5.5 V supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 74AHCT595 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA 4.4 3.94 - 4.5 0 - 0.1 0.36 4.4 3.80 - 0.1 0.44 4.4 3.70 - 0.1 0.55 V V V V VOL 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 7 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter II IOZ input leakage current Conditions Min VI = 5.5 V or GND; VCC = 0 V to 5.5 V 25 °C Typ Max 0.1 ±0.25 −40 °C to +85 °C −40 °C to +125 °C Unit Min Max 1.0 ±2.5 Min Max 2.0 ±10 µA µA OFF-state VI = VIH or VIL; output current VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; VI = VCC − 2.1 V; supply current other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V input capacitance ICC ∆ICC - - 4.0 1.35 - 40 1.5 - 80 1.5 µA mA CI - 3 10 - 10 - 10 pF 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 8 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter 74AHC595 tpd propagation SHCP to Q7S; see Figure 8 delay VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF STCP to Qn; see Figure 9 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF MR to Q7S; see Figure 11 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF ten enable time OE to Qn; see Figure 12 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tdis disable time OE to Qn; see Figure 12 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF 3.8 5.8 8.0 10.3 1.0 1.0 9.5 11.0 1.0 1.0 10.5 12.0 ns ns 5.4 8.7 11.0 15.7 1.0 1.0 13.0 16.2 1.0 1.0 14.5 17.5 ns ns [5] [4] [3] [2] [2] Conditions Min 25 °C Typ[1] Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 5.7 7.7 4.0 5.4 13.0 16.5 8.2 10.0 1.0 1.0 1.0 1.0 15.0 18.5 9.4 11.4 1.0 1.0 1.0 1.0 16.5 20.1 10.5 12.5 ns ns ns ns - 5.9 7.7 4.2 5.5 11.9 15.4 7.4 9.0 1.0 1.0 1.0 1.0 13.5 17.0 8.5 10.5 1.0 1.0 1.0 1.0 15.0 18.5 9.5 11.5 ns ns ns ns - 5.9 7.4 4.4 5.6 12.8 16.3 8.0 10.0 1.0 1.0 1.0 1.0 13.7 17.2 9.1 11.1 1.0 1.0 1.0 1.0 15.0 18.7 10.0 12.0 ns ns ns ns - 5.6 7.4 4.0 5.3 11.5 15.0 8.6 10.6 1.0 1.0 1.0 1.0 13.5 17.0 10.0 12.0 1.0 1.0 1.0 1.0 15.0 18.5 11.0 13.0 ns ns ns ns 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 9 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter fmax maximum frequency Conditions Min SHCP or STCP; see Figure 8 and 9 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW pulse width SHCP HIGH or LOW; see Figure 8 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V STCP HIGH or LOW; see Figure 9 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V MR LOW; see Figure 11 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tsu set-up time DS to SHCP; see Figure 9 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V SHCP to STCP; see Figure 10 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V th hold time DS to SHCP; see Figure 10 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V trec recovery time MR to SHCP; see Figure 11 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power fi = 1 MHz; VI = GND to VCC dissipation capacitance propagation SHCP to Q7S; see Figure 8 delay CL = 15 pF CL = 50 pF STCP to Qn; see Figure 9 CL = 15 pF CL = 50 pF MR to Q7S; see Figure 11 CL = 15 pF CL = 50 pF 74AHC_AHCT595_4 25 °C Typ[1] Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max 80 130 125 170 - 60 110 - 40 90 - MHz MHz 5.0 5.0 - - 5.0 5.0 - 5.0 5.0 - ns ns 5.0 5.0 5.0 5.0 3.5 3.0 - - 5.0 5.0 5.0 5.0 3.5 3.0 - 5.0 5.0 5.0 5.0 3.5 3.0 - ns ns ns ns ns ns 8.5 5.0 1.5 2.0 3.0 2.5 [6] [7] 180 - 8.5 5.0 1.5 2.0 3.0 2.5 - - 8.5 5.0 1.5 2.0 3.0 2.5 - - ns ns ns ns ns ns pF - 74AHCT595; VCC = 4.5 V to 5.5 V tpd [2] [2] 3.8 5.2 4.0 5.3 4.6 5.8 8.2 10.0 7.4 9.0 8.2 10.5 1.0 1.0 1.0 1.0 1.0 1.0 9.0 11.0 8.5 10.5 9.5 11.5 1.0 1.0 1.0 1.0 1.0 1.0 10.0 12.0 9.5 11.5 10.5 12.5 ns ns ns ns ns ns [3] - © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 10 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter ten Conditions Min enable time OE to Qn; see Figure 12 CL = 15 pF CL = 50 pF tdis disable time OE to Qn; see Figure 12 CL = 15 pF CL = 50 pF fmax tW maximum frequency pulse width SHCP and STCP; see Figure 8 and 9 SHCP HIGH or LOW; see Figure 8 STCP HIGH or LOW; see Figure 9 MR LOW; see Figure 11 tsu set-up time DS to SHCP; see Figure 9 SHCP to STCP; see Figure 10 th trec CPD hold time recovery time DS to SHCP; see Figure 10 MR to SHCP; see Figure 11 [6] [7] [5] [4] 25 °C Typ[1] 4.8 6.2 3.6 5.8 170 190 Max 9.0 11.6 6.9 10.3 - −40 °C to +85 °C −40 °C to +125 °C Unit Min 1.0 1.0 1.0 1.0 110 5.0 5.0 5.0 3.0 5.0 2.0 3.0 Max 11.0 13.0 8.0 11.0 Min 1.0 1.0 1.0 1.0 90 5.0 5.0 5.0 3.0 5.0 2.0 3.0 Max 12.0 14.5 9.0 12.0 ns ns ns ns MHz ns ns ns ns ns ns ns pF 130 5.0 5.0 5.0 3.0 5.0 2.0 3.0 - power fi = 1 MHz; VI = GND to VCC dissipation capacitance Typical values are measured at nominal supply voltage. tpd is the same as tPHL and tPLH. tpd is the same as tPHL only. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [1] [2] [3] [4] [5] [6] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; Σ(CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. All 9 outputs switching. [7] 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 11 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 12. Waveforms 1/fmax VI SHCP input GND tW t PLH VOH Q 7S output VOL mna557 VM t PHL VM Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Shift clock pulse, maximum frequency and input to output propagation delays VI SHCP input GND t su VI STCP input GND tW t PLH VOH Q n output VOL mna558 VM 1/fmax VM t PHL VM Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. Storage clock to output propagation delays 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 12 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches VI SHCP input GND t su th VI DS input GND VM t su th VM VOH Q 7S output VOL mna560 VM Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Data set-up and hold times VI MR input GND tW VI SHCP input GND t PHL VOH Q 7S output VOL VM mna561 VM t rec VM Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. Master reset to output propagation delays 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 13 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches VI OE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VM VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled mna450 VM tPZL VOL + 0.3 V tPZH VOH − 0.3 V VM Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 12. Enable and disable times Table 8. Type 74AHC595 74AHCT595 Measurement points Input VM 0.5VCC 1.5 V Output VM 0.5VCC 0.5VCC 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 14 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC G VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 9. Definitions for test circuit: CL = load capacitance including jig and probe capacitance. RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. S1 = test selection switch. Fig 13. Load circuitry for switching times Table 9. Type 74AHC595 74AHCT595 Test data Input VI VCC 3.0 V tr, tf ≤ 3.0 ns ≤ 3.0 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 kΩ 1 kΩ S1 position tPHL, tPLH open open tPZH, tPHZ GND GND tPZL, tPLZ VCC VCC 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 15 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT109-1 (SO16) 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 16 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 15. Package outline SOT403-1 (TSSOP16) 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 17 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 7 vMCAB wM C y1 C C y 1 Eh 16 8 e 9 15 Dh 10 X 2.5 scale 5 mm 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 16. Package outline SOT763-1 (DHVQFN16) 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 18 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 14. Abbreviations Table 10. Acronym CDM CMOS ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 11. Revision history Release date 20090811 Data sheet status Product data sheet Product data sheet Product data sheet Product specification Change notice Supersedes 74AHC_AHCT595_3 74AHC_AHCT595_2 74AHC_AHCT595_1 Document ID 74AHC_AHCT595_4 Modifications: 74AHC_AHCT595_3 74AHC_AHCT595_2 74AHC_AHCT595_1 • Added type number 74AHCT595BQ (DHVQFN16 package) 20080425 20060323 20000315 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 19 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 20 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 August 2009 Document identifier: 74AHC_AHCT595_4