74AHCT157

74AHC157; 74AHCT157 Quad 2-input multiplexer Rev. 02 — 9 November 2007 Product data sheet 1. General description The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74AHC/AHCT157. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. The 74AHC/AHCT157 is logic implementation of a 4-pole, 2-position switch, where the position of the switch is determine by the logic levels applied to S. The logic equations are: 1Y = E × (1I1 × S + 1I0 × S) 2Y = E × (2I1 × S + 2I0 × S) 3Y = E × (3I1 × S + 3I0 × S) 4Y = E × (4I1 × S + 4I0 × S) The 74AHC/AHCT157 is identical to the 74AHC/AHCT158 but has non-inverting (true) outputs. 2. Features s s s s s s s s Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accepts voltages higher than VCC Multiple input enable for easy expansion Ideal for memory chip select decoding For 74AHC157 only: operates with CMOS input levels For 74AHCT157 only: operates with TTL input levels ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101C exceeds 1000 V NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer s Multiple package options s Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range 74AHC157D 74AHCT157D 74AHC157PW 74AHCT157PW 74AHC157BQ 74AHCT157BQ −40 °C to +125 °C DHVQFN16 −40 °C to +125 °C TSSOP16 −40 °C to +125 °C Name SO16 Description plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT403-1 Type number SOT763-1 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 4. Functional diagram S E 1I1 1Y 1I0 2I1 2Y 2I0 2 3Y 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 3I0 1 15 4I1 4Y 4I0 mna484 3I1 3 5 6 11 10 14 13 S E 1Y 4 2Y 7 3Y 9 4Y 12 mna481 Fig 1. Logic diagram Fig 2. logic symbol 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 2 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer 1 2 3 5 6 11 10 14 13 1I0 1I1 2I0 2Y 2I1 3I0 3I1 4I0 4I1 4Y 12 SELECTOR MULTIPLEXER OUTPUTS 7 1Y 4 15 G1 EN 2 3 1 1 MUX 4 3Y 9 5 6 11 10 14 7 9 S 1 E 15 mna483 13 mna482 12 Fig 3. Logic symbol Fig 4. IEC logic symbol 5. Pinning information 5.1 Pinning terminal 1 index area 1I0 16 VCC 15 E 14 4I0 13 4I1 12 4Y 11 3I0 10 3I1 9 001aah066 74AHC157 74AHCT157 S 1I0 1I1 1Y 2I0 2I1 2Y GND 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 GND 3Y 9 16 VCC 15 E 14 4I0 13 4I1 12 4Y 11 3I0 10 3I1 1I1 1Y 2I0 2I1 2Y GND(1) 1 S 157 3Y 001aac931 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SO16, TSSOP16 Fig 6. Pin configuration DHVQFN16 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 3 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer 5.2 Pin description Table 2. Symbol S 1I0 to 4I0 1I1 to 4I1 1Y to 4Y GND E VCC Pin description Pin 1 2, 5, 11, 14 3, 6, 10, 13 4, 7, 9, 12 8 15 16 Description common data select input data inputs from source 0 data inputs from source 1 multiplexer outputs ground (0 V) enable input (active LOW) supply voltage 6. Functional description Table 3. Input E H L L L L [1] Function table[1] Output S X L L H H nI0 X L H X X nI1 X X X L H nY L L H L H H = HIGH voltage level; L = LOW voltage level; X = don’t care. 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 4 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation SO16 package TSSOP16 package DHVQFN16 package [1] [2] [3] [4] Conditions Min −0.5 −0.5 Max +7.0 +7.0 ±20 ±25 75 +150 500 500 500 Unit V V mA mA mA mA mA °C mW mW mW VI < −0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) [1] [1] −20 −75 −65 Tamb = −40 °C to +125 °C [2] [3] [4] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 8 mW/K above 70 °C. Ptot derates linearly with 5.5 mW/K above 60 °C. Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Conditions Min 2.0 0 0 −40 74AHC157 Typ 5.0 +25 Max 5.5 5.5 VCC +125 100 20 Min 4.5 0 0 −40 74AHCT157 Typ 5.0 +25 Max 5.5 5.5 VCC +125 20 V V V °C ns/V ns/V Unit 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 5 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter For type 74AHC157 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V IO = −50 µA; VCC = 3.0 V IO = −50 µA; VCC = 4.5 V IO = −4.0 mA; VCC = 3.0 V IO = −8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V IO = 50 µA; VCC = 3.0 V IO = 50 µA; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V II ICC CI CO input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 2.0 3.0 4.5 0 0 0 3.0 4.0 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 0.1 4.0 10 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.8 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 1.0 40 10 1.5 2.1 3.85 1.9 2.9 4.4 2.40 3.70 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 2.0 80 10 V V V V V V V V V V V V V V V V µA µA pF pF Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance output capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V For type 74AHCT157 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA 4.4 3.94 - 4.5 0 - 0.1 0.36 4.4 3.8 - 0.1 0.44 4.4 3.70 - 0.1 0.55 V V V V VOL 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 6 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter II ICC ∆ICC input leakage current Conditions Min VI = 5.5 V or GND; VCC = 0 V to 5.5 V 25 °C Typ Max 0.1 4.0 1.35 −40 °C to +85 °C −40 °C to +125 °C Unit Min Max 1.0 40 1.5 Min Max 2.0 80 1.5 µA µA mA supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; supply current VI = VCC − 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V input capacitance output capacitance CI CO - 3 4.0 10 - - 10 - - 10 - pF pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 9. Symbol Parameter Conditions Min For type 74AHC157 tpd propagation nI0, nI1 to nY; see Figure 7 delay VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF S to nY; see Figure 7 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF E to nY; see Figure 8 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF 74AHC_AHCT157_2 25 °C Typ[1] Max −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit [2] [2] 4.4 6.3 3.2 4.6 9.7 13.2 6.4 8.4 1.0 1.0 1.0 1.0 11.5 15.0 7.5 9.5 1.0 1.0 1.0 1.0 12.5 16.5 8.0 10.5 ns ns ns ns [2] 4.8 6.8 3.6 5.2 13.6 17.1 8.6 10.6 1.0 1.0 1.0 1.0 16.0 19.5 10.0 12.0 1.0 1.0 1.0 1.0 17.0 21.5 11.0 13.5 ns ns ns ns - 5.9 8.4 4.2 6.0 13.2 16.7 8.1 10.1 1.0 1.0 1.0 1.0 15.5 19.0 9.5 11.5 1.0 1.0 1.0 1.0 16.5 21.0 10.5 13.0 ns ns ns ns © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 7 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer Table 7. Dynamic characteristics …continued GND = 0 V; For test circuit see Figure 9. Symbol Parameter Conditions Min CPD power CL = 50 pF; fi = 1 MHz; dissipation VI = GND to VCC capacitance 4 outputs switching via S 1 outputs switching via I For type 74AHCT157 tpd propagation nI0, nI1 to nY; see Figure 7 delay VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF S to nY; see Figure 7 VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF E to nY; see Figure 8 VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power CL = 50 pF; fi = 1 MHz; dissipation VI = GND to VCC capacitance 4 outputs switching via S 1 outputs switching via I [1] [2] [3] [3] [2] [2] [3] 25 °C Typ[1] Max −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit - 31 13 - - - - - pF pF - 3.2 4.6 6.4 8.7 1.0 1.0 7.5 9.8 1.0 1.0 8.0 11.0 ns ns - 3.7 5.2 8.6 10.4 1.0 1.0 10.0 12.0 1.0 1.0 11.0 13.0 ns ns - 4.7 6.7 8.1 10.6 1.0 1.0 9.5 12.0 1.0 1.0 10.5 13.5 ns ns - 41 16 - - - - - pF pF Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation PD (µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 8 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer 11. Waveforms VI nI0, nI1, S input GND t PHL VOH nY output VOL VM mna486 VM t PLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Propagation delay input (nI0, nI1, S) to output (nYn) VCC E input GND t PHL VOH nY output VOL VM mna485 VM t PLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Propagation delay input (E) to output (nY) Table 8. Type 74AHC157 74AHCT157 Measurement points Input VM 0.5VCC 1.5 V Output VM 0.5VCC 0.5VCC 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 9 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC PULSE GENERATOR VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor S1 = Test selection switch Fig 9. Load circuitry for switching times Table 9. Type 74AHC157 74AHCT157 Test data Input VI VCC 3.0 V tr, tf 3.0 ns 3.0 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 kΩ 1 kΩ S1 position tPHL, tPLH open open tPZH, tPHZ GND GND tPZL, tPLZ VCC VCC 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 10 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT109-1 (SO16) 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 11 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 11. Package outline SOT403-1 (TSSOP16) 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 12 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 7 vMCAB wM C y1 C C y 1 Eh 16 8 e 9 15 Dh 10 X 2.5 scale 5 mm 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT763-1 (DHVQFN16) 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 13 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer 13. Abbreviations Table 10. Acronym CDM CMOS DUT ESD HBM MM TTL Abbreviations Description Charged-Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20071109 Data sheet status Product data sheet Change notice Supersedes 74AHC_AHCT157_1 Document ID 74AHC_AHCT157_2 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN16 package added. Section 8: derating values added for DHVQFN16 package. Section 12: outline drawing added for DHVQFN16 package. Product specification - 74AHC_AHCT157_1 19990924 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 14 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74AHC_AHCT157_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 9 November 2007 15 of 16 NXP Semiconductors 74AHC157; 74AHCT157 Quad 2-input multiplexer 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 November 2007 Document identifier: 74AHC_AHCT157_2