74AHCT273PW

74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 03 — 13 May 2008 Product data sheet 1. General description The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR input. The device is useful for applications where only the true output is required and the clock and master reset are common to all storage elements. 2. Features I I I I I I Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Ideal buffer for MOS microcontroller or memory Common clock and master reset Related product versions: N 74AHC377; 74AHCT377 for clock enable version N 74AHC373; 74AHCT373 for transparent latch version N 74AHC374; 74AHCT374 for 3-state version Input levels: N For 74AHC273: CMOS level N For 74AHCT273: TTL level ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C I I I I NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AHC273 74AHC273D 74AHC273PW 74AHC273BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO20 TSSOP20 DHVQFN20 plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT163-1 SOT360-1 Description Version Type number plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT163-1 SOT360-1 74AHCT273 74AHCT273D 74AHCT273PW 74AHCT273BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO20 TSSOP20 DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm 4. Functional diagram CP MR 11 3 4 7 8 13 14 17 18 CP D0 D1 D2 D3 D4 D5 D6 D7 MR 1 mna763 11 1 C1 R D0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 D1 D2 D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 1D 2 5 6 9 12 15 16 19 mna764 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Fig 1. Logic symbol Fig 2. IEC logic symbol 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 2 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger D0 D1 D2 D3 D Q D Q D Q D Q CP FF1 RD CP CP FF2 RD CP FF3 RD CP FF4 RD MR Q0 D4 D5 Q1 D6 Q2 D7 Q3 D Q D Q D Q D Q CP FF5 RD CP FF6 RD CP FF7 RD CP FF8 RD Q4 Q5 Q6 Q7 001aae056 Fig 3. Logic diagram 3 4 7 8 13 14 17 18 1 11 D0 D1 D2 D3 D4 D5 D6 D7 MR CP FF1 TO FF8 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 001aae055 Fig 4. Functional diagram 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 3 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger 5. Pinning information 5.1 Pinning 74AHC273 74AHCT273 terminal 1 index area 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 GND(1) 13 D4 12 Q4 GND 10 CP 11 MR 2 3 4 5 6 7 8 9 1 Q0 D0 MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP 001aai066 74AHC273 74AHCT273 D1 Q1 Q2 D2 D3 Q3 GND 10 001aai067 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20 5.2 Pin description Table 2. Symbol MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND CP Q4 D4 D5 Q5 Q6 74AHC_AHCT273_3 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description master reset input (active LOW) flip-flop output data input data input flip-flop output flip-flop output data input data input flip-flop output ground (0 V) clock input (LOW-to-HIGH edge-triggered) flip-flop output data input data input flip-flop output flip-flop output © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 4 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger Table 2. Symbol D6 D7 Q7 VCC Pin description …continued Pin 17 18 19 20 Description data input data input flip-flop output supply voltage 6. Functional description Table 3. Function table[1] Control MR Reset (clear) Load ‘1’ Load ‘0’ [1] Operating mode Input CP X ↑ ↑ Dn X h l Output Qn L H L L H H H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; ↑ = LOW-to-HIGH; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions Min −0.5 −0.5 Max +7.0 +7.0 +20 +25 +75 +150 500 Unit V V mA mA mA mA mA °C mW VI < −0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) [1] [1] −20 −20 −25 −75 −65 Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K. 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 5 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger 8. Recommended operating conditions Table 5. Symbol 74AHC273 VCC VI VO Tamb ∆t/∆V 74AHCT273 VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 4.5 V to 5.5 V 4.5 0 0 −40 5.0 +25 5.5 5.5 VCC +125 20 V V V °C ns/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 2.0 0 0 −40 5.0 +25 5.5 5.5 VCC +125 100 20 V V V °C ns/V ns/V Operating conditions Parameter Conditions Min Typ Max Unit 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74AHC273 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V IO = −50 µA; VCC = 3.0 V IO = −50 µA; VCC = 4.5 V IO = −4.0 mA; VCC = 3.0 V IO = −8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V IO = 50 µA; VCC = 3.0 V IO = 50 µA; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V 74AHC_AHCT273_3 Conditions Min 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 - 25 °C Typ 2.0 3.0 4.5 0 0 0 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 −40 °C to +85 °C −40 °C to +125 °C Unit Min 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.80 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 Min 1.5 2.1 3.85 1.9 2.9 4.4 2.40 3.70 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 V V V V V V V V V V V V V V V V © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 6 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter II ICC CI CO input leakage current Conditions Min VI = 5.5 V or GND; VCC = 0 V to 5.5 V 25 °C Typ 3 4 Max 0.1 4.0 10 −40 °C to +85 °C −40 °C to +125 °C Unit Min Max 1.0 40 10 Min Max 2.0 80 10 µA µA pF pF supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance output capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 74AHCT273 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 4.4 3.94 - 0 - 0.1 0.36 0.1 4.0 1.35 4.4 3.80 - 0.1 0.44 1.0 40 1.5 4.4 3.70 - 0.1 0.55 2.0 80 1.5 V V V V µA µA mA VOL II ICC ∆ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; supply current VI = VCC − 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V input capacitance output capacitance CI CO - 3 4 10 - - 10 - - 10 - pF pF 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 7 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter 74AHC273 tpd propagation CP to Qn; see Figure 7 delay VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF MR to Qn; see Figure 8 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF fmax maximum frequency see Figure 7 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tW pulse width CP HIGH or LOW; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V MR LOW; see Figure 8 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tsu set-up time Dn to CP; see Figure 9 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V th hold time Dn to CP; see Figure 9 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 1.0 1.0 1.0 1.0 1.0 1.0 ns ns 3.0 3.0 3.0 3.0 3.0 3.0 ns ns 5.0 5.0 6.0 5.0 6.0 5.0 ns ns 5.0 5.0 6.5 5.0 6.5 5.0 ns ns 120 80 165 110 100 70 100 70 MHz MHz 75 50 120 75 65 45 65 45 MHz MHz 3.7 5.3 8.5 10.5 1.0 1.0 10.0 12.0 1.0 1.0 11.0 13.5 ns ns 5.1 7.3 13.6 17.1 1.0 1.0 16.0 19.5 1.0 1.0 17.0 21.5 ns ns [3] [2] Conditions Min 25 °C Typ[1] Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 6.0 8.6 4.2 6.0 13.6 17.1 9 11.0 1.0 1.0 1.0 1.0 16.0 19.5 10.5 12.5 1.0 1.0 1.0 1.0 17.0 21.5 11.5 14.0 ns ns ns ns 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 8 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter trec recovery time Conditions Min MR to CP; see Figure 8 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD fi = 1 MHz; VI = GND to VCC power dissipation capacitance propagation CP to Qn; see Figure 7 delay CL = 15 pF CL = 50 pF MR to Qn; see Figure 8 CL = 15 pF CL = 50 pF fmax maximum frequency see Figure 7 CL = 15 pF CL = 50 pF tW pulse width CP HIGH or LOW; see Figure 7 MR LOW; see Figure 8 tsu th trec CPD set-up time hold time recovery time Dn to CP; see Figure 9 Dn to CP; see Figure 9 MR to CP; see Figure 8 [4] [3] [4] 25 °C Typ[1] 14 Max - −40 °C to +85 °C −40 °C to +125 °C Unit Min 2.5 2.0 Max Min 2.5 2.0 Max ns ns pF 2.5 2.0 - 74AHCT273; VCC = 4.5 V to 5.5 V tpd [2] 75 50 5.0 5.0 3.0 1.0 2.5 - 4.0 5.8 3.9 5.6 120 75 18 7.5 9.2 10.0 11.0 - 1.0 1.0 1.0 1.0 65 45 6.5 6.0 3.0 1.0 2.5 - 8.8 10.5 11.6 12.6 - 1.0 1.0 1.0 1.0 65 45 6.5 6.0 3.0 1.0 2.5 - 9.5 11.5 12.5 14.0 - ns ns ns ns MHz MHz ns ns ns ns ns pF power fi = 1 MHz; VI = GND to VCC dissipation capacitance [1] [2] [3] [4] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. tpd is the same as tPHL only. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 9 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger 11. Waveforms 1/fmax VI CP input GND tW t PHL VOH Qn output VOL VM 001aac426 VM t PLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Clock pulse width, maximum frequency and input to output propagation delays VI MR input GND VM tW VI CP input GND trec VM tPHL VOH Qn output VOL mna464 VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Master reset pulse width, recovery time and propagation delay 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 10 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger VI CP input GND tsu th VI Dn input GND VM tsu th VM VOH Qn output VOL mna202 VM Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Table 8. Type Data set-up and hold times Measurement points Input VM 0.5 × VCC 1.5 V Output VM 0.5 × VCC 0.5 × VCC 74AHC273 74AHCT273 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 11 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger VI negative pulse GND tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VCC G VI VO VM VI positive pulse GND VM DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 10. Load circuitry for measuring switching times Table 9. Type 74AHC273 74AHCT273 Test data Input VI VCC 3.0 V tr, tf ≤ 3.0 ns ≤ 3.0 ns Load CL 15 pF, 50 pF 15 pF, 50 pF tPLH, tPHL tPLH, tPHL Test 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 12 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT163-1 (SO20) 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 13 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 10 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT360-1 (TSSOP20) 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 14 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 9 vMCAB wM C y1 C C y 1 Eh 20 10 e 11 19 Dh 0 12 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT764-1 (DHVQFN20) 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 15 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger 13. Abbreviations Table 10. Acronym CDM CMOS DUT ESD HBM LSTTL MM MOS Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Metal-Oxide Semiconductor 14. Revision history Table 11. Revision history Release date 20080513 Data sheet status Product data sheet Change notice Supersedes 74AHC_AHCT273_2 Document ID 74AHC_AHCT273_3 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 6: the conditions for input leakage current have been changed. Product specification Product specification 74AHC_AHCT273_1 - 74AHC_AHCT273_2 74AHC_AHCT273_1 20030721 19990901 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 16 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 13 May 2008 17 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 May 2008 Document identifier: 74AHC_AHCT273_3