74AHCT2G32GD,125

74AHC2G32; 74AHCT2G32 Dual 2-input OR gate Rev. 3 — 14 May 2013 Product data sheet 1. General description The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device. The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates. 2. Features and benefits  Symmetrical output impedance  High noise immunity  ESD protection:  HBM JESD22-A114E exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101C exceeds 1000 V  Low power dissipation  Balanced propagation delays  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number 74AHC2G32DP Package Temperature range Name Description 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body SOT505-2 width 3 mm; lead length 0.5 mm 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; body 3  2  0.5 mm 74AHCT2G32DP 74AHC2G32DC 74AHCT2G32DC 74AHC2G32GD 74AHCT2G32GD Version 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 4. Marking Table 2. Marking Type number Marking code[1] 74AHC2G32DP A32 74AHCT2G32DP C32 74AHC2G32DC A32 74AHCT2G32DC C32 74AHC2G32GD A32 74AHCT2G32GD C32 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1 1A 2 1B 5 2A ≥1 7 ≥1 3 2 1Y 7 2Y 3 B 6 2B 5 Y 6 A Fig 1. mna166 mna734 mna733 Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74AHC2G32 74AHCT2G32 74AHC2G32 74AHCT2G32 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aaj505 Transparent top view 001aaj504 Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74AHC_AHCT2G32 Product data sheet Fig 5. Pin configuration SOT996-2 (XSON8) All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 © NXP B.V. 2013. All rights reserved. 2 of 14 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 6.2 Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output VCC 8 supply voltage 7. Functional description Table 4. Function table[1] Input Output nA nB nY L L L L H H H L H H H H [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage IIK Conditions input clamping current VI < 0.5 V [1] [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V IO output current 0.5 V < VO < VCC + 0.5 V ICC Min Max Unit 0.5 +7.0 V 0.5 +7.0 V 20 - mA - 20 mA - 25 mA supply current - 75 mA IGND ground current 75 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 250 mW [1] [2] Tamb = 40 C to +125 C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K. For XSON8 package: above 45 C the value of Ptot derates linearly with 2.4 mW/K. 74AHC_AHCT2G32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 © NXP B.V. 2013. All rights reserved. 3 of 14 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC2G32 Min Typ 74AHCT2G32 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V VI input voltage 0 - 5.5 0 - 5.5 V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 3.3 V  0.3 V - - 100 - - - ns/V VCC = 5.0 V  0.5 V - - 20 - - 20 ns/V 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 74AHC2G32 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 50 A; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = 50 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = 8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 A; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 A II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.0 - 10 - 40 A CI input capacitance - 1.5 10 - 10 - 10 pF 74AHC_AHCT2G32 Product data sheet VI = 5.5 V or GND; VCC = 0 V to 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 © NXP B.V. 2013. All rights reserved. 4 of 14 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 74AHCT2G32 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.8 - 3.70 - V IO = 8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A IO = 8.0 mA VI = 5.5 V or GND; VCC = 0 V to 5.5 V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 A II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.0 - 10 - 40 A ICC additional per input pin; VI = 3.4 V; supply current other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 1.5 10 - 10 - 10 pF 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 7. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max CL = 15 pF - 4.4 7.9 1.0 9.5 1.0 10.0 ns CL = 50 pF - 6.3 11.4 1.0 13.0 1.0 14.5 ns - 3.2 5.5 1.0 6.5 1.0 7.0 ns - 4.6 7.5 1.0 8.5 1.0 9.5 ns - 16 - - - - - pF 74AHC2G32 tpd propagation delay nA, nB to nY; see Figure 6 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V [1] [2] [3] CL = 15 pF CL = 50 pF CPD power dissipation capacitance 74AHC_AHCT2G32 Product data sheet per buffer; CL = 50 pF; fi = 1 MHz; VI = GND to VCC [4] All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 © NXP B.V. 2013. All rights reserved. 5 of 14 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate Table 8. Dynamic characteristics …continued GND = 0 V; for test circuit see Figure 7. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 3.3 6.9 1.0 8.0 1.0 9.0 ns - 4.8 7.9 1.0 9.0 1.0 10.0 ns - 17 - - - - - pF 74AHCT2G32 propagation delay tpd nA, nB to nY; see Figure 6 [1] [3] VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF power dissipation capacitance CPD [4] per buffer; CL = 50 pF; fi = 1 MHz; VI = GND to VCC [1] tpd is the same as tPLH and tPHL. [2] Typical values are measured at VCC = 3.3 V. [3] Typical values are measured at VCC = 5.0 V. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of the outputs. 12. Waveforms VI VM nA, nB input GND t PHL t PLH VOH VM nY output VOL Fig 6. mna224 The input (nA and nB) to output (nY) propagation delays. Table 9. Measurement points Type Input Output VM VM 74AHC2G32 0.5VCC 0.5VCC 74AHCT2G32 1.5 V 0.5VCC 74AHC_AHCT2G32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 © NXP B.V. 2013. All rights reserved. 6 of 14 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 7. Test circuit for measuring switching times Table 10. Test data Type Input VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74AHC2G32 VCC  3 ns 15 pF, 50 pF 1 k open GND VCC 74AHCT2G32 3V  3 ns 15 pF, 50 pF 1 k open GND VCC 74AHC_AHCT2G32 Product data sheet Load S1 position All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 © NXP B.V. 2013. All rights reserved. 7 of 14 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 Fig 8. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Package outline SOT505-2 (TSSOP8) 74AHC_AHCT2G32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 © NXP B.V. 2013. All rights reserved. 8 of 14 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 Fig 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Package outline SOT765-1 (VSSOP8) 74AHC_AHCT2G32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 © NXP B.V. 2013. All rights reserved. 9 of 14 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm B D SOT996-2 A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y y1 C L2 L X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A A1 b 0.05 0.35 D E 2.1 3.1 0.5 0.00 0.15 1.9 e e1 0.5 1.5 2.9 L L1 L2 0.5 0.15 0.6 0.3 0.05 0.4 v 0.1 w y 0.05 0.05 y1 0.1 sot996-2_po Outline version References IEC JEDEC JEITA European projection Issue date 07-12-21 12-11-20 SOT996-2 Fig 10. Package outline SOT996-2 (XSON8) 74AHC_AHCT2G32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 © NXP B.V. 2013. All rights reserved. 10 of 14 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT2G32 v.3 20130514 Product data sheet - 74AHC_AHCT2G32 v.2 Modifications: 74AHC_AHCT2G32 v.2 Modifications: 74AHC_AHCT2G32 v.1 74AHC_AHCT2G32 Product data sheet • For type number 74AHC2G32GD and 74AHCT2G32GD XSON8U has changed to XSON8. 20090120 Product data sheet - 74AHC_AHCT2G32 v.1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Added type number 74AHC2G32GD and 74AHCT2G32GD (XSON8U package). 20040223 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 - © NXP B.V. 2013. All rights reserved. 11 of 14 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74AHC_AHCT2G32 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 © NXP B.V. 2013. All rights reserved. 12 of 14 74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AHC_AHCT2G32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 14 May 2013 © NXP B.V. 2013. All rights reserved. 13 of 14 NXP Semiconductors 74AHC2G32; 74AHCT2G32 Dual 2-input OR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 May 2013 Document identifier: 74AHC_AHCT2G32