74AVC2T45GT

74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 04 — 5 May 2009 Product data sheet 1. General description The 74AVC2T45 is a dual-bit, dual-supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual-supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In Suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state. 2. Features I Wide supply voltage range: N VCC(A): 0.8 V to 3.6 V N VCC(B): 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E Class 3B exceeds 8000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Maximum data rates: N 500 Mbit/s (1.8 V to 3.3 V translation) N 320 Mbit/s (< 1.8 V to 3.3 V translation) N 320 Mbit/s (translate to 2.5 V or 1.8 V) N 280 Mbit/s (translate to 1.5 V) N 240 Mbit/s (translate to 1.2 V) I Suspend mode I Latch-up performance exceeds 100 mA per JESD 78 Class II NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state I I I I I Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AVC2T45DP 74AVC2T45DC 74AVC2T45GT 74AVC2T45GD −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C TSSOP8 VSSOP8 XSON8 XSON8U Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm 4. Marking Table 2. Marking Marking code[1] B45 B45 B45 B45 Type number 74AVC2T45DP 74AVC2T45DC 74AVC2T45GT 74AVC2T45GD [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 2 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 5. Functional diagram DIR 5 DIR 1A 2 1A 7 1B 1B 2A 3 2A 6 VCC(A) VCC(B) VCC(A) 001aag577 2B 2B VCC(B) 001aag578 Fig 1. Logic symbol Fig 2. Logic diagram 6. Pinning information 6.1 Pinning 74AVC2T45 VCC(A) 1A 2A GND 1 2 3 4 001aag579 8 7 6 5 VCC(B) 1B 2B DIR Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74AVC2T45 VCC(A) 1 8 VCC(B) 74AVC2T45 VCC(A) 1A 1 2 3 4 8 7 6 5 VCC(B) 1B 2B DIR 1A 2 7 1B 2A 3 6 2B 2A GND 4 5 DIR GND 001aag580 001aai261 Transparent top view Transparent top view Fig 4. Pin configuration SOT833-1 (XSON8) Fig 5. Pin configuration SOT996-2 (XSON8U) 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 3 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 6.2 Pin description Table 3. Symbol VCC(A) 1A 2A GND DIR 2B 1B VCC(B) Pin description Pin 1 2 3 4 5 6 7 8 Description supply voltage A (referenced to pins 1A, 2A and DIR) data input or output data input or output ground (0 V) direction control data input or output data input or output supply voltage B (referenced to pins 1B and 2B) 7. Functional description Table 4. Function table[1] Input DIR[3] L H X Input/output[2] nA nA = nB input Z nB input nB = nA Z Supply voltage VCC(A), VCC(B) 0.8 V to 3.6 V 0.8 V to 3.6 V GND[4] [1] [2] [3] [4] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. The input circuit of the data I/O is always active. The DIR input circuit is referenced to VCC(A). If at least one of VCC(A) or VCC(B) is at GND level, the device goes into Suspend mode. 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 4 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC(A) VCC(B) IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] [3] [4] Parameter supply voltage A supply voltage B input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions Min −0.5 −0.5 Max +4.6 +4.6 +4.6 VCCO + 0.5 +4.6 ±50 100 +150 250 Unit V V mA V mA V V mA mA mA °C mW VI < 0 V [1] −50 −0.5 −50 [1][2][3] [1] VO < 0 V Active mode Suspend or 3-state mode VO = 0 V to VCCO ICC(A) or ICC(B) −0.5 −0.5 −100 −65 Tamb = −40 °C to +125 °C [4] - The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output port. VCCO + 0.5 V should not exceed 4.6 V. For TSSOP8 package: above 55 °C the value of Ptot derates linearly at 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8 and XSON8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC(A) VCC(B) VI VO Tamb ∆t/∆V [1] [2] Recommended operating conditions Parameter supply voltage A supply voltage B input voltage output voltage ambient temperature input transition rise and fall rate VCCI = 0.8 V to 3.6 V [2] Conditions Min 0.8 0.8 0 Max 3.6 3.6 3.6 VCCO 3.6 +125 5 Unit V V V V V °C ns/V Active mode Suspend or 3-state mode [1] 0 0 −40 - VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the input port. 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 5 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Symbol Parameter Tamb = 25 °C VOH VOL II IOZ IOFF HIGH-level output voltage LOW-level output voltage input leakage current OFF-state output current power-off leakage current VI = VIH IO = −1.5 mA; VCC(A) = VCC(B) = 0.8 V VI = VIL IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V DIR input; VI = GND to VCC(A); VCC(A) = VCC(B) = 0.8 V to 3.6 V A or B port; VO = GND or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V CI CI/O input capacitance input/output capacitance DIR input; VI = GND or 3.3 V; VCC(A) = VCC(B) = 3.3 V A and B port; Suspend mode; VO = VCCO or GND; VCC(A) = VCC(B) = 3.3 V data input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V DIR input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V VIL LOW-level input voltage data input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V DIR input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V 74AVC2T45_4 Conditions Min Typ Max Unit [1] 0.69 0.07 ±0.025 ±0.5 ±0.1 ±0.1 1.0 4.0 ±0.25 ±2.5 ±1.0 ±1.0 - V V µA µA µA µA pF pF - [1] - Tamb = −40 °C to +85 °C VIH HIGH-level input voltage [2] 0.7VCCI 0.65VCCI 1.6 2.0 [2] - 0.3VCCI 0.35VCCI 0.7 0.9 0.3VCC(A) 0.35VCC(A) 0.7 0.9 V V V V V V V V V V V V V V V V 0.7VCC(A) 0.65VCC(A) 1.6 2.0 [2] [2] - © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 6 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Symbol Parameter VOH HIGH-level output voltage Conditions VI = VIH IO = −100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = −3 mA; VCC(A) = VCC(B) = 1.1 V IO = −6 mA; VCC(A) = VCC(B) = 1.4 V IO = −8 mA; VCC(A) = VCC(B) = 1.65 V IO = −9 mA; VCC(A) = VCC(B) = 2.3 V IO = −12 mA; VCC(A) = VCC(B) = 3.0 V VOL LOW-level output voltage VI = VIL IO = 100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V II IOZ IOFF input leakage current OFF-state output current power-off leakage current DIR input; VI = GND to VCC(A); VCC(A) = VCC(B) = 0.8 V to 3.6 V A or B port; VO = GND or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V ICC supply current A port; VI = GND or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V B port; VI = GND or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = GND or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V [2] [2] [2] [1] [1] Min VCCO − 0.1 0.85 1.05 1.2 1.75 2.3 - Typ - Max 0.1 0.25 0.35 0.45 0.55 0.7 ±1.0 ±5.0 ±5.0 ±5.0 Unit V V V V V V V V V V V V µA µA µA µA −2 −2 - 0 0 - 8.0 8.0 8.0 8.0 16 µA µA µA µA µA µA µA 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 7 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Symbol Parameter Tamb = −40 °C to +125 °C VIH HIGH-level input voltage data input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V DIR input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V VIL LOW-level input voltage data input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V DIR input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V VOH HIGH-level output voltage VI = VIH IO = −100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = −3 mA; VCC(A) = VCC(B) = 1.1 V IO = −6 mA; VCC(A) = VCC(B) = 1.4 V IO = −8 mA; VCC(A) = VCC(B) = 1.65 V IO = −9 mA; VCC(A) = VCC(B) = 2.3 V IO = −12 mA; VCC(A) = VCC(B) = 3.0 V VOL LOW-level output voltage VI = VIL IO = 100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V II input leakage current DIR input; VI = GND to VCC(A); VCC(A) = VCC(B) = 0.8 V to 3.6 V 0.1 0.25 0.35 0.45 0.55 0.7 ±1.5 V V V V V V µA [1] [2] [2] [2] [2] Conditions Min Typ Max Unit 0.7VCCI 0.65VCCI 1.6 2.0 0.7VCC(A) 0.65VCC(A) 1.6 2.0 VCCO − 0.1 0.85 1.05 1.2 1.75 2.3 - 0.3VCCI 0.35VCCI 0.7 0.9 0.3VCC(A) 0.35VCC(A) 0.7 0.9 - V V V V V V V V V V V V V V V V V V V V V V 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 8 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Symbol Parameter IOZ IOFF OFF-state output current power-off leakage current Conditions A or B port; VO = GND or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V A port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V ICC supply current A port; VI = GND or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V B port; VI = GND or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = GND or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V [1] [2] VCCO is the supply voltage associated with the data output port. VCCI is the supply voltage associated with the input port. [2] [2] [2] [1] Min - Typ - Max ±7.5 ±35 ±35 Unit µA µA µA −8 −8 - 0 0 - 11.5 11.5 11.5 11.5 23 µA µA µA µA µA µA µA 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 9 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min VCC(A) = 0.8 V tpd propagation delay A to B; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V B to A; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [3] [3] [2] [2] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) Unit - 15.5 8.1 7.6 7.7 8.4 9.2 15.5 12.7 12.3 12.2 12.0 11.8 12.2 12.2 12.2 12.2 12.2 12.2 11.7 7.9 7.6 8.2 8.7 10.2 - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 10 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min ten enable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [4][5] [4][5] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) - Unit - 27.2 20.6 19.9 20.4 20.7 22.0 27.7 20.3 19.8 19.9 20.6 21.4 - - ns ns ns ns ns ns ns ns ns ns ns ns 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 11 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min VCC(A) = 1.1 V to 1.3 V tpd propagation delay A to B; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V B to A; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [3] [3] [2] [2] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) Unit - 12.7 8.1 4.9 9.2 - - 1.0 0.7 0.6 0.5 0.5 1.0 0.8 0.7 0.6 0.5 2.2 2.2 1.8 2.0 1.7 2.4 9.0 6.8 6.1 5.7 6.1 9.0 8.0 7.7 7.2 7.1 8.8 8.4 6.7 6.9 6.2 7.2 9.9 7.5 6.8 6.3 6.8 9.9 8.8 8.5 8.0 7.9 9.7 9.2 7.4 7.6 6.9 8.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 12 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min ten enable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V VCC(A) = 1.4 V to 1.6 V tpd propagation delay A to B; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V B to A; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [2] [2] [4][5] [4][5] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) 17.4 14.7 14.6 13.4 14.3 17.8 15.6 14.9 14.5 14.9 Max (125 °C) 19.1 16.2 16.1 14.9 15.9 19.6 17.2 16.5 16.0 16.5 Unit - 17.3 17.6 - - - ns ns ns ns ns ns ns ns ns ns ns ns - 12.3 7.6 - - 1.0 0.7 0.6 0.5 0.5 1.0 0.8 0.7 0.6 0.5 8.0 5.4 4.6 3.7 3.5 6.8 5.4 5.1 4.7 4.5 8.8 6.0 5.1 4.1 3.9 7.5 6.0 5.7 5.2 5.0 ns ns ns ns ns ns ns ns ns ns ns ns 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 13 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min tdis disable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V ten enable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [4][5] [4][5] [3] [3] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) 6.3 7.6 5.9 6.0 4.8 5.5 14.4 11.3 11.1 9.5 10.0 14.3 11.7 10.9 10.0 9.8 Max (125 °C) 7.0 8.3 6.5 6.6 5.3 6.1 15.8 12.5 12.3 10.5 11.1 15.8 13.0 12.1 11.1 10.9 Unit - 3.8 9.0 16.6 16.1 - - 1.6 2.0 1.8 1.6 1.2 1.7 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 14 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min VCC(A) = 1.65 V to 1.95 V tpd propagation delay A to B; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V B to A; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [3] [3] [2] [2] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) Unit - 12.2 7.7 3.7 8.8 - - 1.0 0.6 0.5 0.5 0.5 1.0 0.7 0.5 0.5 0.5 1.6 1.8 1.8 1.4 1.0 1.5 7.7 5.1 4.3 3.4 3.1 6.1 4.6 4.4 3.9 3.7 5.5 7.7 5.7 5.8 4.5 5.2 8.5 5.7 4.8 3.8 3.5 6.8 5.1 4.9 4.3 4.1 6.1 8.5 6.3 6.4 5.0 5.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 15 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min ten enable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V VCC(A) = 2.3 V to 2.7 V tpd propagation delay A to B; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V B to A; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [2] [2] [4][5] [4][5] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) 13.8 10.3 10.2 8.4 8.9 13.2 10.6 9.8 8.9 8.6 Max (125 °C) 15.3 11.4 11.3 9.3 9.9 14.6 11.8 10.9 9.9 9.6 Unit - 16.5 15.9 - - - ns ns ns ns ns ns ns ns ns ns ns ns - 12.0 8.4 - - 1.0 0.5 0.5 0.5 0.5 1.0 0.6 0.5 0.5 0.5 7.2 4.7 3.9 3.0 2.6 5.7 3.8 3.4 3.0 2.8 8.0 5.2 4.3 3.3 2.9 6.3 4.2 3.8 3.3 3.1 ns ns ns ns ns ns ns ns ns ns ns ns 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 16 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min tdis disable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V ten enable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [4][5] [4][5] [3] [3] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) 4.2 7.3 5.2 5.1 4.2 4.8 13.0 9.0 8.5 7.2 7.6 11.4 8.9 8.1 7.2 6.8 Max (125 °C) 4.7 8.0 5.8 5.7 4.7 5.3 14.3 10.0 9.5 8.0 8.4 12.7 9.9 9.0 8.0 7.6 Unit - 2.8 8.7 17.1 14.8 - - 1.5 1.7 2.0 1.5 0.6 1.1 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 17 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min VCC(A) = 3.0 V to 3.6 V tpd propagation delay A to B; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V B to A; see Figure 6 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [3] [3] [2] [2] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) Unit - 11.8 9.2 3.4 8.6 - - 1.0 0.5 0.5 0.5 0.5 1.0 0.6 0.5 0.5 0.5 1.5 1.7 0.7 0.6 0.7 1.7 7.1 4.5 3.7 2.8 2.4 6.1 3.6 3.1 2.6 2.4 4.7 7.2 5.5 5.5 4.1 4.7 7.9 5.0 4.1 3.1 2.7 6.8 4.0 3.5 2.9 2.7 5.2 7.9 6.1 6.1 4.6 5.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 18 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min ten enable time DIR to A; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 VCC(B) = 0.8 V VCC(B) = 1.1 V to 1.3 V VCC(B) = 1.4 V to 1.6 V VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V VCC(B) = 3.0 V to 3.6 V [4][5] [4][5] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) 13.3 9.1 8.6 6.7 7.1 11.8 9.2 8.4 7.5 7.1 Max (125 °C) 14.7 10.1 9.6 7.5 7.9 13.1 10.2 9.3 8.3 7.9 Unit - 17.8 15.2 - - - ns ns ns ns ns ns ns ns ns ns ns ns 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 19 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min Power dissipation capacitance CPD power dissipation capacitance A port: (direction A to B); B port: (direction B to A) VCC(A) = VCC(B) = 0.8 V VCC(A) = VCC(B) = 1.2 V VCC(A) = VCC(B) = 1.5 V VCC(A) = VCC(B) = 1.8 V VCC(A) = VCC(B) = 2.5 V VCC(A) = VCC(B) = 3.3 V A port: (direction B to A); B port: (direction A to B) VCC(A) = VCC(B) = 0.8 V VCC(A) = VCC(B) = 1.2 V VCC(A) = VCC(B) = 1.5 V VCC(A) = VCC(B) = 1.8 V VCC(A) = VCC(B) = 2.5 V VCC(A) = VCC(B) = 3.3 V [1] [2] [3] [4] [5] [6] All typical values are measured at nominal VCC(A) and VCC(B). tpd is the same as tPLH and tPHL. tdis is the same as tPLZ and tPHZ. ten is the same as tPZL and tPZH. The enable time is a calculated value using the formula shown in Section 13.4 “Enable times”. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. [6][7] [6][7] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) Unit - 1 2 2 2 2 2 - - - - pF pF pF pF pF pF - 9 11 11 12 14 17 - - - - pF pF pF pF pF pF [7] 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 20 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 12. Waveforms VI nA, nB input GND tPHL VOH nB, nA output VOL VM 001aak114 VM tPLH Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. The data input (nA, nB) to output (nB, nA) propagation delay times VI DIR input GND t PLZ output LOW-to-OFF OFF-to-LOW VCCO VM VOL t PHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aae968 VM t PZL VX t PZH VY VM Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Table 9. Enable and disable times Measurement points Input[1] VM 0.5VCCI 0.5VCCI 0.5VCCI Output[2] VM 0.5VCCO 0.5VCCO 0.5VCCO VX VOL + 0.1 V VOL + 0.15 V VOL + 0.3 V VY VOH − 0.1 V VOH − 0.15 V VOH − 0.3 V Supply voltage VCC(A), VCC(B) 1.1 V to 1.6 V 1.65 V to 2.7 V 3.0 V to 3.6 V [1] [2] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 21 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aae331 Test data is given in Table 10. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 8. Table 10. Load circuitry for switching times Test data Input VI[1] VCCI VCCI VCCI ∆t/∆V[2] ≤ 1.0 ns/V ≤ 1.0 ns/V ≤ 1.0 ns/V Load CL 15 pF 15 pF 15 pF RL 2 kΩ 2 kΩ 2 kΩ VEXT tPLH, tPHL open open open tPZH, tPHZ GND GND GND tPZL, tPLZ[3] 2VCCO 2VCCO 2VCCO Supply voltage VCC(A), VCC(B) 1.1 V to 1.6 V 1.65 V to 2.7 V 3.0 V to 3.6 V [1] [2] [3] VCCI is the supply voltage associated with the data input port. dV/dt ≥ 1.0 V/ns VCCO is the supply voltage associated with the output port. 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 22 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 13. Application information 13.1 Unidirectional logic level-shifting application The circuit given in Figure 9 is an example of the 74AVC2T45 being used in an unidirectional logic level-shifting application. VCC1 VCC1 VCC(A) 1A 2A GND VCC1 74AVC2T45 1 2 3 4 8 7 6 5 VCC(B) 1B 2B DIR VCC2 VCC2 VCC2 system-1 system-2 001aag581 Fig 9. Table 11. Pin 1 2 3 4 5 6 7 8 Unidirectional logic level-shifting application Unidirectional logic level-shifting application Function VCC1 OUT1 OUT2 GND DIR IN2 IN1 VCC2 Description supply voltage of system-1 (0.8 V to 3.6 V) output level depends on VCC1 voltage output level depends on VCC1 voltage device GND the GND (LOW level) determines B port to A port direction input threshold value depends on VCC2 voltage input threshold value depends on VCC2 voltage supply voltage of system-2 (0.8 V to 3.6 V) Name VCC(A) 1A 2A GND DIR 2B 1B VCC(B) 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 23 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 13.2 Bidirectional logic level-shifting application Figure 10 shows the 74AVC2T45 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. VCC1 VCC1 VCC2 VCC2 74AVC2T45 I/O-1 PULL-UP/DOWN VCC(A) 1A 2A GND 1 2 3 4 8 7 6 5 VCC(B) 1B 2B DIR PULL-UP/DOWN I/O-2 DIR CTRL DIR CTRL system-1 system-2 001aag582 System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down. Fig 10. Bidirectional logic level-shifting application Table 12 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Table 12. 1 2 H H Bidirectional logic level-shifting application[1][2] I/O-2 input Z Description system-1 data to system-2 system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on the pull-up or pull-down. DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on the pull-up or pull-down. system-2 data to system-1 output Z State DIR CTRL I/O-1 3 4 [1] [2] L L Z input Z output System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down. H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 24 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 13.3 Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 13. VCC(A) 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V Typical total supply current (ICC(A) + ICC(B)) VCC(B) 0V 0 0.1 0.1 0.1 0.1 0.1 0.1 0.8 V 0.1 0.1 0.1 0.1 0.1 0.7 2.3 1.2 V 0.1 0.1 0.1 0.1 0.1 0.3 1.4 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.9 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.5 2.5 V 0.1 0.7 0.3 0.1 0.1 0.1 0.1 3.3 V 0.1 2.3 1.4 0.9 0.5 0.1 0.1 µA µA µA µA µA µA µA Unit 13.4 Enable times The enable times for the 74AVC2T45 are calculated from the following formulas: • ten (DIR to nA) = tdis (DIR to nB) + tpd (nB to nA) • ten (DIR to nB) = tdis (DIR to nA) + tpd (nA to nB) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74AVC2T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 25 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 14. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 Fig 11. Package outline SOT505-2 (TSSOP8) 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 26 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 12. Package outline SOT765-1 (VSSOP8) 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 27 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 13. Package outline SOT833-1 (XSON8) 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 28 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 D B A E A A1 detail X terminal 1 index area e1 L1 1 e b 4 v w M M CAB C C y1 C y L2 L 8 5 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT996-2 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 14. Package outline SOT996-2 (XSON8U) 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 29 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 15. Abbreviations Table 14. Acronym CDM DUT ESD HBM MM Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model 16. Revision history Table 15. Revision history Release date 20090505 Data sheet status Product data sheet Change notice Supersedes 74AVC2T45_3 Document ID 74AVC2T45_4 Modifications: 74AVC2T45_3 74AVC2T45_2 74AVC2T45_1 • Section 8 “Limiting values”: Changed: total power dissipation. Product data sheet Product data sheet Product data sheet 74AVC2T45_2 74AVC2T45_1 - 20090129 20080620 20070703 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 30 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AVC2T45_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 5 May 2009 31 of 32 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Application information. . . . . . . . . . . . . . . . . . 23 Unidirectional logic level-shifting application. . 23 Bidirectional logic level-shifting application. . . 24 Power-up considerations . . . . . . . . . . . . . . . . 25 Enable times . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 30 Legal information. . . . . . . . . . . . . . . . . . . . . . . 31 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Contact information. . . . . . . . . . . . . . . . . . . . . 31 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 May 2009 Document identifier: 74AVC2T45_4