74HC193N

74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Rev. 03 — 23 May 2007 Product data sheet 1. General description The 74HC193 and 74HCT193 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC193 and 74HCT193 are 4-bit synchronous binary up/down counters. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time, or erroneous operation will result. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL). The 74HC193 and 74HCT193 each contain four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions. Each flip-flop contains JK feedback from slave to master, such that a LOW-to-HIGH transition on the CPD input will decrease the count by one, while a similar transition on the CPU input will advance the count by one. One clock should be held HIGH while counting with the other, otherwise the circuit will either count by twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either clock input is LOW. Applications requiring reversible operation must make the reversing decision while the activating clock is HIGH to avoid erroneous counts. The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. 2. Features I I I I Synchronous reversible 4-bit binary counting Asynchronous parallel load Asynchronous reset Expandable without external logic 3. Ordering information Table 1. Ordering information Package Temperature range 74HC193D 74HC193DB 74HC193N 74HC193PW 74HCT193D 74HCT193DB 74HCT193N 74HCT193PW −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name SO16 SSOP16 DIP16 TSSOP16 SO16 SSOP16 DIP16 TSSOP16 Description plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic dual in-line package; 16 leads (300 mil) plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic dual in-line package; 16 leads (300 mil) plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT338-1 SOT38-4 SOT403-1 SOT109-1 SOT338-1 SOT38-4 SOT403-1 Type number 4. Functional diagram 15 D0 1 D1 10 D2 9 D3 TCU COUNTER TCD 12 13 CPU 14 MR FLIP-FLOPS Q0 3 2 Q1 6 Q2 7 Q3 001aag405 11 5 4 PL CPU CPD PL 11 5 4 14 MR D0 15 D1 1 D2 10 D3 9 12 13 TCU TCD CPD 3 Q0 2 Q1 6 Q2 7 Q3 001aag409 Fig 1. Functional diagram 74HC_HCT193_3 Fig 2. Logic symbol © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 2 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 11 5 4 14 15 1 10 9 C3 2+ G1 1− G2 R 3D CTR4 3 2 6 7 2CT = 0 1CT = 15 13 12 001aag410 Fig 3. IEC logic symbol 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 3 of 29 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 03 — 23 May 2007 CPD MR © NXP B.V. 2007. All rights reserved. 74HC_HCT193_3 NXP Semiconductors D0 D1 D2 D3 PL CPU TCU SD T Q T SD Q T SD Q T SD Q Presettable synchronous 4-bit binary up/down counter FF1 Q RD FF2 Q RD FF3 Q RD FF4 Q RD 74HC193; 74HCT193 TCD Q0 Q1 Q2 Q3 001aag412 4 of 29 Fig 4. Logic diagram NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 5. Pinning information 5.1 Pinning 74HC193 74HCT193 D1 1 2 3 4 5 6 7 8 001aaf408 74HC193 74HCT193 D1 Q1 Q0 CPD CPU Q2 Q3 GND 1 2 3 4 5 6 7 8 001aag406 16 VCC 15 D0 14 MR 13 TCD 12 TCU 11 PL 10 D2 9 D3 D1 Q1 Q0 CPD CPU Q2 Q3 GND 1 2 3 4 5 6 7 8 001aag407 16 VCC 15 D0 14 MR 13 TCD 12 TCU 11 PL 10 D2 9 D3 74HC193 74HCT193 16 VCC 15 D0 14 MR 13 TCD 12 TCU 11 PL 10 D2 9 D3 Q1 Q0 CPD CPU Q2 Q3 GND Fig 5. Pin configuration SO16 Fig 6. Pin configuration TSSOP16 and SSOP16 Fig 7. Pin configuration DIP16 5.2 Pin description Table 2. Symbol D0 D1 D2 D3 Q0 Q1 Q2 Q3 CPD CPU GND PL TCU TCD MR VCC [1] Pin description Pin 15 1 10 9 3 2 6 7 4 5 8 11 12 13 14 16 Description data input 0 data input 1 data input 2 data input 3 flip-flop output 0 flip-flop output 1 flip-flop output 2 flip-flop output 3 count down clock input[1] count up clock input[1] ground (0 V) asynchronous parallel load input (active LOW) terminal count up (carry) output (active LOW) terminal count down (borrow) output (active LOW) asynchronous master reset input (active HIGH) supply voltage LOW-to-HIGH, edge triggered. 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 5 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 6. Functional description Table 3. Function table[1] Inputs MR Reset (clear) Parallel load H H L L L L Count up Count down [1] Operating mode Outputs CPU CPD D0 X X X X L H ↑ H L H L H X X H ↑ X X L L H H X X D1 X X L L H H X X D2 X X L L H H X X D3 X X L L H H X X Q0 L L L L H H Q1 L L L L H H Q2 L L L L H H Q3 L L L L H H TCU TCD H H H H L H H[2] H L H L H H H H H[3] PL X X L L L L H H L L count up count down H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH clock transition. TCU = CPU at terminal count up (HHHH) TCD = CPD at terminal count down (LLLL). [2] [3] 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 6 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter MR(1) PL D0 D1 D2 D3 CPU(2) CPD(2) Q0 Q1 Q2 Q3 TCU TCD 0 CLEAR 13 PRESET 14 15 0 COUNT UP 1 2 1 0 15 14 COUNT DOWN 13 001aag411 (1) Clear overrides load, data and count inputs. (2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input (CPU) must be HIGH. Sequence Clear (reset outputs to zero); load (preset) to binary thirteen; count up to fourteen, fifteen, terminal count up, zero, one and two; count down to one, zero, terminal count down, fifteen, fourteen and thirteen. Fig 8. Typical clear, load and count sequence 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 7 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation DIP16 package SO16 package SSOP16 package TSSOP16 package [1] [2] [2] [2] [2] [2] Conditions VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to VCC + 0.5 V [1] [1] Min −0.5 −65 - Max +7.0 ±20 ±20 ±25 50 −50 +150 750 500 500 500 Unit V mA mA mA mA mA °C mW mW mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For DIP16 packages: above 70 °C the value of Ptot derates linearly at 12 mW/K. For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. 8. Recommended operating conditions Table 5. 74HC193 VCC VI VO Tamb tr supply voltage input voltage output voltage ambient temperature rise time inputs VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tf fall time inputs VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 6.0 1000 ns 500 400 ns ns 6.0 1000 ns 500 400 ns ns 2.0 0 0 −40 5.0 +25 6.0 VCC VCC V V V Recommended operating conditions Conditions Min Typ Max Unit Symbol Parameter +125 °C 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 8 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Table 5. 74HCT193 VCC VI VO Tamb tr tf Recommended operating conditions …continued Conditions Min 4.5 0 0 −40 inputs; VCC = 4.5 V inputs; VCC = 4.5 V Typ 5.0 +25 6.0 6.0 Max 5.5 VCC VCC 500 500 Unit V V V ns ns Symbol Parameter supply voltage input voltage output voltage ambient temperature rise time fall time +125 °C 9. Static characteristics Table 6. Static characteristics type 74HC193 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIH Parameter HIGH-level input voltage Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 2.0 V IO = −20 µA; VCC = 4.5 V IO = −20 µA; VCC = 6.0 V IO = −4.0 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC Ci VIH input leakage current supply current input capacitance HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 1.5 3.15 4.2 0 0 0 0.15 0.16 3.5 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 V V V V V µA µA pF V V V Min 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 Typ 1.2 2.4 3.2 0.8 2.1 2.8 2.0 4.5 6.0 4.32 5.81 Max 0.5 1.35 1.8 V V V V V Unit V V V V V V Tamb = 25 °C Tamb = −40 °C to +85 °C 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 9 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Table 6. Static characteristics type 74HC193 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIL Parameter LOW-level input voltage Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 2.0 V IO = −20 µA; VCC = 4.5 V IO = −20 µA; VCC = 6.0 V IO = −4.0 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC input leakage current supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 2.0 V IO = −20 µA; VCC = 4.5 V IO = −20 µA; VCC = 6.0 V IO = −4.0 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC input leakage current supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 0.1 0.1 0.1 0.4 0.4 ±1.0 160 V V V V V µA µA 1.9 4.4 5.9 3.7 5.2 V V V V V 0.1 0.1 0.1 0.33 0.33 ±1.0 80 V V V V V µA µA 1.9 4.4 5.9 3.84 5.34 V V V V V Min Typ Max 0.5 1.35 1.8 Unit V V V Tamb = −40 °C to +125 °C VIH HIGH-level input voltage 1.5 3.15 4.2 0.5 1.35 1.8 V V V V V V 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 10 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Table 7. Static characteristics type 74HCT193 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIH VIL VOH Parameter HIGH-level input voltage LOW-level input voltage HIGH-level output voltage Conditions VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VIH or VIL; VCC = 4.5 V IO = −20 µA IO = −4.0 mA VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 µA IO = 4.0 mA II ICC ∆ICC input leakage current supply current additional supply current VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per input pin; VI = VCC − 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn pins CPU, CPD pin PL pin MR Ci VIH VIL VOH input capacitance HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VIH or VIL; VCC = 4.5 V IO = −20 µA IO = −4.0 mA VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 µA IO = 4.0 mA II ICC ∆ICC input leakage current supply current additional supply current VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per input pin; VI = VCC − 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn pins CPU, CPD pin PL pin MR Tamb = −40 °C to +125 °C VIH VIL 74HC_HCT193_3 Min 2.0 4.4 3.98 - Typ 1.6 1.2 4.5 4.32 0 0.15 - Max 0.8 0.1 0.26 ±0.1 8.0 Unit V V V V V V µA µA Tamb = 25 °C 2.0 4.4 3.84 - 35 140 65 105 3.5 - 126 504 234 378 0.8 0.1 0.33 ±1.0 80 µA µA µA µA pF V V V V V V µA µA Tamb = −40 °C to +85 °C 2.0 - - 157.5 630 292.5 472.5 0.8 µA µA µA µA V V 11 of 29 HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V Rev. 03 — 23 May 2007 © NXP B.V. 2007. All rights reserved. Product data sheet NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Table 7. Static characteristics type 74HCT193 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VOH Parameter HIGH-level output voltage Conditions VI = VIH or VIL; VCC = 4.5 V IO = −20 µA IO = −4.0 mA VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 µA IO = 4.0 mA II ICC ∆ICC input leakage current supply current additional supply current VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per input pin; VI = VCC − 2.1 V and other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn pins CPU, CPD pin PL pin MR 171.5 686 318.5 514.5 µA µA µA µA 0.1 0.4 ±1.0 160 V V µA µA 4.4 3.7 V V Min Typ Max Unit 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 12 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 10. Dynamic characteristics Table 8. Symbol tpd Dynamic characteristics type 74HC193 Parameter propagation delay Conditions Min CPU, CPD to Qn; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPU to TCU; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD to TCD; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V PL to Qn; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR to Qn; see Figure 12 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Dn to Qn; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V PL to TCU, PL to TCD; see Figure 14 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR to TCU, MR to TCD; see Figure 14 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 74HC_HCT193_3 25 °C Typ Max [1] −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max 63 23 18 215 43 37 270 54 46 325 65 55 ns ns ns - 39 14 11 125 25 21 - 155 31 26 - 190 38 32 ns ns ns - 39 14 11 125 25 21 - 155 31 26 - 190 38 32 ns ns ns - 69 25 20 220 44 37 - 275 55 47 - 330 66 56 ns ns ns - 58 21 17 200 40 34 - 250 50 43 - 300 60 51 ns ns ns - 69 25 20 210 42 36 - 265 53 45 - 315 63 54 ns ns ns - 80 29 23 290 58 49 - 365 73 62 - 435 87 74 ns ns ns - 74 27 22 285 57 48 - 355 71 60 - 430 86 73 ns ns ns © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 13 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Table 8. Symbol tpd Dynamic characteristics type 74HC193 …continued Parameter propagation delay Conditions Min Dn to TCU, Dn to TCD; see Figure 14 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 80 29 23 19 7 6 19 7 6 290 58 49 75 15 13 75 15 13 365 73 62 95 19 16 95 19 16 435 87 74 110 22 19 110 22 19 ns ns ns ns ns ns ns ns ns 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max tTHL HIGH to LOW see Figure 12 output transition VCC = 2.0 V time VCC = 4.5 V VCC = 6.0 V LOW to HIGH see Figure 12 output transition VCC = 2.0 V time VCC = 4.5 V VCC = 6.0 V pulse width CPU, CPD (HIGH or LOW); see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR (HIGH); see Figure 12 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V PL (LOW); see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tTLH tW 100 20 17 22 8 6 - 125 25 21 - 150 30 26 - ns ns ns 100 20 17 25 9 7 - 125 25 21 - 150 30 26 - ns ns ns 100 20 17 19 7 6 - 125 25 21 - 150 30 26 - ns ns ns trec recovery time PL to CPU, CPD; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR to CPU, CPD; see Figure 12 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 50 10 9 0 0 0 65 13 11 75 15 13 ns ns ns 50 10 9 8 3 2 65 13 11 75 15 13 ns ns ns 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 14 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Table 8. Symbol tsu Dynamic characteristics type 74HC193 …continued Parameter set-up time Conditions Min Dn to PL; see Figure 13; note: CPU = CPD = HIGH VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 80 16 14 22 8 6 100 20 17 120 24 20 ns ns ns 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max th hold time Dn to PL; see Figure 13 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPU to CPD, CPD to CPU; see Figure 15 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 80 16 8 22 8 6 100 20 17 120 24 20 ns ns ns 0 0 0 −14 −5 −4 0 0 0 0 0 0 ns ns ns fmax maximum frequency CPU, CPD; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 4.0 20 24 [2] 13.5 41 49 24 - 3.2 16 19 - - 2.6 13 15 - - MHz MHz MHz pF CPD power dissipation capacitance VI = GND to VCC; VCC = 5 V; fi = 1 MHz - [1] [2] tpd is the same as tPHL and tPLH. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 15 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Table 9. Symbol tpd Dynamic characteristics type 74HCT193 Parameter propagation delay Conditions Min CPU, CPD to Qn; see Figure 9 VCC = 4.5 V CPU to TCU; see Figure 10 VCC = 4.5 V CPD to TCD; see Figure 10 VCC = 4.5 V PL to Qn; see Figure 11 VCC = 4.5 V MR to Qn; see Figure 12 VCC = 4.5 V Dn to Qn; see Figure 11 VCC = 4.5 V PL to TCU, PL to TCD; see Figure 14 VCC = 4.5 V MR to TCU, MR to TCD; see Figure 14 VCC = 4.5 V Dn to TCU, Dn to TCD; see Figure 14 VCC = 4.5 V 32 7 58 15 73 19 87 22 ns ns 29 55 69 83 ns 31 55 69 83 ns 27 46 58 69 ns 22 40 50 60 ns 26 46 58 69 ns 15 27 34 41 ns 15 27 34 41 ns [1] 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 23 43 - 54 - 65 ns tTHL HIGH to LOW see Figure 12 output transition VCC = 4.5 V time LOW to HIGH see Figure 12 output transition VCC = 4.5 V time pulse width CPU, CPD (HIGH or LOW); see Figure 9 VCC = 4.5 V MR (HIGH); see Figure 12 VCC = 4.5 V PL (LOW); see Figure 11 VCC = 4.5 V tTLH - 7 15 - 19 - 22 ns tW 25 11 - 31 - 38 - ns 20 7 - 25 - 30 - ns 20 8 - 25 - 30 - ns 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 16 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Table 9. Symbol trec Dynamic characteristics type 74HCT193 …continued Parameter recovery time Conditions Min PL to CPU, CPD; see Figure 11 VCC = 4.5 V MR to CPU, CPD; see Figure 12 VCC = 4.5 V 10 0 13 15 ns 10 2 13 15 ns 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max tsu set-up time Dn to PL; see Figure 13; note: CPU = CPD = HIGH VCC = 4.5 V 16 8 20 24 ns Dn to PL; see Figure 13 VCC = 4.5 V CPU to CPD, CPD to CPU; see Figure 15 VCC = 4.5 V 16 7 20 24 ns 0 −6 0 0 ns th hold time fmax maximum frequency power dissipation capacitance CPU, CPD; see Figure 9 VCC = 4.5 V 20 [2] 43 26 - 16 - - 13 - - MHz pF CPD VI = GND to VCC − 1.5 V; VCC = 5 V; fi = 1 MHz - [1] [2] tpd is the same as tPHL and tPLH. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 17 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 11. Waveforms 1/fmax VI CPU, CPD input GND tW t PHL VOH Qn output VOL VM 001aag413 VM t PLH Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 9. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock pulse frequency VI CPU, CPD input GND tPHL VOH TCU, TCD output VOL VM 001aag414 VM tPLH Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 10. The clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 18 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter VI Dn input GND VI PL input GND tW VI CPU, CPD input GND t PLH VOH Qn output VOL 001aag415 VM VM t rec VM t PHL VM Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 11. The parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock input (CPU, CPD) VI MR input GND tW VI CPU, CPD input GND t PHL VOH Qn output VOL 90 % VM 10 % t THL t TLH 001aag416 VM t rec VM Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 12. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and output transition times 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 19 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter VI Dn input GND VI PL input GND VOH Qn output VOL 001aag417 VM tsu th VM tsu th The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 10. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 13. The data input (Dn) to parallel load input (PL) set-up and hold times VI PL, MR, Dn input GND tPLH VOH TCU, TCD output VOL 001aag418 VM tPHL VM Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage drops that occur with the output load. Fig 14. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs (TCU, TCD) propagation delays VI CPU or CPD input GND th VI CPD or CPU input GND VM 001aag419 VM Measurement points are given in Table 10. Fig 15. The CPU to CPD or CPD to CPU hold times 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 20 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Table 10. Type 74HC193 74HCT193 Measurement points Input VM 0.5 × VCC 1.3 V VI GND to VCC GND to 3 V Output VM 0.5 × VCC 1.3 V VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC PULSE GENERATOR VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 11. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor S1 = Test selection switch Fig 16. Load circuitry for measuring switching times Table 11. Type 74HC193 74HCT193 Test data Input VI VCC 3V tr, tf 6 ns 6 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 kΩ 1 kΩ S1 position tPHL, tPLH open open 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 21 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 12. Application information data input D0 D1 D2 D3 up clock down clock CPU CPD PL asynchronous parallel load reset data output 001aag420 D0 D1 D2 D3 CPU CPD PL TCU carry borrow TCU IC1 TCD MR IC2 TCD MR Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Fig 17. Application for cascaded up/down counter with parallel load 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 22 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 18. Package outline SOT109-1 (SO16) 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 23 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 19. Package outline SOT338-1 (SSOP16) 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 24 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 20. Package outline SOT38-4 (DIP16) 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 25 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 21. Package outline SOT403-1 (TSSOP16) 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 26 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 14. Revision history Table 12. Revision history Release date 20070523 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT193_CNV_2 Document ID 74HC_HCT193_3 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Family specification included Product specification - 74HC_HCT193_CNV_2 19970828 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 27 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 15. Legal information 16. Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.2 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74HC_HCT193_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 23 May 2007 28 of 29 NXP Semiconductors 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information. . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Contact information. . . . . . . . . . . . . . . . . . . . . 28 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 May 2007 Document identifier: 74HC_HCT193_3