74HC4024N,652

74HC4024 7-stage binary ripple counter Rev. 7 — 31 October 2013 Product data sheet 1. General description The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Low-power dissipation  Complies with JEDEC standard no. 7A  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V.  Multiple package options  Specified from 40 C to +80 C and from 40 C to +125 C. 3. Applications  Frequency dividing circuits  Time delay circuits. 74HC4024 NXP Semiconductors 7-stage binary ripple counter 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4024N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HC4024D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HC4024DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74HC4024PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 5. Functional diagram Q6 3 Q5 4 7-STAGE COUNTER Q4 5 Q3 6 1 Q2 Q3 2 9 Q1 11 6 Q0 12 5 CT = 0 MR 1 2 Fig 2. Q T Q FF 2 Q T Q RD T T Q FF 5 Q RD IEC logic symbol Q FF 4 Q RD Fig 3. Q FF 3 3 001aab907 Functional diagram Q FF 1 6 001aab908 Logic symbol T 6 CT 4 CP 001aab906 CP 9 2 3 Q6 12 11 + 4 Q5 Fig 1. 1 5 Q4 MR 0 Q2 9 11 Q1 CP CTR7 12 Q0 T Q RD Q FF 6 T FF 7 Q RD Q RD RD MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 001aab909 Fig 4. Logic diagram 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 2 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter 6. Pinning information 6.1 Pinning 74HC4024 CP 1 14 VCC MR 2 13 n.c. Q6 3 12 Q0 Q5 4 11 Q1 Q4 5 10 n.c. Q3 6 9 Q2 GND 7 8 n.c. 001aab905 Fig 5. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description CP 1 clock input (HIGH-to-LOW, edge-triggered) MR 2 master reset input (active HIGH) Q6, Q5, Q4, Q3, Q2, Q2, Q1, Q0 3, 4, 5, 6, 9, 11, 12 parallel output GND 7 ground (0 V) n.c. 8, 10, 13 not connected VCC 14 positive supply voltage 7. Functional description Table 3. Function table[1] Input Output MR CP Qn H X L L  no change  count [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition. 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 3 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to VCC + 0.5 V - 25 mA ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C DIP14 package [1] - 750 mW SO14 package [2] - 500 mW SSOP14 and TSSOP14 package [3] - 500 mW total power dissipation Ptot [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. [3] For (T)SSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Min Typ Max Unit VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V t/V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V 40 - +125 C Tamb Conditions ambient temperature 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 4 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - V IO = 4 mA; VCC = 4.5 V 3.98 4.32 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - V IO = 20 A; VCC = 2.0 V - 0 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 V Tamb = 25 C VIH VIL VOH VOL LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 4 mA; VCC = 4.5 V - 0.15 0.26 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 A CI input capacitance - 3.5 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 - - V IO = 20 A; VCC = 4.5 V 4.4 - - V IO = 20 A; VCC = 6.0 V 5.9 - - V IO = 4 mA; VCC = 4.5 V 3.84 - - V IO = 5.2 mA; VCC = 6.0 V 5.34 - - V Tamb = 40 C to +85 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 74HC4024 Product data sheet VI = VIH or VIL All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 5 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V - - 0.1 V IO = 20 A; VCC = 4.5 V - - 0.1 V IO = 20 A; VCC = 6.0 V - - 0.1 V IO = 4 mA; VCC = 4.5 V - - 0.33 V IO = 5.2 mA; VCC = 6.0 V - - 0.33 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 80 A VCC = 2.0 V 1.5 - - V Tamb = 40 C to +125 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 - - V IO = 20 A; VCC = 4.5 V 4.4 - - V IO = 20 A; VCC = 6.0 V 5.9 - - V IO = 4 mA; VCC = 4.5 V 3.7 - - V IO = 5.2 mA; VCC = 6.0 V 5.2 - - V IO = 20 A; VCC = 2.0 V - - 0.1 V IO = 20 A; VCC = 4.5 V - - 0.1 V IO = 20 A; VCC = 6.0 V - - 0.1 V IO = 4 mA; VCC = 4.5 V - - 0.4 V VI = VIH or VIL VI = VIH or VIL IO = 5.2 mA; VCC = 6.0 V - - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 160 A 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 6 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter 11. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V - 47 175 ns VCC = 4.5 V - 17 35 ns VCC = 6.0 V - 14 30 ns - 14 - ns VCC = 2.0 V - 25 80 ns VCC = 4.5 V - 9 16 ns VCC = 6.0 V - 7 14 ns VCC = 2.0 V - 63 200 ns VCC = 4.5 V - 23 40 ns - 18 34 ns VCC = 2.0 V - 19 75 ns VCC = 4.5 V - 7 15 ns VCC = 6.0 V - 6 13 ns VCC = 2.0 V 80 17 - ns VCC = 4.5 V 16 6 - ns VCC = 6.0 V 14 5 - ns VCC = 2.0 V 80 22 - ns VCC = 4.5 V 16 8 - ns VCC = 6.0 V 14 6 - ns VCC = 2.0 V 50 6 - ns VCC = 4.5 V 10 2 - ns VCC = 6.0 V 9 2 - ns VCC = 2.0 V 6.0 27 - MHz VCC = 4.5 V 30 82 - MHz Tamb = 25 C tpd propagation delay CP to Q0; see Figure 6 [1] VCC = 5.0 V; CL = 15 pF Qn to Qn+1; see Figure 6 tPHL HIGH to LOW propagation delay [1] MR to Q0; see Figure 6 VCC = 6.0 V tt tW transition time pulse width see Figure 6 [2] CP HIGH or LOW; see Figure 6 MR HIGH; see Figure 6 trec fmax CPD recovery time maximum frequency power dissipation capacitance 74HC4024 Product data sheet MR to CP; see Figure 6 CP; see Figure 6 VCC = 6.0 V 35 98 - MHz VCC = 5.0 V; CL = 15 pF - 90 - MHz - 25 - pF VI = GND to VCC [3] All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 7 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions Min Typ Max Unit Tamb = 40 C to +85 C tpd propagation delay CP to Q0; see Figure 6 [1] VCC = 2.0 V - - 220 ns VCC = 4.5 V - - 44 ns - - 37 ns VCC = 6.0 V Qn to Qn+1; see Figure 6 tPHL HIGH to LOW propagation delay [1] VCC = 2.0 V - - 100 ns VCC = 4.5 V - - 20 ns VCC = 6.0 V - - 17 ns MR to Q0; see Figure 6 VCC = 2.0 V - - 250 ns VCC = 4.5 V - - 50 ns - - 43 ns VCC = 2.0 V - - 95 ns VCC = 4.5 V - - 19 ns VCC = 6.0 V - - 16 ns VCC = 6.0 V tt tW transition time pulse width see Figure 6 [2] CP HIGH or LOW; see Figure 6 VCC = 2.0 V 100 - - ns VCC = 4.5 V 20 - - ns VCC = 6.0 V 17 - - ns MR HIGH; see Figure 6 trec fmax recovery time maximum frequency 74HC4024 Product data sheet VCC = 2.0 V 100 - - ns VCC = 4.5 V 20 - - ns VCC = 6.0 V 17 - - ns VCC = 2.0 V 65 - - ns VCC = 4.5 V 13 - - ns VCC = 6.0 V 11 - - ns MR to CP; see Figure 6 CP; see Figure 6 VCC = 2.0 V 4.8 - - MHz VCC = 4.5 V 24 - - MHz VCC = 6.0 V 28 - - MHz All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 8 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions Min Typ Max Unit Tamb = 40 C to +125 C tpd propagation delay CP to Q0; see Figure 6 [1] VCC = 2.0 V - - 265 ns VCC = 4.5 V - - 53 ns - - 45 ns VCC = 6.0 V Qn to Qn+1; see Figure 6 tPHL HIGH to LOW propagation delay [1] VCC = 2.0 V - - 120 ns VCC = 4.5 V - - 24 ns VCC = 6.0 V - - 20 ns MR to Q0; see Figure 6 VCC = 2.0 V - - 300 ns VCC = 4.5 V - - 60 ns - - 51 ns VCC = 6.0 V tt tW transition time pulse width see Figure 6 [2] VCC = 2.0 V - - 110 ns VCC = 4.5 V - - 22 ns VCC = 6.0 V - - 19 ns CP HIGH or LOW; see Figure 6 VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns MR HIGH; see Figure 6 trec recovery time 74HC4024 Product data sheet VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns VCC = 2.0 V 75 - - ns VCC = 4.5 V 15 - - ns VCC = 6.0 V 13 - - ns MR to CP; see Figure 6 All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 9 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions fmax maximum frequency CP; see Figure 6 [1] Min Typ Max Unit VCC = 2.0 V 4.0 - - MHz VCC = 4.5 V 20 - - MHz VCC = 6.0 V 24 - - MHz tpd is the same as tPLH and tPHL. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 12. Waveforms MR input VM tW 1/fmax trec VM CP input tPHL Q0 or Qn output tPLH tW 90 % tPHL 90 % 10 % VM 10 % tTLH tTHL 001aab910 Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) recovery time. VM = 0.5  VI. Fig 6. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 10 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter VCC PULSE GENERATOR VI VO DUT RT CL mna101 Test data is given in Table 8. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 7. Table 8. Test circuit for measuring switching times Test data Supply Input Load VCC VI tr, tf CL 2.0 V VCC 6 ns 50 pF 4.5 V VCC 6 ns 50 pF 6.0 V VCC 6 ns 50 pF 5.0 V VCC 6 ns 15 pF 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 11 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Package outline SOT27-1 (DIP14) 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 12 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 13 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 10. Package outline SOT337-1 (SSOP14) 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 14 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 11. Package outline SOT402-1 (TSSOP14) 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 15 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter 14. Abbreviations Table 9. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC4024 v.7 20131031 Product data sheet - 74HC4024 v.6 Modifications: • General description updated. 74HC4024 v.6 20120823 Product data sheet - 74HC4024 v.5 74HC4024 v.4 20100929 Product data sheet - 74HC4024 v.3 74HC4024 v.3 20041112 Product data sheet - 74HC_HCT4024_CNV v.2 74HC_HCT4024_CNV v.2 19970901 Product specification - 74HC_HCT4024 v.1 74HC_HCT4024 v.1 19901201 Product specification - - 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 16 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74HC4024 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 17 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC4024 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 October 2013 © NXP B.V. 2013. All rights reserved. 18 of 19 74HC4024 NXP Semiconductors 7-stage binary ripple counter 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 31 October 2013 Document identifier: 74HC4024