74HC4066N,652

74HC4066; 74HCT4066 Quad single-pole single-throw analog switch Rev. 7 — 2 April 2013 Product data sheet 1. General description The 74HC4066; 74HCT4066 is a quad single pole, single throw analog switch. Each switch features two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When nE is LOW, the analog switch is turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Input levels nE inputs:  For 74HC4066: CMOS level  For 74HCT4066: TTL level  Low ON resistance:  50  (typical) at VCC = 4.5 V  45  (typical) at VCC = 6.0 V  35  (typical) at VCC = 9.0 V  Specified in compliance with JEDEC standard no. 7A  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch 3. Ordering information Table 1. Ordering information Type number 74HC4066N Package Temperature range Name Description Version 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body SOT402-1 width 4.4 mm 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5  3  0.85 mm 74HCT4066N 74HC4066D 74HCT4066D 74HC4066DB 74HCT4066DB 74HC4066PW 74HCT4066PW 74HC4066BQ 74HCT4066BQ SOT762-1 4. Functional diagram 1 13 4 5 1Y 1Z 1 2 13 # 1E 1 2Y 2Z 2 13 # 3 5# 4 2E 3 5# 8 6 3Y 3Z 9 8 8 9 12 4Y 4Z 10 10 Logic symbol 74HC_HCT4066 Product data sheet 11 12 # 12 # 1 2 X1 1 1 3 X1 1 1 9 X1 1 1 10 X1 4E (a) 001aad269 Fig 1. 6# 6# 3E 11 11 4 1 (b) 001aad270 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 2 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch nY nE VCC VCC GND nZ 001aad271 Fig 3. Schematic diagram (one switch) 5. Pinning information 1Y terminal 1 index area 14 VCC 5.1 Pinning 1 14 VCC 1Z 2 13 1E 1Z 2 13 1E 12 4E 2Z 3 12 4E 2Y 4 4066 11 4Y 2E 5 (1) 10 4Z 3E 6 1 1Y 4066 11 4Y 10 4Z 2E 5 3E 6 9 3Z GND 7 8 3Y VCC 9 8 4 3Y 2Y 7 3 GND 2Z 3Z 001aac116 Transparent top view 001aad268 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to VCC. Fig 4. Pin configuration for DIP14, SO14, SSOP14 and TSSOP14 Fig 5. Pin configuration for DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1Z, 2Z, 3Z, 4Z 2, 3, 9, 10 independent input or output 1Y, 2Y, 3Y, 4Y 1, 4, 8, 11 independent input or output GND 7 ground (0 V) 1E, 2E, 3E, 4E 13, 5, 6, 12 enable input (active HIGH) VCC 14 supply voltage 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 3 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch 6. Functional description Table 3. Function table[1] Input nE Switch L OFF H ON [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V ISK switch clamping current VSW < 0.5 V or VSW > VCC + 0.5 V ISW switch current VSW = 0.5 V to VCC + 0.5 V ICC supply current IGND ground current Tstg storage temperature total power dissipation Ptot P [1] [2] power dissipation Conditions Min Max Unit 0.5 +11.0 V - 20 mA - 20 mA - 25 mA - 50 mA - 50 mA 65 +150 C DIP14 package - 750 SO14, (T)SSOP14 and DHVQFN14 packages - 500 100 mW Tamb = 40 C to +125 C per switch [1] [2] - To avoid drawing VCC current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of terminals Yn. In this case there is no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or GND. For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C. 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 4 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions 74HC4066 74HCT4066 Unit Min Typ Max Min Typ Max 2.0 5.0 10.0 4.5 5.0 5.5 V VI input voltage GND - VCC GND - VCC V VSW switch voltage GND - VCC GND - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V VCC = 10.0 V - - 35 - - - ns/V 9. Static characteristics Table 6. RON resistance per switch for types 74HC4066 and 74HCT4066 VI = VIH or VIL; for test circuit see Figure 6. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. For 74HC4066: VCC  GND = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4066: VCC  GND = 4.5 V. Symbol RON(peak) Parameter ON resistance (peak) 40 C to +85 C Conditions Min Max Min Max - - - - -  VCC = 4.5 V; ISW = 1000 A - 54 - 118 142  VCC = 6.0 V; ISW = 1000 A - 42 - 105 126  VCC = 9.0 V; ISW = 1000 A - 32 - 88 105  - 80 - - -  Vis = VCC to GND VCC = 2.0 V; ISW = 100 A RON(rail) ON resistance (rail) 40 C to +125 C Unit Typ[1] [2] Vis = GND VCC = 2.0 V; ISW = 100 A [2] VCC = 4.5 V; ISW = 1000 A - 35 - 95 115  VCC = 6.0 V; ISW = 1000 A - 27 - 82 100  VCC = 9.0 V; ISW = 1000 A - 20 - 70 85  Vis = VCC VCC = 2.0 V; ISW = 100 A 74HC_HCT4066 Product data sheet - 100 - - -  VCC = 4.5 V; ISW = 1000 A - 42 - 106 128  VCC = 6.0 V; ISW = 1000 A - 35 - 94 113  VCC = 9.0 V; ISW = 1000 A - 20 - 78 95  [2] All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 5 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch Table 6. RON resistance per switch for types 74HC4066 and 74HCT4066 …continued VI = VIH or VIL; for test circuit see Figure 6. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. For 74HC4066: VCC  GND = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4066: VCC  GND = 4.5 V. Symbol Parameter 40 C to +85 C Conditions Min RON ON resistance mismatch between channels 40 C to +125 C Unit Typ[1] Max Min Max Vis = VCC to GND - - - - -  VCC = 4.5 V - 5 - - -  VCC = 6.0 V - 4 - - -  VCC = 9.0 V - 3 - - -  VCC = 2.0 V [2] [1] Typical values are measured at Tamb = 25 C. [2] At supply voltages (VCC  GND) approaching 2 V, the analog switch ON resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital signals only, when using these supply voltages. aaa-003459 60 RON (Ω) VCC = 4.5 V 50 VSW 6V 40 9V VCC 30 nE VIH nY Vis nZ 20 GND ISW 10 0 1.8 aaa-003458 Vis = 0 V to VCC 3.6 5.4 7.2 Vis (V) 9.0 Vis = 0 V to VCC V SW R ON = --------I SW Fig 6. Test circuit for measuring RON 74HC_HCT4066 Product data sheet Fig 7. Typical RON as a function of input voltage Vis All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 6 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch Table 7. Static characteristics 74HC4066 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Conditions Min Typ[1] Max Unit VCC = 2.0 V 1.5 1.2 - V Tamb = 40 C to +85 C VIH VIL II HIGH-level input voltage LOW-level input voltage input leakage current VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 9.0 V 6.3 4.7 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.80 V VCC = 9.0 V - 4.3 2.70 V VCC = 6.0 V - - 1.0 A VCC = 10.0 V - - 2.0 A VI = VCC or GND IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW = VCC  GND; see Figure 8 IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL; VSW = VCC  GND; see Figure 9 ICC supply current VI = VCC or GND; Vis = GND or VCC; Vos = VCC or GND - - 1.0 A - - 1.0 A VCC = 6.0 V - - 20.0 A VCC = 10.0 V - - 40.0 A per channel CI input capacitance - 3.5 - pF Csw switch capacitance - 8 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 9.0 V 6.3 - - V VCC = 2.0 V - - 0.50 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.80 V VCC = 9.0 V - - 2.70 V VCC = 6.0 V - - 1.0 A VCC = 10.0 V - - 2.0 A - - 1.0 A - - 1.0 A Tamb = 40 C to +125 C VIH VIL II IS(OFF) HIGH-level input voltage LOW-level input voltage input leakage current OFF-state leakage current VI = VCC or GND VCC = 10.0 V; VI = VIH or VIL; VSW = VCC  GND; see Figure 8 per channel IS(ON) ON-state leakage current 74HC_HCT4066 Product data sheet VCC = 10.0 V; VI = VIH or VIL; VSW = VCC  GND; see Figure 9 All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 7 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch Table 7. Static characteristics 74HC4066 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Min Typ[1] Max Unit VCC = 6.0 V - - 40 A VCC = 10.0 V - - 80 A Conditions Min Typ[1] Max Unit Symbol Parameter Conditions ICC supply current VI = VCC or GND; Vis = GND or VCC; Vos = VCC or GND [1] Typical values are measured at Tamb = 25 C. Table 8. Static characteristics 74HCT4066 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Tamb = 40 C to +85 C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 A IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW = VCC  GND; see Figure 8 - - 1.0 A per channel IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW = VCC  GND; see Figure 9 - - 1.0 A ICC supply current VI = VCC or GND; Vis = GND or VCC; Vos = VCC or GND; VCC = 4.5 V to 5.5 V - - 20.0 A ICC additional supply current per input pin; VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 100 450 A CI input capacitance - 3.5 - pF Csw switch capacitance - 8 - pF 2.0 - - V Tamb = 40 C to +125 C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 A IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW = VCC  GND; see Figure 8 - - 1.0 A IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL; VSW = VCC  GND; see Figure 9 - - 1.0 A ICC supply current VI = VCC or GND; Vis = GND or VCC; Vos = VCC or GND; VCC = 4.5 V to 5.5 V - - 40 A ICC additional supply current per input pin; VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - - 490 A per channel [1] Typical values are measured at Tamb = 25 C. 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 8 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch VCC VCC E VIL ISW Yn Vis E VIH Z ISW GND ISW Z Yn Vos Vis Vos GND aaa-003456 Fig 8. aaa-003457 Vis = VCC and Vos = GND Vis = VCC and Vos = open Vis = GND and Vos = VCC Vis = GND and Vos = open Test circuit for measuring OFF-state leakage current Fig 9. Test circuit for measuring ON-state leakage current 10. Dynamic characteristics Table 9. Dynamic characteristics 74HC4066 GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 12. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter 40 C to +85 C Conditions propagation delay nY to nZ or nZ to nY; RL =  ; see Figure 10 tpd Typ[1] Max Min Max [2] VCC = 2.0 V - 8 75 - 90 ns VCC = 4.5 V - 3 15 - 18 ns VCC = 6.0 V - 2 13 - 15 ns - 2 10 - 12 ns VCC = 2.0 V - 44 190 - 225 ns VCC = 4.5 V - 16 38 - 45 ns VCC = 5.0 V; CL = 15 pF - 13 - - - ns VCC = 6.0 V - 13 33 - 38 ns VCC = 9.0 V - 16 26 - 30 ns - 36 125 - 150 ns VCC = 4.5 V - 13 25 - 30 ns VCC = 5.0 V; CL = 15 pF - 11 - - - ns VCC = 6.0 V - 10 21 - 26 ns - 8 16 - 20 ns - - - pF VCC = 9.0 V turn-off time toff turn-on time ton nE to nY or nZ; see Figure 11 nE to nY or nZ; see Figure 11 [4] [3] VCC = 2.0 V VCC = 9.0 V power dissipation capacitance CPD per switch; VI = GND to VCC [1] Typical values are measured at Tamb = 25 C. [2] tpd is the same as tPHL and tPLH. [3] ton is the same as tPHZ and tPLZ. 74HC_HCT4066 Product data sheet 40 C to +125 C Unit Min [5] 11 All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 9 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch [4] toff is the same as tPZH and tPZL. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi + {(CL + Csw)  VCC2  fo} where: fi = input frequency in MHz; fo = output frequency in MHz; {(CL + Csw)  VCC2  fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. Table 10. Dynamic characteristics 74HCT4066 GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 12. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter propagation delay tpd 40 C to +85 C Conditions nY to nZ or nZ to nY; RL =  ; see Figure 10 Min Max Min Max - 3 15 - 18 ns - 20 44 - 53 ns - 16 - - - ns - 12 30 - 36 ns - 12 - - - ns - 12 - - - pF [2] VCC = 4.5 V turn-off time toff nE to nY or nZ; see Figure 11 [4] VCC = 4.5 V VCC = 5.0 V; CL = 15 pF turn-on time ton nE to nY or nZ; see Figure 11 [3] VCC = 4.5 V VCC = 5.0 V; CL = 15 pF power dissipation per switch; capacitance VI = GND to (VCC  1.5 V) CPD [1] [5] Typical values are measured at Tamb = 25 C. [2] tpd is the same as tPHL and tPLH. [3] ton is the same as tPHZ and tPLZ. [4] toff is the same as tPZH and tPZL. [5] 40 C to +125 C Unit Typ[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi + {(CL + Csw)  VCC2  fo} where: fi = input frequency in MHz; fo = output frequency in MHz; {(CL + Csw)  VCC2  fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 10 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch 11. Waveforms 50 % Vis input tPLH tPHL 50 % Vos output 001aad555 Fig 10. Input (Vis) to output (Vos) propagation delays VI VM E input 0V tPLZ tPZL 50 % Vos output 10 % tPHZ tPZH 90 % 50 % Vos output switch ON switch ON switch OFF aaa-003460 Measurement points are shown in Table 11. Fig 11. Turn-on and turn-off times Table 11. Measurement points Type VI 74HC4066 VCC 0.5VCC 74HCT4066 3.0 V 1.3 V 74HC_HCT4066 Product data sheet VM All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 11 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC Vis PULSE GENERATOR VCC Vos VI S1 RL open DUT RT CL GND 001aag732 Test data is given in Table 12. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistor. S1 = Test selection switch. Fig 12. Load circuitry for measuring switching times Table 12. Test data Test Input Control E Output Switch Yn (Z) tr, tf Switch Z (Yn) CL RL GND to VCC 6 ns 50 pF - open GND to VCC VCC 6 ns 50 pF, 15 pF 1 k GND GND to VCC GND 6 ns 50 pF, 15 pF 1 k VCC VI[1] Vis tPHL, tPLH GND tPHZ, tPZH tPLZ, tPZL [1] S1 position For 74HCT4066: maximum input voltage VI = 3.0 V. 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 12 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch 12. Additional dynamic characteristics Table 13. Additional dynamic characteristics Recommended conditions and typical values; GND = 0 V; Tamb = 25 C. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Conditions THD fi = 1 kHz; RL = 10 k; CL = 50 pF; see Figure 13 total harmonic distortion Min Typ Max Unit % VCC = 4.5 V; VI = 4.0 V (p-p) - 0.04 - % VCC = 9.0 V; VI = 8.0 V (p-p) - 0.02 - % - 0.12 - % - 0.06 - % - 180 - MHz - 200 - MHz VCC = 4.5 V - 50 - dB VCC = 9.0 V - 50 - dB - 110 - mV - 220 - mV VCC = 4.5 V - 60 - dB VCC = 9.0 V - 60 - dB fi = 10 kHz; RL = 10 k; CL = 50 pF; see Figure 13 VCC = 4.5 V; VI = 4.0 V (p-p) VCC = 9.0 V; VI = 8.0 V (p-p) f(3dB) 3 dB frequency response RL = 50 ; CL = 10 pF; see Figure 15 [2] VCC = 4.5 V VCC = 9.0 V iso RL = 600 ; CL = 50 pF; fi = 1 MHz; see Figure 14 isolation (OFF-state) crosstalk voltage Vct [1] between digital input and switch (peak to peak value); RL = 600 ; CL = 50 pF; fi = 1 MHz; see Figure 16 VCC = 4.5 V VCC = 9.0 V Xtalk between switches; RL = 600 ; CL = 50 pF; fi = 1 MHz; see Figure 17 crosstalk [1] [1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 ). [2] Adjust input voltage Vis to 0 dBm level at Vos for fi = 1 MHz (0 dBm = 1 mW into 50 ). After set-up, fi is increased to obtain a reading of 3 dB at Vos. VCC VCC nE VIH 2RL 10 μF nY/nZ nZ/nY fi VO 2RL D CL 001aaj468 Fig 13. Test circuit for measuring total harmonic distortion 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 13 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch mna082 0 (dB) −20 −40 −60 −80 −100 10 102 103 104 105 106 fi (kHz) a. Isolation (OFF-state) VCC VCC nE VIL 2RL 0.1 μF nY/nZ nZ/nY fi VO CL 2RL dB 001aaj470 b. Test circuit VCC = 4.5 V; GND = 0 V; RL = 600 ; Rsource = 1 k. Fig 14. Isolation (OFF-state) as a function of frequency 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 14 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch mna083 5 (dB) 0 −5 10 102 103 104 105 106 fi (kHz) a. Typical 3 dB frequency response VCC VCC nE VIH 2RL 0.1 μF nY/nZ fi nZ/nY VO 2RL CL dB 001aaj469 b. Test circuit VCC = 4.5 V; GND = 0 V; RL = 50 ; Rsource = 1 k. Fig 15. 3 dB frequency response 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 15 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch VCC nE VCC VCC GND 2RL 2RL nY/nZ nZ/nY DUT 2RL 2RL oscilloscope CL GND mnb011 a. Circuit V(p−p) mnb012 b. Crosstalk voltage Fig 16. Test circuit for measuring crosstalk voltage (between the digital input and the switch) VCC 1E VIH 0.1 μF RL 2RL 1Y or 1Z 1Z or 1Y CHANNEL ON fi 2RL CL V VO1 V VO2 2E VIL VCC VCC 2RL 2RL 2Y or 2Z 2RL 2Z or 2Y CHANNEL OFF 2RL CL 001aai846 Fig 17. Test circuit for measuring crosstalk (between the switches) 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 16 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 18. Package outline SOT27-1 (DIP14) 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 17 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 19. Package outline SOT108-1 (SO14) 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 18 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 20. Package outline SOT337-1 (SSOP14) 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 19 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 21. Package outline SOT402-1 (TSSOP14) 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 20 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 0.5 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 22. Package outline SOT762-1 (DHVQFN14) 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 21 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch 14. Abbreviations Table 14. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT4066 v.7 20130402 Product data sheet - 74HC_HCT4066 v.6 - 74HC_HCT4066 v.5 Modifications: 74HC_HCT4066 v.6 Modifications: • • Descriptive title corrected (errata). New general description (errata). 20120718 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 74HC_HCT4066 v.5 20041111 74HC_HCT4066 v.4 Product data sheet - 74HC_HCT4066 v.4 20030617 Product data sheet - 74HC_HCT4066_CNV v.3 74HC_HCT4067_CNV v.3 19981110 Product data sheet - 74HC_HCT4066_CNV v.2 74HC_HCT4066_CNV v.2 19981002 Product specification - - 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 22 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT4066 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 23 of 25 74HC4066; 74HCT4066 NXP Semiconductors Quad single-pole single-throw analog switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT4066 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 April 2013 © NXP B.V. 2013. All rights reserved. 24 of 25 NXP Semiconductors 74HC4066; 74HCT4066 Quad single-pole single-throw analog switch 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Additional dynamic characteristics . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information. . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 April 2013 Document identifier: 74HC_HCT4066