74HC4067

74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Rev. 03 — 15 October 2007 Product data sheet 1. General description The 74HC4067; 74HCT4067 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4067B. The device is specified in compliance with JEDEC standard no. 7A. The 74HC4067; 74HCT4067 is a 16-channel analog multiplexer/demultiplexer with four address inputs (S0 to S3), an active-LOW enable input (E), sixteen independent inputs/outputs (Y0 to Y15) and a common input/output (Z). The 74HC4067; 74HCT4067 contains sixteen bidirectional analog switches, each with one side connected to an independent input/output (Y0 to Y15) and the other side connected to a common input/output (Z). With pin E = LOW, one of the sixteen switches is selected by pins S0 to S3 (low impedance ON-state). All unselected switches are in the high-impedance OFF-state. With pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins S0 to S3. The analog inputs/outputs (Y0 to Y15, and Z) can swing between VCC as a positive limit and GND as a negative limit. VCC to GND may not exceed 10 V. 2. Features I Low ON resistance: N 80 Ω (typical) at VCC = 4.5 V N 70 Ω (typical) at VCC = 6.0 V N 60 Ω (typical) at VCC = 9.0 V I Typical ‘break before make’ built-in 3. Applications I Analog multiplexing and demultiplexing I Digital multiplexing and demultiplexing I Signal gating NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 4. Ordering information Table 1. Ordering information Package Temperature range Name 74HC4067 74HC4067N 74HC4067D 74HC4067DB 74HC4067PW 74HC4067BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C DIP24 SO24 SSOP24 TSSOP24 plastic dual in-line package; 24 leads (600 mil); reverse bending plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT101-1 SOT137-1 SOT340-1 SOT355-1 SOT815-1 Description Version Type number DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm DIP24 SO24 SSOP24 TSSOP24 plastic dual in-line package; 24 leads (600 mil); reverse bending plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm 74HCT4067 74HCT4067N 74HCT4067D 74HCT4067DB 74HCT4067PW 74HCT4067BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SOT101-1 SOT137-1 SOT340-1 SOT355-1 SOT815-1 DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 2 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 5. Functional diagram 10 11 14 13 0 16 × 3 G16 0 15 9 S0 S1 S2 S3 10 11 14 13 8 7 6 5 4 3 2 23 22 21 20 19 18 17 E 15 1 Z 16 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 15 1 MUX/DMUX 9 0 8 1 7 2 6 3 5 4 4 5 3 6 2 7 23 8 22 9 21 10 20 11 19 12 18 13 17 14 16 15 001aag726 001aag725 Fig 1. Logic symbol Fig 2. IEC logic symbol Yn VCC VCC Z from logic GND 001aag729 Fig 3. Schematic diagram (one switch) 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 3 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 9 Y0 8 Y1 S0 10 7 Y2 6 Y3 S1 11 5 Y4 4 Y5 S2 14 3 Y6 2 Y7 S3 13 1-OF-16 DECODER 23 Y8 22 Y9 21 Y10 20 Y11 19 Y12 18 Y13 17 Y14 E 15 16 Y15 1Z 001aag727 Fig 4. Functional diagram 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 4 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Y0 Y1 Y2 Y3 Y4 S0 Y5 Y6 Y7 S1 Y8 Y9 Y10 S2 Y11 Y12 Y13 S3 Y14 Y15 E Z 001aag728 Fig 5. Logic diagram 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 5 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning 74HC4067 74HCT4067 terminal 1 index area 24 VCC 23 Y8 22 Y9 21 Y10 20 Y11 19 Y12 18 Y13 17 Y14 16 Y15 15 E 14 S2 13 S3 001aag730 Z Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 1 2 3 4 5 6 7 8 9 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 2 3 4 5 6 7 8 9 VCC(1) GND 12 S3 13 24 VCC 23 Y8 22 Y9 21 Y10 20 Y11 19 Y12 18 Y13 17 Y14 16 Y15 15 E 14 S2 S0 10 S1 11 GND 12 S0 10 S1 11 1 Z 74HC4067 74HCT4067 001aag731 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. Fig 6. Pin configuration for DIP24, SO24, SSOP24 and TSSOP24 Fig 7. Pin configuration for DHVQFN24 6.2 Pin description Table 2. Symbol Z Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 S0 S1 GND S3 S2 74HC_HCT4067_3 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description common input/output independent input/output 7 independent input/output 6 independent input/output 5 independent input/output 4 independent input/output 3 independent input/output 2 independent input/output 1 independent input/output 0 address input 0 address input 1 ground (0 V) address input 3 address input 2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 6 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Table 2. Symbol E Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 VCC Pin description …continued Pin 15 16 17 18 19 20 21 22 23 24 Description enable input (active LOW) independent input/output 15 independent input/output 14 independent input/output 13 independent input/output 12 independent input/output 11 independent input/output 10 independent input/output 9 independent input/output 8 supply voltage 7. Functional description Table 3. Inputs E L L L L L L L L L L L L L L L L H [1] Function table[1] Channel ON S3 L L L L L L L L H H H H H H H H X S2 L L L L H H H H L L L L H H H H X S1 L L H H L L H H L L H H L L H H X S0 L H L H L H L H L H L H L H L H X Y0 to Z Y1 to Z Y2 to Z Y3 to Z Y4 to Z Y5 to Z Y6 to Z Y7 to Z Y8 to Z Y9 to Z Y10 to Z Y11 to Z Y12 to Z Y13 to Z Y14 to Z Y15 to Z - H = HIGH voltage level; L = LOW voltage level; X = don’t care. 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 7 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK ISK ISW ICC IGND Tstg Ptot Parameter supply voltage input clamping current switch clamping current switch current supply current ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C DIP24 package SO24 package SSOP24 package TSSOP24 package DHVQFN24 package P [1] [2] [3] [4] [4] [5] Conditions [1] Min −0.5 −65 - Max +11.0 ±20 ±20 ±25 50 −50 +150 750 500 500 500 500 100 Unit V mA mA mA mA mA °C mW mW mW mW mW mW VI < −0.5 V or VI > VCC + 0.5 V VSW < −0.5 V or VSW > VCC + 0.5 V VSW = −0.5 V to (VCC + 0.5 V) power dissipation per switch To avoid drawing VCC current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of terminals Yn. In this case there is no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or GND. For DIP24 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO24 package: Ptot derates linearly with 8 mW/K above 70 °C. For SSOP24 and TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN24 package: Ptot derates linearly with 4.5 mW/K above 60 °C. [2] [3] [4] [5] 9. Recommended operating conditions Table 5. Symbol 74HC4067 VCC VI VSW tr supply voltage input voltage switch voltage rise time VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 10.0 V tf fall time VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 10.0 V Tamb 74HC_HCT4067_3 Recommended operating conditions Parameter Conditions Min 2.0 GND GND −40 Typ 5.0 6.0 6.0 +25 Max 10.0 VCC VCC 1000 500 400 250 1000 500 400 250 +125 Unit V V V ns ns ns ns ns ns ns ns °C ambient temperature © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 8 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Table 5. Symbol VCC VI VSW tr tf Tamb Recommended operating conditions …continued Parameter supply voltage input voltage switch voltage rise time fall time ambient temperature VCC = 4.5 V VCC = 4.5 V Conditions Min 4.5 GND GND −40 Typ 5.0 6.0 6.0 +25 Max 5.5 VCC VCC 500 500 +125 Unit V V V ns ns °C 74HCT4067 10. Static characteristics Table 6. RON resistance per switch for types 74HC4067 and 74HCT4067 VI = VIH or VIL; for test circuit see Figure 8. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. For 74HC4067: VCC − GND = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4067: VCC − GND = 4.5 V. Symbol Parameter Conditions Typ RON(peak) ON resistance (peak) Vis = VCC to GND VCC = 2.0 V; ISW = 100 µA VCC = 4.5 V; ISW = 1000 µA VCC = 6.0 V; ISW = 1000 µA VCC = 9.0 V; ISW = 1000 µA RON(rail) ON resistance (rail) Vis = GND or VCC VCC = 2.0 V; ISW = 100 µA VCC = 4.5 V; ISW = 1000 µA VCC = 6.0 V; ISW = 1000 µA VCC = 9.0 V; ISW = 1000 µA ∆RON ON resistance mismatch Vis = VCC to GND between channels VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V [1] [1] [1] [1] 25 °C Max −40 °C to +125 °C Unit Max Max (85 °C) (125 °C) 225 200 165 200 175 150 270 240 195 240 210 180 Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω 110 95 75 150 90 80 70 9 8 6 180 160 130 160 140 120 - At supply voltages (VCC − GND) approaching 2 V, the analog switch ON resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital signals only, when using these supply voltages. 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 9 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 110 RON (Ω) VSW VCC E Yn GND Z 50 Vis ISW (3) (1) mnb047 90 70 VIL (2) 30 001aag733 10 0 1.8 3.6 5.4 7.2 Vis (V) 9.0 Vis = 0 V to (VCC − GND) Vis = 0 V to (VCC − GND) (1) VCC = 4.5 V (2) VCC = 6.0 V (3) VCC = 9.0 V V SW R ON = ---------I SW Fig 8. Test circuit for measuring RON Fig 9. Typical RON as a function of input voltage Vis Table 7. Static characteristics 74HC4067 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol VIH Parameter HIGH-level input voltage Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V II input leakage current VI = VCC or GND VCC = 6.0 V VCC = 10.0 V IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 10 per channel all channels IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 11 ±0.1 ±0.8 ±0.8 µA µA µA ±0.1 ±0.2 µA µA Min 1.5 3.15 4.2 6.3 Typ 1.2 2.4 3.2 4.7 0.8 2.1 2.8 4.3 Max 0.5 1.35 1.80 2.70 Unit V V V V V V V V Tamb = 25 °C 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 10 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Table 7. Static characteristics 74HC4067 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol ICC Parameter supply current Conditions VI = VCC or GND; Vis = GND or VCC; Vos = VCC or GND VCC = 6.0 V VCC = 10.0 V CI VIH input capacitance HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V II input leakage current VI = VCC or GND VCC = 6.0 V VCC = 10.0 V IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 10 per channel all channels IS(ON) ICC ON-state leakage current supply current VCC = 10.0 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 11 VI = VCC or GND; Vis = GND or VCC; Vos = VCC or GND VCC = 6.0 V VCC = 10.0 V Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V II input leakage current VI = VCC or GND VCC = 6.0 V VCC = 10.0 V ±1.0 ±2.0 µA µA 1.5 3.15 4.2 6.3 0.50 1.35 1.80 2.70 V V V V V V V V 80.0 160 µA µA ±1.0 ±8.0 ±8.0 µA µA µA ±1.0 ±2.0 µA µA Tamb = −40 °C to +85 °C 1.5 3.15 4.2 6.3 0.50 1.35 1.80 2.70 V V V V V V V V 3.5 8.0 16.0 µA µA pF Min Typ Max Unit 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 11 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Table 7. Static characteristics 74HC4067 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol IS(OFF) Parameter OFF-state leakage current Conditions VCC = 10.0 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 10 per channel all channels IS(ON) ICC ON-state leakage current supply current VCC = 10.0 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 11 VI = VCC or GND; Vis = GND or VCC; Vos = VCC or GND VCC = 6.0 V VCC = 10.0 V Table 8. Static characteristics 74HCT4067 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol VIH VIL II IS(OFF) Parameter HIGH-level input voltage LOW-level input voltage input leakage current OFF-state leakage current Conditions VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VCC or GND; VCC = 5.5 V VCC = 5.5 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 10 per channel all channels IS(ON) ICC ∆ICC ON-state leakage current supply current additional supply current VCC = 5.5 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 11 VI = VCC or GND; Vis = GND or VCC; Vos = VCC or GND; VCC = 4.5 V to 5.5 V per input pin; VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V pin E pin Sn CI VIH VIL II IS(OFF) input capacitance HIGH-level input voltage LOW-level input voltage input leakage current OFF-state leakage current VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VCC or GND; VCC = 5.5 V VCC = 5.5 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 10 per channel all channels ±1.0 ±8.0 µA µA Tamb = −40 °C to +85 °C 2.0 0.8 ±1.0 V V µA 60 50 3.5 216 180 µA µA pF ±0.1 ±0.8 ±0.8 8.0 µA µA µA µA Min 2.0 Typ 1.6 1.2 Max 0.8 ±0.1 Unit V V µA Tamb = 25 °C 160 320 µA µA ±1.0 ±8.0 ±8.0 µA µA µA Min Typ Max Unit 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 12 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Table 8. Static characteristics 74HCT4067 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol IS(ON) ICC ∆ICC Parameter ON-state leakage current supply current additional supply current Conditions VCC = 5.5 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 11 VI = VCC or GND; Vis = GND or VCC; Vos = VCC or GND; VCC = 4.5 V to 5.5 V per input pin; VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V pin E pin Sn Tamb = −40 °C to +125 °C VIH VIL II IS(OFF) HIGH-level input voltage LOW-level input voltage input leakage current OFF-state leakage current VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VCC or GND; VCC = 5.5 V VCC = 5.5 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 10 per channel all channels IS(ON) ICC ∆ICC ON-state leakage current supply current additional supply current VCC = 5.5 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 11 VI = VCC or GND; Vis = GND or VCC; Vos = VCC or GND; VCC = 4.5 V to 5.5 V per input pin; VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V pin E pin Sn 294 245 µA µA ±1.0 ±8.0 ±8.0 160 µA µA µA µA 2.0 0.8 ±1.0 V V µA 270 225 µA µA Min Typ Max ±8.0 80.0 Unit µA µA VCC E ISW Vis VCC E Z Yn Vos VIH VIL Z GND ISW Vos Yn ISW Vis GND 001aag734 001aag735 Vis = VCC and Vos = GND Vis = GND and Vos = VCC Vis = VCC and Vos = open Vis = GND and Vos = open Fig 10. Test circuit for measuring OFF-state leakage current Fig 11. Test circuit for measuring ON-state leakage current 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 13 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 11. Dynamic characteristics Table 9. Dynamic characteristics 74HC4067 GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Conditions Typ tpd propagation delay Yn to Z; see Figure 12 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V Z to Yn VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V toff turn-off time E to Yn; see Figure 13 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V VCC = 9.0 V Sn to Yn VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V VCC = 9.0 V E to Z VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V Sn to Z VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V 94 34 27 25 290 58 47 45 365 73 62 56 435 87 74 68 ns ns ns ns 85 31 25 24 275 55 47 42 345 69 59 53 415 83 71 63 ns ns ns ns 83 30 29 24 21 250 50 43 38 315 63 54 48 375 75 64 57 ns ns ns ns ns [3] [1][2] 25 °C Max −40 °C to +125 °C Unit Max Max (85 °C) (125 °C) 95 19 16 11 75 15 13 10 315 63 54 48 110 22 19 14 90 18 15 12 375 75 64 57 ns ns ns ns ns ns ns ns ns ns ns ns ns 25 9 7 5 18 6 5 4 74 27 27 22 20 75 15 13 9 60 12 10 8 250 50 43 38 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 14 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Table 9. Dynamic characteristics 74HC4067 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Conditions Typ ton turn-on time E to Yn; see Figure 13 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V VCC = 9.0 V Sn to Yn VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V VCC = 9.0 V E to Z VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V Sn to Z VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V CPD power dissipation capacitance tpd is the same as tPHL and tPLH. Due to higher Z terminal capacitance (16 switches versus 1) the delay figures to the Z terminal are higher than those to the Y terminal. ton is the same as tPHZ and tPLZ. toff is the same as tPZH and tPZL. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑{(CL + Csw) × VCC2 × fo} where: fi = input frequency in MHz; fo = output frequency in MHz; ∑{(CL + Csw) × VCC2 × fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. [4] 25 °C Max −40 °C to +125 °C Unit Max Max (85 °C) (125 °C) 345 69 59 53 375 75 64 56 345 69 59 53 375 75 64 56 415 83 71 63 450 90 77 68 415 83 71 63 450 90 77 68 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF 80 29 26 23 17 88 32 29 26 18 85 31 25 18 94 34 27 19 [5] 275 55 47 42 300 60 51 45 275 55 47 42 300 60 51 45 29 per switch; VI = GND to VCC - [1] [2] [3] [4] [5] 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 15 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Table 10. Dynamic characteristics 74HCT4067 GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter Conditions Typ tpd propagation delay Yn to Z; see Figure 12 VCC = 4.5 V Z to Yn VCC = 4.5 V toff turn-off time E to Yn; see Figure 13 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF Sn to Yn VCC = 4.5 V VCC = 5.0 V; CL = 15 pF E to Z VCC = 4.5 V Sn to Z VCC = 4.5 V ton turn-on time E to Yn; see Figure 13 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF Sn to Yn VCC = 4.5 V VCC = 5.0 V; CL = 15 pF E to Z VCC = 4.5 V Sn to Z VCC = 4.5 V CPD power dissipation capacitance per switch; VI = GND to (VCC − 1.5 V) [5] [4] [3] [1][2] 25 °C Max −40 °C to +125 °C Unit Max Max (85 °C) (125 °C) 19 15 69 69 75 75 75 75 81 81 22 18 83 83 90 90 90 90 98 98 ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF 9 6 26 26 31 30 30 35 32 32 35 33 38 38 - 15 12 55 55 60 60 60 60 65 65 29 [1] [2] [3] [4] [5] tpd is the same as tPHL and tPLH. Due to higher Z terminal capacitance (16 switches versus 1) the delay figures to the Z terminal are higher than those to the Y terminal. ton is the same as tPHZ and tPLZ. toff is the same as tPZH and tPZL. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑{(CL + Csw) × VCC2 × fo} where: fi = input frequency in MHz; fo = output frequency in MHz; ∑{(CL + Csw) × VCC2 × fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 16 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 12. Waveforms Vis input 50 % tPLH tPHL Vos output 50 % 001aad555 Fig 12. Input (Vis) to output (Vos) propagation delays VI E, Sn inputs 0V tPLZ tPZL VM Vos output 10 % tPHZ 90 % Vos output tPZH 50 % 50 % switch ON switch OFF switch ON 001aad556 Measurement points are shown in Table 11. Fig 13. Turn-on and turn-off times Table 11. Type 74HC4067 74HCT4067 Measurement points VI VCC 3.0 V VM 0.5VCC 1.3 V 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 17 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC Vis PULSE GENERATOR VI DUT RT CL VCC Vos RL S1 open GND 001aag732 Test data is given in Table 12. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistor. S1 = Test selection switch. Fig 14. Load circuitry for measuring switching times Table 12. Test Test data Input Control E VI[1] tPHL, tPLH tPHZ, tPZH tPLZ, tPZL [1] Output Address Sn VI[1] GND or VCC GND to VCC GND to VCC Switch Yn (Z) tr, tf Vis GND to VCC VCC GND 6 ns 6 ns 6 ns Switch Z (Yn) CL 50 pF 50 pF, 15 pF 50 pF, 15 pF RL 1 kΩ 1 kΩ S1 position GND GND to VCC GND to VCC open GND VCC For 74HCT4067: maximum input voltage VI = 3.0 V. 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 18 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 13. Additional dynamic characteristics Table 13. Additional dynamic characteristics Recommended conditions and typical values; GND = 0 V; Tamb = 25 °C. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter THD total harmonic distortion Conditions RL = 10 kΩ; CL = 50 pF; see Figure 15 fi = 1 kHz VCC = 4.5 V; Vis(p-p) = 4.0 V VCC = 9.0 V; Vis(p-p) = 8.0 V fi = 10 kHz VCC = 4.5 V; Vis(p-p) = 4.0 V VCC = 9.0 V; Vis(p-p) = 8.0 V αiso isolation (OFF-state) RL = 600 Ω; CL = 50 pF; see Figure 16 VCC = 4.5 V VCC = 9.0 V f(-3dB) −3 dB frequency response RL = 50 Ω; CL = 10 pF; see Figure 17 VCC = 4.5 V VCC = 9.0 V Csw switch capacitance independent pins Y common pin Z [1] [2] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 Ω). Adjust input voltage Vis to 0 dBm level at Vos for fi = 1 MHz (0 dBm = 1 mW into 50 Ω). After set-up, fi is increased to obtain a reading of −3 dB at Vos. [2] [1] Min Typ Max Unit - 0.04 0.02 0.12 0.06 −50 −50 90 100 5 45 - % % % % dB dB MHz MHz pF pF VCC E 10 µF VCC 2RL VIL Vis Yn GND Z Vos 2RL CL fi D 001aag736 Fig 15. Test circuit for measuring total harmonic distortion 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 19 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 0 αiso (dB) −20 001aae332 −40 −60 −80 −100 10 102 103 104 105 fi (kHz) 106 a. Isolation (OFF-state) VCC E 0.1 µF VCC 2RL VIH Vis Yn GND Z Vos 2RL CL fi dB 001aag737 b. Test circuit VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ. Fig 16. Isolation (OFF-state) as a function of frequency 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 20 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 5 001aag739 Vos (dB) 0 −5 10 102 103 104 105 fi (kHz) 106 a. Typical −3 dB frequency response VCC E Z GND VCC 2RL VIL Vis 0.1 µF Yn Vos 2RL CL fi dB 001aag738 b. Test circuit VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ. Fig 17. −3 dB frequency response 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 21 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 14. Package outline DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1 seating plane D ME A2 A L A1 c Z e b1 b 24 13 MH wM (e 1) pin 1 index E 1 12 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.2 A1 min. 0.51 0.02 A2 max. 4 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 32.0 31.4 1.26 1.24 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.1 e1 15.24 0.6 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 2.2 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT101-1 REFERENCES IEC 051G02 JEDEC MO-015 JEITA SC-509-24 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 18. Package outline SOT101-1 (DIP24) 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 22 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c y HE vMA Z 24 13 Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 19. Package outline SOT137-1 (SO24) 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 23 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 12 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 20. Package outline SOT340-1 (SSOP24) 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 24 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 12 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 21. Package outline SOT355-1 (TSSOP24) 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 25 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm SOT815-1 D B A E A A1 c detail X terminal 1 index area C terminal 1 index area 2 L 12 e1 e b 11 vMCAB wM C y1 C y 1 Eh e2 24 13 23 Dh 0 14 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.6 5.4 Dh 4.25 3.95 E (1) 3.6 3.4 Eh 2.25 1.95 e 0.5 e1 4.5 e2 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT815-1 REFERENCES IEC --JEDEC --JEITA --EUROPEAN PROJECTION ISSUE DATE 03-04-29 Fig 22. Package outline SOT815-1 (DHVQFN24) 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 26 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 15. Revision history Table 14. Revision history Release date 20071015 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT4067_CNV_2 Document ID 74HC_HCT4067_3 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added: type numbers 74HC4067BQ and 74HCT4067BQ (DHVQFN24 package). Product specification - 74HC_HCT4067_CNV_2 19970901 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 27 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74HC_HCT4067_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 October 2007 28 of 29 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 14 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Additional dynamic characteristics . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Contact information. . . . . . . . . . . . . . . . . . . . . 28 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 October 2007 Document identifier: 74HC_HCT4067_3