74HC7403D-Q100,518

74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state Rev. 1 — 21 September 2012 Product data sheet 1. General description The 74HC7403-Q100; 74HCT7403-Q100 is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 4 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. A higher data-rate can be obtained in applications where the status flags are not used (burst-mode). With separate controls for shift-in (SI) and shift-out (SO), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR), an output enable input (OE) and flags. The data-in-ready (DIR) and data-out-ready (DOR) flags indicate the status of the device. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Synchronous or asynchronous operation  30 MHz (typical) shift-in and shift-out rates  Readily expandable in word and bit dimensions  Pinning arranged for easy board layout: input pins directly opposite output pins  Input levels:  For 74HC7403-Q100: CMOS level  For 74HCT7403-Q100: TTL level  3-state outputs  Complies with JEDEC standard JESD7A  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  Multiple package options 3. Applications  High-speed disc or tape controller  Communications buffer 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state 4. Ordering information Table 1. Ordering information Type number Package 74HC7403D-Q100 Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT7403D-Q100 5. Functional diagram  ),)2[  2(  ' 4   ' 4   ' 4   ' 4   6, '25   62 ',5  * =    '      PJD PJD Logic symbol Fig 2. 62$  ),)2$  'Q% 62 62%  4Q$ '25 '25% ',5%  6,$ ',5$ ',5 IEC logic symbol 6,% '25$ 6,   *   '$7$,1387 &75 & &7 &7  &7!     05 Fig 1. >,5@ >25@ (1 = ),)2% 4Q%  '$7$287387 'Q$ 05 2( 05 2( 05 PJD 2( Fig 3. Functional diagram 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 2 of 32 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  5 )3 6 '25 4 05 NXP Semiconductors 74HC_HCT7403_Q100 Product data sheet 5 62 [ 6,  5 )6 6  5 4 5 )) 4 6  4 5 5 )) 4 6 5 4 6 4 )) WR )) 5  5 )) 4 6  4 5 )% 4 6 4 ',5 2( ' ' &/ &/ &/ &/ &/ &/ &/ &/ 4  /$7&+(6  /$7&+(6  /$7&+(6  /$7&+(6 ' 4 SRVLWLRQ SRVLWLRQWR LOW on S input of the flip-flops FS, FB and FP set Q output to HIGH independent of state on R input LOW on R input of FF1 to FF64 sets Q output to LOW independent of state on S input SRVLWLRQ PVE 3 of 32 © NXP B.V. 2012. All rights reserved. 4-bit x 64-word FIFO register; 3-state SRVLWLRQ Logic diagram 67$7( 287387 %8))(5 4 ' Fig 4. 4 74HC7403-Q100; 74HCT7403-Q100 Rev. 1 — 21 September 2012 All information provided in this document is subject to legal disclaimers. 5 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state 6. Pinning information 6.1 Pinning +&4 +&74 2(   9&& ',5   62 6,   '25 '   4 '   4 '   4 '   4 *1'   05 DDD Fig 5. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) DIR 2 data-in-ready output SI 3 shift-in input (active HIGH) D0 to D3 4, 5, 6, 7 parallel data input GND 8 ground (0 V) MR 9 asynchronous master-reset input (active LOW) Q0 to Q3 13, 12, 11, 10 data output DOR 14 data-out-ready output SO 15 shift-out input (active LOW) VCC 16 supply voltage 7. Functional description A DIR flag indicates the input stage status, either empty and ready to receive data (DIR = HIGH) or full and busy (DIR = LOW). When DIR and SI are HIGH, data present at D0 to D3 is shifted into the input stage; once complete DIR goes LOW. When SI is set LOW, data is automatically shifted to the output stage or to the last empty location. DIR set HIGH indicates a FIFO which can receive data. 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 4 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state A DOR flag indicates the output stage status, either data available (DOR = HIGH) or busy (DOR = LOW). When SO and DOR are HIGH, data is available at the outputs (Q0 to Q3). When SO is set LOW new data may be shifted into the output stage, once complete DOR is set HIGH. 7.1 Expanded format The DOR and DIR signals are used to allow the 74HC7403-Q100; 74HCT7403-Q100 to be cascaded. Both parallel and serial expansion is possible. (see Figure 18). Serial expansion is only possible with typical devices. 7.1.1 Parallel expension Parallel expension is accomplished by logically ANDing the DOR and DIR signals to form a composite signal. 7.1.2 Serial expension Parallel expension is accomplished by: • Tying the data outputs of the first device to the data inputs of the second device. • Connecting the DOR pin of the first device to the SI pin of the second device. • Connecting the SO pin of the first device to the DIR pin of the second device. 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) - 35 mA ICC supply current - +70 mA IGND ground current - 70 mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 500 mW [1] [1] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 5 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state 9. Recommended operating conditions Table 4. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC7403-Q100 Min Typ 74HCT7403-Q100 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 10. Static characteristics Table 5. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ VCC = 2.0 V 1.5 VCC = 4.5 V 3.15 VCC = 6.0 V 4.2 VCC = 2.0 V - VCC = 4.5 V - VCC = 6.0 V 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 1.2 - 1.5 - 1.5 - V 2.4 - 3.15 - 3.15 - V 3.2 - 4.2 - 4.2 - V 0.8 0.5 - 0.5 - 0.5 V 2.1 1.35 - 1.35 - 1.35 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 8 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 10 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 8 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 10 mA; VCC = 6.0 V - 0.15 0.26 - 0.33 - 0.4 V 74HC7403-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V - - 0.5 - 5.0 - 10.0 A 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 6 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state Table 5. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min ICC supply current CI input capacitance VI = VCC or GND; IO = 0 A; VCC = 6.0 V Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max - 500 - 1000 - - 50 - 3.5 - A pF 74HCT7403-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 8 mA 3.98 4.32 - 3.84 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 8 mA - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A - - 0.5 - 5.0 - 10 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 50 - 500 - 1000 A ICC additional supply current VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A per input pin; Dn inputs - 75 270 - 338 - 368 A per input pin; OE input - 100 360 - 450 - 490 A per input pin; SI input - 150 540 - 675 - 735 A per input pin; MR input - 150 540 - 675 - 735 A per input pin; SO input - 150 540 - 675 - 735 A - 3.5 - CI input capacitance 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 pF © NXP B.V. 2012. All rights reserved. 7 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state 11. Dynamic characteristics Table 6. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 69 210 - 265 - 315 ns VCC = 4.5 V - 25 42 - 53 - 63 ns VCC = 6.0 V - 20 36 - 45 - 54 ns - 66 205 - 255 - 310 ns 74HC7403-Q100 tpd propagation delay [1] MR to DIR or DOR; see Figure 8 [1] SI to DIR; see Figure 6 VCC = 2.0 V VCC = 4.5 V - 24 41 - 51 - 62 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns - 19 35 - 43 - 53 ns VCC = 2.0 V - 94 290 - 365 - 435 ns VCC = 4.5 V - 34 58 - 73 - 87 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns - 27 49 - 62 - 74 ns VCC = 2.0 V - 11 35 - 45 - 55 ns VCC = 4.5 V - 4 7 - 9 - 11 ns - 3 6 - 8 - 9 ns VCC = 2.0 V - 105 325 - 406 - 488 ns VCC = 4.5 V - 38 65 - 81 - 98 ns VCC = 6.0 V - 30 55 - 69 - 83 ns VCC = 2.0 V - 52 160 - 200 - 240 ns VCC = 4.5 V - 19 32 - 40 - 48 ns - 15 27 - 34 - 41 ns VCC = 2.0 V - 2.2 7 - 8.8 - 10.5 ns VCC = 4.5 V - 0.8 1.4 - 1.8 - 2.1 ns - 0.6 1.2 - 1.5 - 1.8 ns VCC = 2.0 V - 2.8 9 - 11.2 - 13.5 ns VCC = 4.5 V - 1.0 1.8 - 2.2 - 2.7 ns VCC = 6.0 V - 0.8 1.5 - 1.9 - 2.3 ns VCC = 6.0 V SO to DOR; see Figure 9 [1] VCC = 6.0 V DOR to Qn; see Figure 10 [1] VCC = 6.0 V SO to Qn; see Figure 14 tPHL HIGH to LOW propagation delay [1] MR to Qn; see Figure 8 VCC = 6.0 V tPLH LOW to HIGH propagation delay SI to DOR; see Figure 10 [5] VCC = 6.0 V SO to DIR; see Figure 7 74HC_HCT7403_Q100 Product data sheet [6] All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 8 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state Table 6. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17. Symbol Parameter ten enable time 25 C Conditions Min Typ Max Min Max Min Max VCC = 2.0 V - 44 150 - 190 - 225 ns VCC = 4.5 V - 16 30 - 38 - 45 ns - 13 26 - 32 - 38 ns VCC = 2.0 V - 50 150 - 190 - 225 ns VCC = 4.5 V - 18 30 - 38 - 45 ns - 14 26 - 33 - 38 ns OE to Qn; see Figure 16 [2] VCC = 6.0 V tdis disable time OE to Qn; see Figure 16 [3] VCC = 6.0 V tt tW transition time pulse width 40 C to +85 C 40 C to +125 C Unit [4] Qn; see Figure 14 VCC = 2.0 V - 14 60 - 75 - 90 ns VCC = 4.5 V - 5 12 - 15 - 18 ns VCC = 6.0 V - 4 10 - 13 - 15 ns VCC = 2.0 V 35 11 - 45 - 55 - ns VCC = 4.5 V 7 4 - 9 - 11 - ns VCC = 6.0 V 6 3 - 8 - 9 - ns VCC = 2.0 V 70 22 - 90 - 105 - ns VCC = 4.5 V 14 8 - 18 - 21 - ns VCC = 6.0 V 12 6 - 15 - 18 - ns VCC = 2.0 V 10 41 130 8 165 8 195 ns VCC = 4.5 V 5 15 26 4 33 4 39 ns VCC = 6.0 V 4 12 22 3 28 3 23 ns VCC = 2.0 V 14 52 160 12 200 12 240 ns VCC = 4.5 V 7 19 32 6 40 6 48 ns VCC = 6.0 V 6 15 27 5 34 5 41 ns VCC = 2.0 V 120 39 - 150 - 180 - ns VCC = 4.5 V 24 14 - 30 - 36 - ns VCC = 6.0 V 20 11 - 26 - 31 - ns VCC = 2.0 V 80 24 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 7 - 17 - 20 - ns SI HIGH or LOW; see Figure 6 SO HIGH or LOW; see Figure 9 DIR HIGH; see Figure 7 DOR HIGH; see Figure 10 MR LOW; see Figure 8 trec recovery time 74HC_HCT7403_Q100 Product data sheet MR to SI; see Figure 15 All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 9 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state Table 6. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17. Symbol Parameter tsu th fmax set-up time hold time maximum frequency 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 8 36 - 6 - 6 - ns VCC = 4.5 V 4 13 - 3 - 3 - ns VCC = 6.0 V 3 10 - 3 - 3 - ns Dn to SI; see Figure 13 Dn to SI; see Figure 13 VCC = 2.0 V 135 44 - 170 - 205 - ns VCC = 4.5 V 27 16 - 34 - 12 - ns VCC = 6.0 V 5 13 - 29 - 14 - ns VCC = 2.0 V 3.6 9.9 - 2.8 - 2.4 - MHz VCC = 4.5 V 18 30 - 14 - 12 - MHz - 30 - - - - - MHz 21 36 - 16 - 14 - MHz VCC = 2.0 V 3.6 9.9 - 2.8 - 2.4 - MHz VCC = 4.5 V 18 30 - 14 - 12 - MHz - 30 - - - - - MHz 21 36 - 16 - 14 - MHz VCC = 2.0 V - 7.6 - - - - - MHz VCC = 4.5 V - 23 - - - - - MHz - 27 - - - - - MHz - 475 - - - - - pF SI, SO burst mode; see Figure 11 and Figure 12 VCC = 5 V; CL = 15 pF VCC = 6.0 V SI, SO using flags; see Figure 6 and Figure 9 VCC = 5 V; CL = 15 pF VCC = 6.0 V SI, SO cascaded; see Figure 6 and Figure 9 VCC = 6.0 V CPD power dissipation capacitance 74HC_HCT7403_Q100 Product data sheet VI = GND to VCC [7] All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 10 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state Table 6. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 30 51 - 53 - 63 74HCT7403-Q100 tpd propagation delay [1] MR to DIR or DOR; see Figure 8 VCC = 4.5 V SI to DIR; see Figure 6 VCC = 4.5 V - 25 43 - 54 - 65 ns VCC = 5 V; CL = 15 pF - 17 - - - - - ns - 36 61 - 76 - 92 ns - 17 - - - - - ns - 7 12 - 15 - 18 ns - 42 72 - 90 - 108 ns - 22 38 - 48 - 57 ns - 0.8 1.4 - 1.75 - 2.1 ns - 1.0 1.8 - 2.25 - 2.7 ns - 16 30 - 38 - 45 ns - 19 30 - 38 - 45 ns - 5 12 - 15 - 18 ns 9 5 - 6 - 8 - ns 14 8 - 18 - 21 - ns 5 17 29 4 36 4 44 ns 7 21 36 6 45 6 54 ns 26 15 - 33 - 39 - ns SO to DOR; see Figure 9 [1] VCC = 4.5 V VCC = 5 V; CL = 15 pF DOR to Qn; see Figure 10 [1] VCC = 4.5 V SO to Qn; see Figure 14 [1] VCC = 4.5 V tPHL tPLH HIGH to LOW propagation delay MR to Qn; see Figure 8 LOW to HIGH propagation delay SI to DOR; see Figure 10 enable time OE to Qn; see Figure 16 VCC = 4.5 V [5] VCC = 4.5 V SO to DIR; see Figure 7 [6] VCC = 4.5 V ten [2] VCC = 4.5 V tdis disable time OE to Qn; see Figure 16 tt transition time Qn; see Figure 14 pulse width SI HIGH or LOW; see Figure 6 [3] VCC = 4.5 V tW ns [1] [4] VCC = 4.5 V VCC = 4.5 V SO HIGH or LOW; see Figure 9 VCC = 4.5 V DIR HIGH; see Figure 7 VCC = 4.5 V DOR HIGH; see Figure 10 VCC = 4.5 V MR LOW; see Figure 8 VCC = 4.5 V 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 11 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state Table 6. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17. Symbol Parameter 25 C Conditions trec recovery time MR to SI; see Figure 15 tsu set-up time Dn to SI; see Figure 13 VCC = 4.5 V VCC = 4.5 V th hold time Dn to SI; see Figure 13 fmax maximum frequency SI, SO burst mode; see Figure 11 and Figure 12 VCC = 4.5 V VCC = 4.5 V VCC = 5 V; CL = 15 pF 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 18 10 - 23 - 27 - ns 5 16 - 4 - 4 - ns 30 18 - 38 - 45 - ns 18 30 - 14 - 12 - MHz - 30 - - - - - MHz 18 30 - 14 - 12 - MHz - 30 - - - - - MHz - 23 - - - - - MHz - 490 - - - - - pF SI, SO using flags; see Figure 6 and Figure 9 VCC = 4.5 V VCC = 5 V; CL = 15 pF SI, SO cascaded; see Figure 6 and Figure 9 VCC = 4.5 V CPD power dissipation capacitance VI = GND to VCC  1.5 V [1] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] This is the ripple through delay. [6] This is the bubble-up delay. [7] [7] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 12 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state 12. Waveforms VWZRUG I PD[  W3+/ W3/+ WKZRUG 90 90  6,,1387 QGZRUG  WZ   ',5287387   'Q,1387 PJD Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. Shifting in sequence FIFO empty to FIFO full (1) DIR initially HIGH; FIFO is prepared for valid data (2) SI set HIGH; data loaded into input stage (3) DIR goes LOW; input stage “busy” (4) SI set LOW; data from first location “ripple through” (5) DIR goes HIGH; status flag indicates FIFO prepared for additional data (6) Repeat process to load 2nd word through to 64th word into FIFO; DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs. Fig 6. Propagation delay SI input to DIR output, the SI pulse width and the SI maximum frequency 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 13 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state  62,1387 6,,1387  90 90 W3/+  W: EXEEOHXS GHOD\ 90 ',5287387   PJD Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. With FIFO full; SI held HIGH in anticipation of empty location (1) FIFO is initially full, shift-in is held HIGH (2) SO pulse; data in output stage is unloaded, “bubble-up” process of empty location begins (3) DIR HIGH; when empty location reaches input stage, flag indicates that FIFO is prepared for data input (4) DIR returns to LOW; data returns to LOW; data shift-in to empty location is complete, FIFO is full again (5) SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full Fig 7. Bubble-up delay SO input to DIR output and the DIR pulse width. 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 14 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state 05,1387  90 W3/+ W: 90 ',5287387   W3+/  90 '25287387 W3+/ 4Q287387  PJD Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. Master reset applied with FIFO full (1) DIR LOW; output ready HIGH; assume that FIFO is full (2) MR pulse LOW; clears FIFO (3) DIR goes HIGH; flag indicates input prepared for valid data (4) DOR goes LOW; flag indicates FIFO empty (5) Qn outputs go LOW (only last bit is reset) Fig 8. Propagation delay MR input to DIR output, DOR output and Qn outputs and the MR pulse width. 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 15 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state VW62SXOVH QG62SXOVH WK62SXOVH I PD[ 90  62,1387 90  W3+/ W3/+  W:   90 '25287387   4Q287387 VWZRUG QGZRUG WKZRUG PJD Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. (1) DOR HIGH; no data transfer in progress, valid data is present at the output stage (2) SO set HIGH; result in DOR going LOW (3) DOR goes LOW; output stage “busy” (4) SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input stage (5) DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay (6) Repeat process to unload the 3rd through the 64th word from FIFO (7) DOR remains LOW; FIFO is empty Fig 9. Propagation delay SO input to DOR output, the SO pulse width and the SO maximum frequency. 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 16 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state 6,,1387 62,1387   90 90  W3/+ W: ULSSOHWKURXJK GHOD\ '25287387  90  W3+/W3/+  4Q287387 PJD Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. With FIFO empty; SO is held HIGH in anticipation (1) FIFO is initially empty. SO is held HIGH. (2) SI pulse; loads data into FIFO and initiates ripple through process (3) DOR flag signals the arrival of valid data at the output stage (4) Output transition; data arrives at output stage after the specified propagation delay between the rising and falling edge of the DOR pulse to the Qn output (5) DOR goes LOW; data shift-out is completed, FIFO is empty again (6) SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty Fig 10. Ripple through delay SI input to DOR output, propagation delay DOR input to Qn outputs and the DOR pulse width IPD[ W: 90 6,,1387 'Q,1387 ',5287387 PJD Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. Shift-in operation; high speed burst mode In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications. The DIR status flag is a “don’t care” condition, and a shift-in pulse can be applied regardless of the flag. An SI pulse which would overflow the storage capacity of the FIFO is ignored. Fig 11. Shift-in (SI) pulse width and maximum frequency (SI) 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 17 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state I  PD[ W: 90 62,1387 4Q287387 '25287387 PJD Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. Shift-out operation; high speed burst mode In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW specifications. The DOR flag is a “don’t care” condition, and an SO pulse can be applied without regard to the flag. Fig 12. Shift-in (SO) pulse width and maximum frequency (SO) 'Q,1387 90 WVX WVX WK WK 90 6,,1387 PJD Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the output is permitted to change for predictable output performance Fig 13. Set-up and hold times 62,1387 90 W3/+ W3+/   90 4Q287387  W7/+  W7+/ PJD Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. Fig 14. Propagation delay shift-out input (SO) to data outputs (Qn) and output transition time 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 18 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state 90 05,1387 WUHF 90 6,,1387 PJD Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. Fig 15. Master-reset (MR) to shift-in (SI) recovery time VI OE input VM GND tPLZ tPZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY Qn output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled 001aah078 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. Fig 16. Enable and disable times Table 7. Measurement points Type Input Output VM VM VX VY 74HC7403-Q100 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT7403-Q100 1.3 V 1.3 V 0.1VCC 0.9VCC 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 19 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 8. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 17. Test circuit for measuring switching times Table 8. Test data Type Input VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC7403-Q100 VCC 6 ns 15 pF, 50 pF 1 k open GND VCC 74HCT7403-Q100 3 V 6 ns 15 pF, 50 pF 1 k open GND VCC 74HC_HCT7403_Q100 Product data sheet Load S1 position All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 20 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state 13. Application information 2( '25 6, 6, 2( '25 6, ' 4 ' ' 4 ' 4 ' 4 '  ' ' ',5 05 62 2( '25 4 4  4 4 ',5 05 62 ELW GDWD ELW GDWD 6, 2( '25 ' '  ' ' ',5 05 6, 4 ' 4 ' 4 ' 4 ' 62 2( '25 4 4  ',5 05 4 4 62 ',5 62 05 PJD Fig 18. Expanded FIFO (parallel and serial) for increased word length; 8 bits wide x 64 n-bits  '$7$,1387 &20326,7( ',5 )/$* 'Q ',5 6,  '$7$287387 '25  62 62 05 2( 2( ',5 '25 6, 05 4Q 6, &20326,7( '25 )/$* 62  '$7$,1387  05 2( 'Q 4Q  '$7$287387 PJD The 74HC7403-Q100; 74HCT7403-Q100 is easily expanded to increase word length. Composite DIR and DIR flags are formed with the addition of an AND gate. The basic operation and timing are identical to a single FIFO, with the exception of an added gate delay on the flags. Fig 19. Expanded FIFO for increased word length; 64 words x 10 bits 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 21 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state  ',5 4 FRPSRVLWH ',5  ' 6, &3 4Q 'Q  '25  05 ' 62  4 ' ' ',5 &3 4 5 FRPSRVLWH '25 &3 2( 4 4 4 6, '25 &3 62 62 05 2( 2( 'Q 4Q 6,  05  4  5 4 PJD This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in cycles are started or if the SO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are started (see Figure 7 and Figure 10). Fig 20. Expanded FIFO for increased word length 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 22 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state 13.1 Expanded format Figure 21 shows two cascaded FIFOs providing a capacity of 128 words x 4 bits. Figure 22 shows the signals on the nodes of both FIFOs after the application of the SI pulse, when both FIFOs are initially empty. After a ripple through delay, data arrives at the output of FIFOA. Due to SOA being HIGH, a DORA pulse is generated. The requirements od SIB and DnB are satisfied by the DORA pulse width and the timing between the rising edge of DORA and QnA. After a second ripple through delay data arrives at the output of FIFOB. Figure 23 shows the signals on the nodes of both FIFOs after the application of the SOB pulse, when both FIFOs are initially full. After a bubble-up delay, a DIRB pulse is generated, which acts as a SOA pulse for FIFOA. One word is transferred from the output of FIFOA to the input of FIFOB. The requirements of the SOA pulse for FIFOA is satisfied by the pulse width of DORB. After a second bubble-up delay an empty space arrives at DnA, at which time DIRA goes HIGH. Figure 24 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence. 6,% '25$ 62$ 6, '$7$,1387  6,$ ',5$ ',5  ),)2$  'Q% 62 62%  4Q$ '25 '25% ',5% ),)2% 4Q%  '$7$287387 'Q$ 05 2( 05 2( 05 PJD 2( The 74HC7403-Q100; 74HCT7403-Q100 is easily cascaded to increase word capacity without external circuitry. In cascaded format, all necessary communications are handled by the FIFOs. Figure 22 and Figure 23 demonstrate the communication timing between FIFOA and FIFOB. Figure 24 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and shifted empty again. Fig 21. Cascading for increased word capacity; 128 words x 4 bits 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 23 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state ',5$ 90 6,$ 90  ULSSOHWKURXJK GHOD\ '25$6,% ',5%62$ 4Q$'Q%  90   90   ULSSOHWKURXJK GHOD\ '25%  90 4Q% PJD (1) FIFOA and FIFOB are initially empty, SOA held HIGH in anticipation of data (2) Load one word into FIFOA; SI pulse; applied. results in DIR pulse (3) Data-out A/ data-in B transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag, meeting data input set-up requirements of FIFOB. (4) DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data output ready pulse, data is shifted into FIFOB (5) DIRB and SOA go LOW; flag indicates that input stage of FIFOB is busy, shift-out of FIFOA is complete (6) DIRB and SOA go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in anticipation of additional data (7) DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB output stage Fig 22. FIFO to FIFO communication; input timing under empty condition 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 24 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state 90 '25% 62% 90  EXEEOHXS GHOD\ ',5%62$ '25$6,%   90  90  4Q$'Q% EXEEOHXS GHOD\ ',5$  90 PJD (1) FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up (2) Unload one word from FIFOB; SO pulse applied, results in DOR pulse (3) DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse, data is shifted out of FIFOA (4) DORA and SIB go LOW; flag indicates that the output stage of FIFOA is busy, shift-in of FIFOB is complete (5) DORA and SIB go HIGH; flag indicates that valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting bubble-up of empty location. (6) DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA Fig 23. FIFO to FIFO communication; output timing under full condition 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 25 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state VHTXHQFH VHTXHQFH VHTXHQFH VHTXHQFH VHTXHQFH VHTXHQFH  62%,1387    '25%287387 4Q%287387  ',5%287387   '25$287387    4Q$287387   ',5$287387  6,$,1387  'Q$,1387 05,1387 PJD See also Section 13.1.1 Fig 24. Waveforms showing the functionality and intercommunication between two FIFOs (refer to Figure 19) 13.1.1 Sequence 1 (both FIFOs empty, starting SHIFT-IN process) After an MR pulse has been applied, FIFOA and FIFOB are empty. The DOR flags of FIFOA and FIFOB go LOW due to no valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SOB is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through the output stage of FIFOA and the input stage of FIFIB (2). When data arrives at the output of FIFOB, a DORB pulse is generated (3). When SOB goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes high (4). 13.1.2 Sequence 2 (FIFOB runs full) After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIRB remains LOW due to FIFOB being full (5). DORA goes LOW due to FIFOA being empty. 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 26 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state 13.1.3 Sequence 3 (FIFOA runs full) When 65 words are shifted in, DORA remains HIGH due to valid data remaining at the output of FIFOA. QnA remains HIGH, being the polarity of the 65th word (6). After the 128th SI pulse, DIR remains LOW and both FIFOs are full (7). Additional pulses have no effect. 13.1.4 Sequence 4 (both FIFOs full, starting SHIFT-OUT) SIA is held HIGH and two SOB pulses are applied (8). These pulses shift out two words and thus allow two empty locations to bubble-up to the input stage of FIFOB, and proceed to FIFOA (9). When the first empty location arrives at the input of FIFOA, a DIRA pulse is generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH (11). 13.1.5 Sequence 5 (FIFOA runs empty) At the start of sequence 5, FIFOA contains 63 valid words due to two words being shifted out and one word being shifted in, in sequence 4. And additional series of SOB pulses are applied. After 63 SOB pulses, all words from FIFOA are shifted in FIFOB. DORA remains LOW (12). 13.1.6 Sequence 6 (FIFOB runs empty) After the next SOB pulse, DIRB remains HIGH due to the input stage of FIFOB being empty. After another 63 SOB pulses, DORB remains LOW due to both FIFOS being empty (14). Additional SOB pulses have no effect. The last word remains available at the output Qn. 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 27 of 32 74HC7403-Q100; 74HCT7403-Q100 NXP Semiconductors 4-bit x 64-word FIFO register; 3-state 14. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 25. Package outline SOT109-1 (SO16) 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 28 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state 15. Abbreviations Table 9. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic FIFO First In First Out MIL Military 16. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT7403_Q100 v.1 20120921 Product data sheet - - 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 29 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT7403_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 30 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT7403_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 September 2012 © NXP B.V. 2012. All rights reserved. 31 of 32 NXP Semiconductors 74HC7403-Q100; 74HCT7403-Q100 4-bit x 64-word FIFO register; 3-state 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 8 9 10 11 12 13 13.1 13.1.1 13.1.2 13.1.3 13.1.4 13.1.5 13.1.6 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Expanded format . . . . . . . . . . . . . . . . . . . . . . . 5 Parallel expension . . . . . . . . . . . . . . . . . . . . . . 5 Serial expension . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 21 Expanded format . . . . . . . . . . . . . . . . . . . . . . 23 Sequence 1 (both FIFOs empty, starting SHIFT-IN process) . . . . . . . . . . . . . . . . . . . . . 26 Sequence 2 (FIFOB runs full) . . . . . . . . . . . . . 26 Sequence 3 (FIFOA runs full) . . . . . . . . . . . . . 27 Sequence 4 (both FIFOs full, starting SHIFT-OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Sequence 5 (FIFOA runs empty) . . . . . . . . . . 27 Sequence 6 (FIFOB runs empty) . . . . . . . . . . 27 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 28 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Contact information. . . . . . . . . . . . . . . . . . . . . 31 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 September 2012 Document identifier: 74HC_HCT7403_Q100