74LV00D,112

74LV00 Quad 2-input NAND gate Rev. 5 — 10 September 2021 Product data sheet 1. General description The 74LV00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. 2. Features and benefits • • • • • • • • • • • Wide supply voltage range from 1.0 to 5.5 V CMOS low power dissipation Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C Complies with JEDEC standards: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • JESD36 (4.5 V to 5.5 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV00D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LV00PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LV00BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT762-1 74LV00 Nexperia Quad 2-input NAND gate 4. Functional diagram 1 1 1A 2 1B 1Y 3 4 2A 5 2B 2Y 6 9 3A 10 3B 3Y 8 12 4A 13 4B 2 4 5 9 10 12 4Y 11 13 mna212 Fig. 1. & 3 & 6 & 8 & 11 A Y B mna246 Logic symbol Fig. 2. IEC logic symbol Fig. 3. mna211 Logic diagram (one gate) 5. Pinning information 5.1. Pinning 1 1A terminal 1 index area 2 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y 2A 4 11 4Y 2B 5 2Y 6 VCC(1) 13 4B 10 3B 9 3A 001aah092 Transparent top view (1) This is not a supply pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to VCC aaa-033972 Fig. 4. 12 4A 8 1B 14 VCC 13 4B 1Y 3 3Y 1 2 7 1A 1B GND 74LV00 14 VCC 74LV00 Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 74LV00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 September 2021 © Nexperia B.V. 2021. All rights reserved 2 / 12 74LV00 Nexperia Quad 2-input NAND gate 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care Output Input nA nB nY L X H X L H H H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Max Unit VCC supply voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] -0.5 +7.0 V - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±50 mA IO output current VO = -0.5 V to (VCC + 0.5 V) - ±25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] Conditions Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate [1] Conditions [1] Min Typ Max Unit 1.0 3.3 5.5 V 0 - VCC V 0 - VCC V -40 +25 +125 °C VCC = 1.0 V to 2.0 V - - 500 ns/V VCC = 2.0 V to 2.7 V - - 200 ns/V VCC = 2.7 V to 3.6 V - - 100 ns/V VCC = 3.6 V to 5.5 V - - 50 ns/V The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 74LV00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 September 2021 © Nexperia B.V. 2021. All rights reserved 3 / 12 74LV00 Nexperia Quad 2-input NAND gate 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VOL -40 °C to +125 °C Unit Typ[1] Max Min Max VCC = 1.2 V 0.9 - - 0.9 - V VCC = 2.0 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.2 V - - 0.3 - 0.3 V VCC = 2.0 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V - 1.2 - - - V IO = -100 μA; VCC = 2.0 V 1.8 2.0 - 1.8 - V IO = -100 μA; VCC = 2.7 V 2.5 2.7 - 2.5 - V IO = -100 μA; VCC = 3.0 V 2.8 3.0 - 2.8 - V IO = -100 μA; VCC = 4.5 V 4.3 4.5 - 4.3 - V IO = -6 mA; VCC = 3.0 V 2.4 2.82 - 2.2 - V IO = -12 mA; VCC = 4.5 V 3.6 4.2 - 3.5 - V VI = VIH or VIL LOW-level output voltage IO = 100 μA; VCC = 1.2 V - 0 - - - V IO = 100 μA; VCC = 2.0 V - 0 0.2 - 0.2 V IO = 100 μA; VCC = 2.7 V - 0 0.2 - 0.2 V IO = 100 μA; VCC = 3.0 V - 0 0.2 - 0.2 V IO = 100 μA; VCC = 4.5 V - 0 0.2 - 0.2 V IO = 6 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V IO = 12 mA; VCC = 4.5 V - 0.35 0.55 - 0.65 V - - 1.0 - 1.0 μA LOW-level input voltage VOH -40 °C to +85 °C Min HIGH-level input voltage VIL Conditions VI = VIH or VIL HIGH-level output voltage IO = -100 μA; VCC = 1.2 V II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 20.0 - 40 μA ΔICC additional per input; VI = VCC - 0.6 V; supply current VCC = 2.7 V to 3.6 V - - 500 - 850 μA CI input capacitance - 3.5 - - - pF [1] VI = VCC or GND; VCC = 5.5 V Typical values are measured at Tamb = 25 °C. 74LV00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 September 2021 © Nexperia B.V. 2021. All rights reserved 4 / 12 74LV00 Nexperia Quad 2-input NAND gate 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Fig. 7. Symbol Parameter tpd propagation delay CPD [1] [2] [3] [4] Conditions power dissipation capacitance -40 °C to +85 °C Min Typ[1] VCC = 1.2 V - VCC = 2.0 V - VCC = 2.7 V nA, nB to nY; see Fig. 6 -40 °C to +125 °C Unit Max Min Max 45 - - - ns 15 26 - 31 ns - 11 18 - 23 ns [2] VCC = 3.0 V to 3.6 V; CL = 15 pF [3] - 7 - - - ns VCC = 3.0 V to 3.6 V [3] - 9.0 15 - 18 ns VCC = 4.5 V to 5.5 V [3] - 6.5 11 - 14 ns CL = 50 pF; fi = 1 MHz; VI = GND to VCC [4] - 22 - - - pF All typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL. Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz, fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching 2 Σ(CL x VCC x fo) = sum of the outputs. 10.1. Waveform and test circuit VI VM nA, nB input GND tPLH tPHL VOH VM nY output VOL 001aah088 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 6. The input (nA, nB) to output (nY) propagation delays Table 8. Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V ≥ 4.5 V 0.5VCC 0.5VCC 74LV00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 September 2021 © Nexperia B.V. 2021. All rights reserved 5 / 12 74LV00 Nexperia Quad 2-input NAND gate VCC PULSE GENERATOR VI VO DUT RT CL 50 pF RL 1 kΩ 001aaa663 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig. 7. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf < 2.7 V VCC ≤ 2.5 ns 2.7 V to 3.6 V 2.7 V ≤ 2.5 ns ≥ 4.5 V VCC ≤ 2.5 ns 74LV00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 September 2021 © Nexperia B.V. 2021. All rights reserved 6 / 12 74LV00 Nexperia Quad 2-input NAND gate 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74LV00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 September 2021 © Nexperia B.V. 2021. All rights reserved 7 / 12 74LV00 Nexperia Quad 2-input NAND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 Fig. 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Package outline SOT402-1 (TSSOP14) 74LV00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 September 2021 © Nexperia B.V. 2021. All rights reserved 8 / 12 74LV00 Nexperia Quad 2-input NAND gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm B D SOT762-1 A A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e v w b 2 6 C A B C y y1 C L 1 7 14 8 Eh e k 13 9 Dh X k 0 2 Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 1 A1 b 0.05 0.30 0.02 0.25 0.00 0.18 4 mm scale c D(1) Dh E(1) Eh e e1 0.2 3.1 3.0 2.9 1.65 1.50 1.35 2.6 2.5 2.4 1.15 1.00 0.85 0.5 2 k L v 0.2 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT762-1 References IEC JEDEC JEITA sot762-1_po European projection Issue date 15-04-10 15-05-05 MO-241 Fig. 10. Package outline SOT762-1 (DHVQFN14) 74LV00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 September 2021 © Nexperia B.V. 2021. All rights reserved 9 / 12 74LV00 Nexperia Quad 2-input NAND gate 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV00 v.5 20210910 Product data sheet - 74LV00 v.4 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74LV00DB (SOT337-1/SSOP14) removed. Section 1 and Section 2 updated. Section 7: Derating values for Ptot total power dissipation have been updated. 74LV00 v.4 20151209 Modifications: • 74LV00 v.3 20071220 Modifications: • • • • • Product data sheet - 74LV00 v.3 - 74LV00 v.2 Type number 74LV00N (SOT27-1) removed. Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN14 package added. Section 7: derating values added for DHVQFN14 package. Section 11: outline drawing added for DHVQFN14 package. 74LV00 v.2 19980420 Product specification - 74LV00 v.1 74LV00 v.1 19970203 Product specification - - 74LV00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 September 2021 © Nexperia B.V. 2021. All rights reserved 10 / 12 74LV00 Nexperia Quad 2-input NAND gate 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 September 2021 © Nexperia B.V. 2021. All rights reserved 11 / 12 74LV00 Nexperia Quad 2-input NAND gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................2 5.1. Pinning.........................................................................2 5.2. Pin description............................................................. 2 6. Functional description................................................. 3 7. Limiting values............................................................. 3 8. Recommended operating conditions..........................3 9. Static characteristics....................................................4 10. Dynamic characteristics............................................ 5 10.1. Waveform and test circuit.......................................... 5 11. Package outline.......................................................... 7 12. Abbreviations............................................................ 10 13. Revision history........................................................10 14. Legal information......................................................11 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 10 September 2021 74LV00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 September 2021 © Nexperia B.V. 2021. All rights reserved 12 / 12