74LV03D,112

INTEGRATED CIRCUITS 74LV03 Quad 2-input NAND gate Product data Supersedes data of 1998 Apr 20 
   2003 Mar 03 Philips Semiconductors Product data Quad 2-input NAND gate 74LV03 FEATURES DESCRIPTION • Wide operating voltage: 1.0 V to 5.5 V • Optimized for Low Voltage applications: 1.0 V to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V @ VCC = 3.3 V, The 74LV03 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT03. The 74LV03 provides the 2-input NAND function. The 74LV03 has open-drain N-transistor outputs, which are not clamped by a diode connected to VCC. In the OFF-state, i.e., when one input is LOW, the output may be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, these devices must have a pull-up resistor to establish a logic HIGH level. Tamb = 25 °C • Typical VOHV (output VOH undershoot) > 2 V @ VCC = 3.3 V, Tamb = 25 °C • Level shifter capability • Output capability: standard • ICC category: SSI (open drain) QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr =tf ≤ 2.5 ns PARAMETER SYMBOL CONDITIONS tPZL/tPLZ Propagation delay nA, nB to nY CL = 15 pF VCC = 3.3 V CI Input capacitance CPD Power dissipation capacitance per gate Notes 1, 2 TYPICAL UNIT 8 ns 3.5 pF 4 pF NOTES: 1 CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi × N +Σ (CL × VCC2 × fo) where: N = the number of outputs switching; fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. 2 The condition is VI = GND to VCC 3 The given value of CPD is obtained with : CL = 0 pF and RL = ∞ ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE PKG. DWG. # –40 °C to +125 °C 74LV03D SOT108-1 14-Pin Plastic SO PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER FUNCTION 1 14 VCC 1, 4, 9, 12 1A to 4A Data inputs 1B 2 13 4B 2, 5, 10, 13 1B to 4B Data inputs 1Y 3 12 4A 3, 6, 8, 11 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y SV00354 2003 Mar 03 SYMBOL 1A 2 1Y to 4Y Data outputs 7 GND Ground (0 V) 14 VCC Positive supply voltage Philips Semiconductors Product data Quad 2-input NAND gate 74LV03 LOGIC SYMBOL 1 LOGIC SYMBOL (IEEE/IEC) 2 1B 4 2A 5 2B 9 3A 3 1Y 3 2Y 6 3B 12 4A & 6 5 & 9 8 8 10 4Y 13 2 4 3Y 10 & 1 1A & 12 11 11 4B 13 SV00356 SV00355 LOGIC DIAGRAM FUNCTION TABLE INPUTS Y A nA nB nY L L Z L H Z H L Z H H L NOTES: H = HIGH voltage level L = LOW voltage level Z = High impedance OFF-state GND B SV00357 70 2003 Mar 03 3 OUTPUT Philips Semiconductors Product data Quad 2-input NAND gate 74LV03 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER DC supply voltage VI Input voltage VO Output voltage Tamb tr, tf Operating ambient temperature range in free air CONDITIONS MIN TYP. MAX UNIT See Note1 1.0 0 3.3 5.5 V – VCC V 0 – VCC V +85 +125 °C ns/V See DC and AC characteristics –40 –40 VCC = 1.0 V to 2.0 V – – 500 VCC = 2.0 V to 2.7 V – – 200 VCC = 2.7 V to 3.6 V – – 100 VCC = 3.6 V to 5.5 V – – 50 Input rise and fall times NOTES: 1 The LV is guaranteed to function down to VCC = 1.0 V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER VCC DC supply voltage CONDITIONS RATING UNIT –0.5 to +7.0 V ±IIK DC input diode current VI < –0.5 or VI > VCC + 0.5 V 20 mA ±IOK DC output diode current VO < –0.5 or VO > VCC + 0.5 V 50 mA ±IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5 V 25 ±IGND, ±ICC Tstg PTOT DC VCC or GND current for types with –standard outputs 50 Storage temperature range Power dissipation per package –plastic mini-pack (SO) for temperature range: –40 °C to +125 °C above +70 °C derate linearly with 8 mW/K mA mA –65 to +150 °C 500 mW NOTES: 1 Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2003 Mar 03 4 Philips Semiconductors Product data Quad 2-input NAND gate 74LV03 DC CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0 V) LIMITS SYMBOL PARAMETER –40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage TYP1 VOH VOL HIGH level output voltage; g STANDARD outputs LOW level output voltage all outputs out uts voltage; MIN 0.9 0.9 VCC = 2.0 V 1.4 1.4 VCC = 2.7 V to 3.6 V 2.0 2.0 VCC = 4.5 V to 5.5 V 0.7*VCC UNIT MAX V 0.7*VCC VCC = 1.2 V 0.3 0.3 VCC = 2.0 V 0.6 0.6 VCC = 2.7 V to 3.6 V 0.8 0.8 0.3*VCC 0.3*VCC VCC = 1.2 V; VI = VIH or VIL; –IO = 100 µA HIGH level output voltage out uts voltage; all outputs MAX VCC = 1.2 V VCC = 4.5 V to 5.5 V VOH –40°C to +125°C V 1.2 VCC = 2.0 V; VI = VIH or VIL; –IO = 100 µA 1.8 2.0 1.8 VCC = 2.7 V; VI = VIH or VIL; –IO = 100 µA 2.5 2.7 2.5 VCC = 3.0 V; VI = VIH or VIL; –IO = 100 µA 2.8 3.0 2.8 VCC = 4.5 V; VI = VIH or VIL; –IO = 100 µA 4.3 4.5 4.3 VCC = 3.0 V; VI = VIH or VIL; –IO = 6 mA 2.40 2.82 2.20 VCC = 4.5 V;VI = VIH or VIL; –IO = 12 mA 3.60 4.20 3.50 V V VCC = 1.2 V; VI = VIH or VIL; IO = 100 µA 0 VCC = 2.0 V; VI = VIH or VIL; IO = 100 µA 0 0.2 0.2 VCC = 2.7 V; VI = VIH or VIL; IO = 100 µA 0 0.2 0.2 VCC = 3.0 V; VI = VIH or VIL; IO = 100 µA 0 0.2 0.2 VCC = 4.5 V; VI = VIH or VIL; IO = 100 µA 0 0.2 0.2 V LOW level output voltage; g STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; IO = 6 mA 0.25 0.40 0.50 VCC = 4.5 V; VI = VIH or VIL; IO = 12 mA 0.35 0.55 0.65 IOZ HIGH level output leakage current VCC = 2.0 V to 3.6 V; VI = VIL; VO = VCC or GND 5.0 10 µA IOZ HIGH level output leakage current VCC = 2.0 V to 3.6 V; VI = VIL; VO = 6.0 V2 10 20 µA Input leakage current VCC = 5.5 V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; SSI VCC = 5.5 V; VI = VCC or GND; IO = 0 20.0 40 µA ∆ICC Additional quiescent supply current per input VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 500 850 µA VOL II V NOTES: 1 All typical values are measured at Tamb = 25 °C. 2 The maximum operating output voltage (VO(max)) is 6.0 V. 2003 Mar 03 5 Philips Semiconductors Product data Quad 2-input NAND gate 74LV03 AC CHARACTERISTICS FOR 74LV03 GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 kΩ SYMBOL PARAMETER Propagation delay nA, nB, to nY tPZL/tPLZ LIMITS –40 to +85 °C CONDITION WAVEFORM LIMITS –40 to +125 °C VCC (V) MIN TYP1 MAX MIN MAX 1.2 – 50 – – – 2.0 – 17 26 – 31 2.7 – 13 19 – 23 3.0 to 3.6 – 102 16 – 19 4.5 to 5.5 – –3 13 – 16 Figures, 1, 2 UNIT ns NOTE: 1 Unless otherwise stated, all typical values are at Tamb = 25 °C. 2 Typical value measured at VCC = 3.3 V. 3 Typical value measured at VCC = 5.0 V. AC WAVEFORMS TEST CIRCUIT VM = 1.5 V at VCC ≥ 2.7 V ≤ 3.6 V VM = 0.5 V * VCC at VCC < 2.7 V and ≥ 4.5 V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3 V at VCC ≥ 2.7 V and ≤ 3.6 V VX = VOL + 0.1 * VCC at VCC < 2.7 V and ≥ 4.5 V VCC 2 * VCC Open GND RL = 1k VO VI PULSE GENERATOR D.U.T. RT CL RL = 1k 50 pF Test Circuit for Outputs DEFINITIONS VI nA, nB INPUT RL = Load resistor CL = Load capacitance includes jig and probe capacitiance. RT = Termination resistance should be equal to ZOUT of pulse generators. VM SWITCH POSITION VCC tPLZ tPZL S1 VCC tPLH/tPHL Open < 2.7V VCC tPLZ/tPZL 2 * VCC 2.7–3.6V 2.7V tPHZ/tPZH GND TEST VI GND nY OUTPUT VOL VM VX w 4.5V VCC SV00896 Figure 2. Load circuitry for switching times SV00358 Figure 1. Input (nA, nB) to output (nY) propagation delays. 2003 Mar 03 6 Philips Semiconductors Product data Quad 2-input NAND gate 74LV03 REVISION HISTORY Rev Date Description _3 20030303 Product data (9397 750 11191). ECN 853-1963 29494 of 07 February 2003. Supersedes data of 1998 Apr 20 (9397 750 04403). Modifications: • Delete DIL, SSOP and TSSOP package ordering and package outlines (discontinued options). • Correct power dissipation formula. _2 19980420 Product specification (9397 750 04403). ECN 853-1963 19257 of 20 April 1998. Supersedes data of 1997 Mar 28. Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.  Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 03-03 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 
   2003 Mar 03 7 9397 750 11191 Philips Semiconductors - PIP - 74LV03; Quad 2-input NAND gate Submit Que Philips Semiconductors Home ProductBuy MySemiconductors ContactProduct Information catalogonline 74LV03; Quad 2input NAND gate Products MultiMarket • Semiconductors • Product Selector Catalog by • Function Catalog by • System • Cross-reference • Packages End of Life • information Distributors Go • Here! • Models • SoC solutions General description Features Block diagram Products & packages Buy online Parametrics Information as of 2003-04-22 My.Semiconductors.COM. Your personal service from Use right mouse button to Philips Semiconductors. download datasheet Please register now ! Download datasheet Stay informed Applications Support & tools Similar products Datasheet Email/translate General description top The 74LV03 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT03. The 74LV03 provides the 2-input NAND function. The 74LV03 has open-drain N-transistor outputs, which are not clamped by a diode connected to VCC . In the OFF-state, i.e., when one input is LOW, the output may be pulled to any voltage between GND and VOmax . This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, these devices must have a pull-up resistor to establish a logic HIGH level. Features top ● ● ● ● ● ● ● ● Wide operating voltage: 1.0 V to 5.5 V Optimized for Low Voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V @ VCC = 3.3 V, Tamb = 25 Cel Typical VOHV (output VOH undershoot) > 2 V @ VCC = 3.3 V, Tamb = 25 Cel Level shifter capability Output capability: standard (open drain) ICC category: SSI file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74LV03D.html (1 of 3) [May-08-2003 6:04:08 PM] Philips Semiconductors - PIP - 74LV03; Quad 2-input NAND gate Datasheet top Type number Title Publication release date Datasheet status Page count File size (kB) Datasheet 74LV03 3/3/2003 Product specification 7 58 Download Download PDF File Quad 2input NAND gate Parametrics top Type number Package Description Propagation Voltage No. Power Logic Output Delay(ns) of Dissipation Switching Drive Pins Considerations Levels Capability Quad 2Input SOT108- NAND Gate 74LV03D 15 1 (SO14) with Level Shift Capability Low 14 Low Power or Battery Applications TTL Low Products, packages, availability and ordering top Type number North Ordering code American (12NC) type number 74LV03D 74LV03D 74LV03DT Marking/Packing Package Device status Buy online IC packing info Download PDF File Standard Marking * SOT108-1 Full production order this (SO14) Tube product Standard Marking * SOT108-1 Full production online 9351 758 20118 Reel Pack, SMD, order this (SO14) 13" product online 9351 758 20112 - Similar products top 74LV03 links to the similar products page containing an overview of products that are similar in Products function similar or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category. to 74LV03 file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74LV03D.html (2 of 3) [May-08-2003 6:04:08 PM] Philips Semiconductors - PIP - 74LV03; Quad 2-input NAND gate Email/translate this product information top ● ● Email this product information. Translate this product information page from English to: French Translate The English language is the official language used at the semiconductors.philips.com website and webpages. All translations on this website are created through the use of Google Language Tools and are provided for convenience purposes only. No rights can be derived from any translation on this website. About this Web Site | Copyright © 2003 Koninklijke Philips N.V. All rights reserved. | Privacy Policy | | Koninklijke Philips N.V. | Access to and use of this Web Site is subject to the following Terms of Use. | file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74LV03D.html (3 of 3) [May-08-2003 6:04:08 PM]