74LV273DB,112

INTEGRATED CIRCUITS 74LV273 Octal D-type flip-flop with reset; positive-edge trigger Product specification Supersedes data of 1997 Apr 07 IC24 Data Handbook
     1998 May 29 Philips Semiconductors Product specification 74LV273 Octal D-type flip-flop with reset; positive edge-trigger FEATURES DESCRIPTION • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce)  0.8V @ VCC = 3.3V, The 74LV273 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT273. The 74LV273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. Tamb = 25°C • Typical VOHV (output VOH undershoot)  2V @ VCC = 3.3V, Tamb = 25°C All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. • Ideal buffer for MOS microprocessor or memory • Common clock and master reset • Output capability: standard • ICC category: MSI The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf 2.5 ns PARAMETER SYMBOL tPHL/tPLH Propagation delay CP to Qn; MR to Qn fmax Maximum clock frequency CI Input capacitance CPD Power dissipation capacitance per flip-flop CONDITIONS CL = 15pF VCC = 3.3V Notes 1 and 2 TYPICAL UNIT 12 13 ns 110 MHz 3.5 pF 20 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD
VCC2 x fi 
(CL
VCC2
fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V;
(CL
VCC2
fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic DIL –40°C to +125°C 74LV273 N 74LV273 N SOT146-1 20-Pin Plastic SO –40°C to +125°C 74LV273 D 74LV273 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +125°C 74LV273 DB 74LV273 DB SOT339-1 20-Pin Plastic TSSOP –40°C to +125°C 74LV273 PW 74LV273PW DH SOT360-1 1998 May 29 2 853–1965 19466 Philips Semiconductors Product specification 74LV273 Octal D-type flip-flop with reset; positive edge-trigger PIN CONFIGURATION LOGIC SYMBOL 11 MR 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 CP 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 13 D4 Q4 12 Q2 6 15 Q5 D2 7 14 D5 14 D5 Q5 15 D6 Q6 16 D7 Q7 19 D3 8 13 D4 17 Q3 9 12 Q4 18 11 CP GND 10 MR 1 SV00366 SV00367 PIN DESCRIPTION PIN NUMBER 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 LOGIC SYMBOL (IEEE/IEC) SYMBOL MR Q0 to Q7 FUNCTION Master reset input (active-LOW) Flip-flop outputs D0 to D7 Data inputs GND Ground (0V) CP VCC Clock input (LOW-to-HIGH, edgetriggered) Positive supply voltage 11 C1 1 R 3 1D 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 SV00368 1998 May 29 3 Philips Semiconductors Product specification 74LV273 Octal D-type flip-flop with reset; positive edge-trigger FUNCTIONAL DIAGRAM FUNCTION TABLE INPUTS OPERATING MODES 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 13 D4 Q4 12 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 1 MR 11 CP FF0 to FF7 H h L l ↑ X OUTPUTS MR CP Dn Q0 to Q7 Reset (clear) L X X L Load (‘1’) H ↑ h H Load (‘0’) H ↑ l L = HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW–to–HIGH clock transition = Don’t care SV00369 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP. MAX UNIT See Note1 1.0 3.3 5.5 V DC supply voltage VI Input voltage 0 – VCC V VO Output voltage 0 – VCC V +85 +125 °C 500 200 100 50 ns/V Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V –40 –40 – – – – – – – NOTES: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. 1998 May 29 4 Philips Semiconductors Product specification 74LV273 Octal D-type flip-flop with reset; positive edge-trigger ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) PARAMETER SYMBOL VCC DC supply voltage ±IIK DC input diode current ±IOK ±IO ±IGND, ±ICC Tstg PTOT CONDITIONS RATING UNIT –0.5 to +7.0 V VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 DC VCC or GND current for types with –standard outputs mA mA 50 Storage temperature range °C –65 to +150 Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC CHARACTERISTICS FOR THE LV FAMILY Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage TYP1 HIGH level output voltage; g STANDARD outputs LOW level output voltage all outputs out uts voltage; VOL LOW level output voltage; g STANDARD outputs 1998 May 29 MIN 0.9 0.9 VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*VCC UNIT MAX V 0.7*VCC VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 0.3*VCC 0.3*VCC VCC = 1.2V; VI = VIH or VIL; –IO = 100µA VOH MAX VCC = 1.2V VCC = 4.5 to 5.5 HIGH level output voltage out uts voltage; all outputs -40°C to +125°C V 1.2 VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 4.5V;VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3 VCC = 3.0V;VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 VCC = 4.5V;VI = VIH or VIL; –IO = 12mA 3.60 4.20 3.50 V V VCC = 1.2V; VI = VIH or VIL; IO = 100µA VCC = 2.0V; VI = VIH or VIL; IO = 100µA 0 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 4.5V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50 VCC = 4.5V;VI = VIH or VIL; IO = 12mA 0.35 0.55 0.65 V V 5 Philips Semiconductors Product specification 74LV273 Octal D-type flip-flop with reset; positive edge-trigger DC CHARACTERISTICS FOR THE LV FAMILY (Continued) Over recommended operating conditions voltages are referenced to GND (ground = 0V) SYMBOL PARAMETER LIMITS TEST CONDITIONS -40°C to +85°C -40°C to +125°C UNIT Input leakage current VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; MSI VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 µA ∆ICC Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA II NOTE: 1. All typical values are measured at Tamb = 25°C. AC CHARACTERISTICS GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL tPHL/tPLH tPHL tW tW trem tsu th fmax PARAMETER Propagation delay CP to Qn Propagation delay MR to Qn Clock pulse width HIGH or LOW Master reset pulse width LOW Removal time MR to CP Set-up time Dn to CP Hold time Dn to CP Maximum clock pulse ulse frequency WAVEFORM VCC(V) MIN TYP1 1.2 – 2.0 – LIMITS –40 to +125 °C MAX MIN 75 – – – 26 32 – 41 2.7 – 19 24 – 30 – 142 19 – 24 4.5 to 5.5 – – 16 – 20 1.2 – 80 – – – 2.0 – 27 44 – 56 2.7 – 20 33 – 41 3.0 to 3.6 – 152 26 – 33 4.5 to 5.5 – – 22 – 28 2.0 34 9 – 41 – 2.7 25 6 – 30 – 3.0 to 3.6 20 52 – 24 – 2.0 34 10 – 41 – Figure 2 Figure 1 2.7 25 8 – 30 – 3.0 to 3.6 20 62 – 24 – 1.2 – –10 – – – 2.0 5 –4 – 5 – 2.7 5 –3 – 5 – 3.0 to 3.6 5 –22 – 5 – 1.2 – 20 – – – 2.0 22 7 – 26 – 2.7 16 5 – 19 – 3.0 to 3.6 13 42 – 15 – 1.2 – –10 – – – 2.0 5 –4 – 5 – 2.7 5 –3 – 5 – 3.0 to 3.6 5 –22 – 5 – 2.0 14 40 – 12 – 2.7 19 75 – 16 – 24 1002 – 20 – Figure 2 Figure 2 Figure 3 Figure 3 Figure 1 NOTE: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. 6 UNIT MAX 3.0 to 3.6 Figure 1 3.0 to 3.6 1998 May 29 LIMITS –40 to +85 °C CONDITION ns ns ns ns ns ns ns MHz Philips Semiconductors Product specification 74LV273 Octal D-type flip-flop with reset; positive edge-trigger AC WAVEFORMS VM = 1.5V at VCC  2.7V  3.6V VM = 0.5V * VCC at VCC
2.7V and  4.5V VOL and VOH are the typical output voltage drop that occur with the output load. VI CP INPUT GND VM ÌÌÌÌ ÌÌÌÌÌÌ ÌÌ ÌÌÌÌ ÌÌÌÌÌÌ ÌÌ ÌÌÌÌ ÌÌÌÌÌÌÌÌ t su t su th VI 1/fMAX Dn INPUT VI CP INPUT GND VM GND VM VOH tw tPHL tPLH Qn OUTPUT VOH Qn OUTPUT th VM VOL VM VOL SV00371 Figure 3. Data set-up and hold times for the data input (Dn) NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SV00370 Figure 1. The clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency TEST CIRCUIT Vcc VO Vl PULSE GENERATOR VI MR INPUT D.U.T. VM VM 50pF RT CL RL= 1k GND tw VI trem CP INPUT Test Circuit for Outputs VM DEFINITIONS GND VOH Qn OUTPUT RL = Load resistor tPHL CL = Load capacitance includes jig and probe capacitiance RT = Termination resistance should be equal to ZOUT of pulse generators. VM VOL TEST tPLH/tPHL SV00372 VI < 2.7V VCC 2.7–3.6V 2.7V ≥ 4.5 V VCC SV00902 Figure 4. Figure 2. The master reset (MR) pulse width, the master reset to output (Qn) propagations delay and the master reset to clock (CP) removal time 1998 May 29 VCC 7 Load circuitry for switching times Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger DIP20: plastic dual in-line package; 20 leads (300 mil) 1998 May 29 8 74LV273 SOT146-1 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger SO20: plastic small outline package; 20 leads; body width 7.5 mm 1998 May 29 9 74LV273 SOT163-1 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1998 May 29 10 74LV273 SOT339-1 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1998 May 29 11 74LV273 SOT360-1 Philips Semiconductors Product specification Octal D–type flip–flop with reset; positive edge–trigger 74LV273 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number:
     1997 Apr 07 12 Date of release: 05-96 9397-750-04443