74LV4020N

74LV4020 14-stage binary ripple counter Rev. 01 — 29 November 2005 Product data sheet 1. General description The 74LV4020 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HCT4020. The 74LV4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 fully buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. 2. Features s Optimized for low-voltage applications: 1.0 V to 5.5 V s Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V s Typical LOW-level output voltage (peak) or output ground bounce: VOL(p) < 0.8 V at VCC = 3.3 V and Tamb = 25 °C s Typical HIGH-level output voltage (valley) or output VOH undershoot: VOH(v) > 2 V at VCC = 3.3 V and Tamb = 25 °C s ESD protection: x HBM EIA/JESD22-A114-C exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from −40 °C to +80 °C and from −40 °C to +125 °C. 3. Applications s Frequency dividing circuits s Time delay circuits s Control counters Philips Semiconductors 74LV4020 14-stage binary ripple counter 4. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 2.5 ns. Symbol Parameter tPHL, tPLH propagation delay CP to Q0 Qn to Q(n+1) tPHL fmax Ci CPD [1] Conditions CL = 15 pF; VCC = 3.3 V Min - Typ 12 7 16 100 3.5 20 Max - Unit ns ns ns MHz pF pF propagation delay MR to Qn maximum input clock frequency input capacitance power dissipation capacitance CL = 15 pF; VCC = 3.3 V CL = 15 pF; VCC = 3.3 V per gate; VI = GND to VCC [1] - CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 5. Ordering information Table 2: Ordering information Package Temperature range 74LV4020N 74LV4020D 74LV4020DB 74LV4020PW −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name DIP16 SO16 SSOP16 TSSOP16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT38-4 SOT109-1 SOT338-1 SOT403-1 Type number 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 2 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter 6. Functional diagram CP MR 10 11 T 14-STAGE COUNTER CD 9 7 5 4 6 13 12 14 15 1 2 3 Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad722 Fig 1. Functional diagram CTR14 Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 9 7 5 4 6 13 12 14 15 1 2 3 10 11 + CT 0 9 7 5 4 6 13 12 14 15 1 2 3 10 CP CT 11 MR 13 001aad723 001aad724 Fig 2. Logic symbol Fig 3. IEC logic symbol CP FF T0 Q FF T1 Q FF T2 Q FF T3 Q FF T4 Q FF T5 Q FF T6 Q Q RD MR RD Q RD Q RD Q RD Q RD Q RD Q Q0 Q3 Q4 Q5 Q6 FF T7 Q FF T8 Q FF T9 Q FF T 10 Q FF T 11 Q FF T 12 Q FF T 13 Q Q RD RD Q RD Q RD Q RD Q RD Q RD Q Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad725 Fig 4. Logic diagram 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 3 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter 7. Pinning information 7.1 Pinning Q11 Q12 Q13 Q5 Q4 Q6 Q3 GND 1 2 3 4 16 VCC 15 Q10 14 Q9 13 Q7 4020 5 6 7 8 001aad721 12 Q8 11 MR 10 CP 9 Q0 Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16 7.2 Pin description Table 3: Symbol Q11 Q12 Q13 Q5 Q4 Q6 Q3 GND Q0 CP MR Q8 Q7 Q9 Q10 VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description parallel output 11 parallel output 12 parallel output 13 parallel output 5 parallel output 4 parallel output 6 parallel output 3 ground (0 V) parallel output 0 clock input (HIGH-to-LOW, edge-triggered) master reset input (active HIGH) parallel output 8 parallel output 7 parallel output 9 parallel output 10 supply voltage 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 4 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter 8. Functional description 8.1 Function table Table 4: Input CP ↑ ↓ X [1] Function table [1] Output MR L L H Q0, Q3 to Q13 no change count L H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition. 8.1.1 Timing diagram 1 CP input MR input Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad726 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 Fig 6. Timing diagram 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 5 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter 9. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current quiescent supply current ground current storage temperature total power dissipation DIP16 package SO16 package SSOP16 and TSSOP16 packages [1] [2] [3] Above Tamb = 70 °C: Ptot derates linearly with 12 mW/K. Above Tamb = 70 °C: Ptot derates linearly with 8 mW/K. Above Tamb = 60 °C: Ptot derates linearly with 5.5 mW/K. Conditions VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to VCC + 0.5 V Min −0.5 −65 Max +7 ±20 ±50 ±25 50 −50 +150 750 500 400 Unit V mA mA mA mA mA °C mW mW mW Tamb = −40 °C to +125 °C [1] [2] [3] - 10. Recommended operating conditions Table 6: Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and VCC = 1.0 V to 2.0 V fall rate VCC = 2.0 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 5.5 V [1] Conditions [1] Min 1.0 0 0 −40 - Typ 3.3 - Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V °C ns/V ns/V ns/V ns/V The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 6 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter 11. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 VIH °C [1] VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-state input voltage VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-state output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.2 V IO = −100 µA; VCC = 2.0 V IO = −100 µA; VCC = 2.7 V IO = −100 µA; VCC = 3.0 V IO = −100 µA; VCC = 4.5 V IO = −6 mA; VCC = 3.0 V IO = −12 mA; VCC = 4.5 V VOL LOW-state output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.2 V IO = 100 µA; VCC = 2.0 V IO = 100 µA; VCC = 2.7 V IO = 100 µA; VCC = 3.0 V IO = 100 µA; VCC = 4.5 V IO = 6 mA; VCC = 3.0 V IO = 12 mA; VCC = 4.5 V ILI ICC ∆ICC Ci VIH input leakage current quiescent supply current additional quiescent supply current input capacitance HIGH-state input voltage VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per input; VI = VCC − 0.6 V; VCC = 2.7 V to 3.6 V 0.9 1.4 2.0 0 0 0 0 0 0.25 0.35 3.5 0.2 0.2 0.2 0.2 0.40 0.55 1.0 20.0 500 V V V V V V V µA µA µA pF V V V V 1.8 2.5 2.8 4.3 2.40 3.60 1.2 2.0 2.7 3.0 4.5 2.82 4.20 V V V V V V V 0.9 1.4 2.0 0.3 0.6 0.8 V V V V V V V HIGH-state input voltage Conditions Min Typ Max Unit 0.7 × VCC - 0.3 × VCC V Tamb = −40 °C to +125 °C 0.7 × VCC - 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 7 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL LOW-state input voltage Conditions VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-state output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.2 V IO = −100 µA; VCC = 2.0 V IO = −100 µA; VCC = 2.7 V IO = −100 µA; VCC = 3.0 V IO = −100 µA; VCC = 4.5 V IO = −6 mA; VCC = 3.0 V IO = −12 mA; VCC = 4.5 V VOL LOW-state output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.2 V IO = 100 µA; VCC = 2.0 V IO = 100 µA; VCC = 2.7 V IO = 100 µA; VCC = 3.0 V IO = 100 µA; VCC = 4.5 V IO = 6 mA; VCC = 3.0 V IO = 12 mA; VCC = 4.5 V ILI ICC ∆ICC input leakage current quiescent supply current additional quiescent supply current VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per input; VI = VCC − 0.6 V; VCC = 2.7 V to 3.6 V 0.2 0.2 0.2 0.2 0.50 0.65 1.0 160 850 V V V V V V V µA µA µA 1.8 2.5 2.8 4.3 2.20 3.50 V V V V V V V Min Typ Max 0.3 0.6 0.8 Unit V V V 0.3 × VCC V [1] All typical values are measured at Tamb = 25 °C. 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 8 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter 12. Dynamic characteristics Table 8: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF; for test circuit see Figure 9. Symbol Parameter Tamb = −40 °C to +85 tPHL, tPLH CP to Q0 °C [1] see Figure 7 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 3.3 V; CL = 15 pF Qn to Q(n+1) see Figure 7 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 3.3 V; CL = 15 pF tPHL propagation delay MR to Qn see Figure 8 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 3.3 V; CL = 15 pF tW pulse width CP (HIGH and LOW) see Figure 7 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V MR (HIGH) see Figure 8 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 35 25 20 15 11 9 8 7 ns ns ns ns 35 25 20 15 7 5 4 3 ns ns ns ns 55 27 19 16 11 16 44 31 26 17 ns ns ns ns ns ns 40 18 13 11 7 7 29 21 18 12 ns ns ns ns ns ns 60 27 19 16 11 12 43 31 26 17 ns ns ns ns ns ns propagation delay Conditions Min Typ Max Unit 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 9 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter Table 8: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF; for test circuit see Figure 9. Symbol Parameter trec recovery time MR to CP see Figure 8 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum input clock frequency see Figure 7 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 3.3 V; CL = 15 pF CPD tPHL, tPLH power dissipation capacitance propagation delay CP to Q0 see Figure 7 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V Qn to Q(n+1) see Figure 7 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tPHL propagation delay MR to Qn see Figure 8 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 55 39 32 22 ns ns ns ns ns 37 26 22 15 ns ns ns ns ns 54 38 32 22 ns ns ns ns ns per gate; VI = GND to VCC [2] Conditions Min Typ Max Unit 22 16 13 10 14 19 24 36 - 10 5 4 3 2 60 76 94 112 100 20 - ns ns ns ns ns MHz MHz MHz MHz MHz pF Tamb = −40 °C to +125 °C 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 10 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter Table 8: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF; for test circuit see Figure 9. Symbol Parameter tW pulse width CP (HIGH and LOW) see Figure 7 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V MR (HIGH) see Figure 8 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V trec recovery time MR to CP see Figure 8 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum input clock frequency see Figure 7 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V [1] [2] Typical values are measured at nominal VCC and Tamb = 25 °C. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. Conditions Min Typ Max Unit 41 30 24 18 41 30 24 18 - - ns ns ns ns ns ns ns ns 26 19 15 12 12 16 20 30 - - ns ns ns ns ns MHz MHz MHz MHz 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 11 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter 13. Waveforms 1/fmax VI input CP, Qn GND tW t PHL VOH output Q0, Q(n+1) VOL VM 001aad727 VM t PLH Measurement points: VM = 0.5 × VCC. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. Propagation delay clock (CP) to output (Qn), clock pulse width and maximum clock frequency VI MR input GND tW VI CP input GND t PHL VOH Qn output VOL VM 001aad728 VM t rec VM Measurement points: VM = 0.5 × VCC. VOL and VOH are typical output voltage drop that occur with the output load. Fig 8. Propagation delay master reset (MR) to output (Qn), pulse width master reset (MR) and removal time master reset (MR) to clock (CP) 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 12 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF RL 1 kΩ VO 001aaa663 Test data is given in Table 9. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 9. Load circuitry for switching times Table 9: VCC 1.2 V 2.0 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr, tf ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 50 pF 50 pF 50 pF 50 pF, 15 pF 50 pF RL 1 kΩ 1 kΩ 1 kΩ 1 kΩ 1 kΩ tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH Test Supply voltage 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 13 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter 14. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 10. Package outline SOT38-1 (DIP16) 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 14 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT109-1 (SO16) 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 15 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT338-1 (SSOP16) 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 16 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 13. Package outline SOT403-1 (TSSOP16) 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 17 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter 15. Abbreviations Table 10: Acronym CMOS TTL HBM ESD MM Abbreviations Description Complementary Metal Oxide Semiconductor Transistor Transistor Logic Human Body Model ElectroStatic Discharge Machine Model 16. Revision history Table 11: Revision history Release date 20051129 Data sheet status Product data sheet Change notice Doc. number Supersedes Document ID 74LV4020_1 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 18 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter 17. Data sheet status Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 20. Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 21. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 19 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.1.1 9 10 11 12 13 14 15 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 19 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 29 November 2005 Document number: 74LV4020_1 Published in The Netherlands