74LV4053N,112

74LV4053 Triple single-pole double-throw analog switch Rev. 5 — 18 September 2014 Product data sheet 1. General description The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all switches into the high-impedance OFF-state, independent of Sn. VCC and GND are the supply voltage connections for the digital control inputs (Sn and E). The VCC to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC  VEE may not exceed 6 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). VEE and VSS are the supply voltage connections for the switches. 2. Features and benefits  Optimized for low-voltage applications: 1.0 V to 3.6 V  Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  Low ON resistance:  180  (typical) at VCC  VEE = 2.0 V  100  (typical) at VCC  VEE = 3.0 V  75  (typical) at VCC  VEE = 4.5 V  Logic level translation:  To enable 3 V logic to communicate with 3 V analog signals  Typical ‘break before make’ built in  ESD protection:  HBM JESD22-A114-C exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 74LV4053 NXP Semiconductors Triple single-pole double-throw analog switch 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV4053N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74LV4053D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LV4053DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74LV4053PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74LV4053BQ 40 C to +125 C DHVQFN16 plastic dual-in line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm SOT763-1 4. Functional diagram E 6 VCC 16 13 1Y1 S1 11 LOGIC LEVEL CONVERSION 12 1Y0 DECODER 14 1Z 1 2Y1 S2 10 LOGIC LEVEL CONVERSION 2 2Y0 15 2Z 3 3Y1 S3 9 LOGIC LEVEL CONVERSION 5 3Y0 4 3Z 8 GND Fig 1. 7 VEE 001aak341 Functional diagram 74LV4053 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 27 74LV4053 NXP Semiconductors Triple single-pole double-throw analog switch   6