74LVC132A

74LVC132A Quad 2-input NAND Schmitt trigger Rev. 01 — 15 December 2006 Product data sheet 1. General description The 74LVC132A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the input hysteresis voltage VH. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environment. 2. Features s s s s s s s s Wide supply voltage range from 2.3 V to 3.6 V 5 V tolerant inputs for interfacing with 5 V logic CMOS low power consumption Direct interface with TTL levels Unlimited rise and fall times Inputs accept voltages up to 5.5 V Complies with JEDEC standard JESD8-B/JESD36 ESD protection: x HBM JESD22-A114-D exceeds 2000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Applications s Wave and pulse shaper s Astable multivibrator s Monostable multivibrator. NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 4. Ordering information Table 1. Ordering information Package Temperature range Name 74LVC132AD −40 °C to +125 °C SO14 TSSOP14 Description plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT108-1 SOT402-1 SOT762-1 Type number 74LVC132APW −40 °C to +125 °C 74LVC132ABQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 5. Functional diagram 1 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 2 4 2Y 6 5 9 10 12 13 mna212 & 3 & 6 3Y 8 & 8 A 4Y 11 & mna246 11 B Y 001aac532 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 2 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 6. Pinning information 6.1 Pinning 74LVC132A terminal 1 index area 14 VCC 13 4B 12 4A 11 4Y GND(1) 7 8 10 3B 9 GND 3Y 3A 1A 2 3 4 5 6 1 1B 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 001aaf590 74LVC132A 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 8 3A 3Y 2Y 1Y 2A 2B 001aaf591 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 6.2 Pin description Table 2. Symbol 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description data input data input data output data input data input data output ground (0 V) data output data input data input data output data input data input supply voltage 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 3 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 7. Functional description Table 3. Input nA L L H H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output nB L H L H nY H H H L 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions [1] [1] Min −0.5 −0.5 −0.5 −50 −100 −65 Max +6.5 +6.5 VCC + 0.5 ±50 ±50 100 +150 500 Unit V V V mA mA mA mA mA °C mW VI < 0 V VO > VCC or VO < 0 V VO = 0 V to VCC Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO14 packages: Ptot derates linearly with 8 mW/K above 70 °C. For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C. 9. Recommended operating conditions Table 5. Symbol VCC VI VO Tamb Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature Conditions Min 1.2 0 0 −40 Typ Max 3.6 5.5 VCC +125 Unit V V V °C 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 4 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 10. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 °C VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 3.6 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −18 mA; VCC = 3.0 V IO = −24 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 3.6 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V II ICC ∆ICC CI VOH input leakage current supply current additional supply current input capacitance HIGH-level output voltage VCC = 3.6 V; VI = 5.5 V or GND VCC = 3.6 V; VI = VCC or GND; IO = 0 A per input pin; VCC = 2.7 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A VCC = 0 V to 3.6 V; VI = GND to VCC VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 3.6 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −18 mA; VCC = 3.0 V IO = −24 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 3.6 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V II ICC ∆ICC input leakage current supply current additional supply current VCC = 3.6 V; VI = 5.5 V or GND VCC = 3.6 V; VI = VCC or GND; IO = 0 A per input pin; VCC = 2.7 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A 0.3 0.65 0.8 0.6 0.8 ±20 40 5 V V V V V µA µA mA VCC − 0.3 VCC − 0.6 V V V V V V ±0.1 0.1 5 4.0 0.2 0.45 0.6 0.4 0.55 ±5 10 500 V V V V V µA µA µA pF VCC − 0.2 VCC − 0.5 VCC − 0.5 VCC − 0.6 VCC − 0.8 V V V V V V VCC − 0.45 Conditions Min Typ[1] Max Unit Tamb = −40 °C to +125 °C VCC − 0.65 VCC − 0.65 VCC − 0.75 VCC − 1 - [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. © NXP B.V. 2006. All rights reserved. 74LVC132A_1 Product data sheet Rev. 01 — 15 December 2006 5 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter tpd propagation delay Conditions nA, nB to nY; see Figure 6 VCC = 1.2 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tsk(o) CPD output skew time power dissipation capacitance per buffer; VI = GND to VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] [3] [4] [3] [4] [2] −40 °C to +85 °C Min 2.0 1.5 1.5 1.5 Typ[1] 18.0 7.2 4.0 3.8 3.4 10.5 10.8 11.4 Max 12.8 7.6 7.6 6.4 1.0 - −40 °C to +125 °C Unit Min 2.0 1.5 1.5 1.5 Max 16.0 9.6 9.6 8.0 1.5 ns ns ns ns ns ns pF pF pF Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. tpd is the same as tPLH and tPHL. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 12. Waveforms nA, nB input VM tPHL tPLH nY output VM mna213 VM = 1.5 V at VCC ≥ 2.7 V. VM = 0.5 × VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drops that occur with the output load. Fig 6. The input (nA, nB) to output (nY) propagation delays 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 6 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC RL VM VI positive pulse 0V VM PULSE GENERATOR VI DUT RT VO CL RL 001aae331 Test data is given in Table 8. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Load circuitry for switching times Table 8. Test data Input VI 1.2 V 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V VCC VCC VCC 2.7 V 2.7 V tr, tf ≤ 2 ns ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 30 pF 50 pF 50 pF RL 1 kΩ 1 kΩ 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open tPLZ, tPZL 2 × VCC 2 × VCC 2 × VCC 2 × VCC 2 × VCC tPHZ, tPZH GND GND GND GND GND Supply voltage 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 7 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 13. Transfer characteristics Table 9. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol VT+ Parameter positive-going threshold voltage Conditions see Figure 8 and Figure 9 VCC = 1.2 V VCC = 1.65 V VCC = 1.95 V VCC = 2.3 V VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V VT− negative-going threshold voltage see Figure 8 and Figure 9 VCC = 1.2 V VCC = 1.65 V VCC = 1.95 V VCC = 2.3 V VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V VH hysteresis voltage (VT+ − VT−); see Figure 8, Figure 9 and Figure 10 VCC = 1.2 V VCC = 1.65 V VCC = 1.95 V VCC = 2.3 V VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 0.1 0.2 0.2 0.3 0.3 0.3 0.3 0.3 1.0 1.15 1.25 1.3 1.3 1.1 1.2 1.2 0.1 0.2 0.2 0.3 0.3 0.3 0.3 0.3 1.0 1.15 1.25 1.3 1.3 1.1 1.2 1.2 V V V V V V V V 0.12 0.15 0.25 0.4 0.4 0.8 0.8 0.8 0.75 0.85 0.95 1.1 1.2 1.4 1.5 1.5 0.12 0.15 0.25 0.4 0.4 0.8 0.8 0.8 0.75 0.85 0.95 1.1 1.2 1.4 1.5 1.5 V V V V V V V V 0.2 0.4 0.6 0.8 0.9 1.1 1.2 1.2 1.0 1.3 1.5 1.7 1.7 2 2 2 0.2 0.4 0.6 0.8 0.9 1.1 1.2 1.2 1.0 1.3 1.5 1.7 1.7 2 2 2 V V V V V V V V −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 8 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 14. Waveforms transfer characteristics VO VT+ VI VT− VH VH VT− VT+ VI mna207 VO mna208 Fig 8. Transfer characteristic Fig 9. Definition of VT+, VT− and VH 5 I CC (mA) 4 mna582 3 2 1 0 0 0.6 1.2 1.8 2.4 VI (V) 3 Fig 10. Typical transfer characteristic; VCC = 3.3 V 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 9 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 15. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index θ Lp 1 e bp 7 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT108-1 (SO14) 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 10 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Fig 12. Package outline SOT402-1 (TSSOP14) 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 11 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 vMCAB wM C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT762-1 (DHVQFN14) 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 12 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 16. Abbreviations Table 10. Acronym CDM CMOS DUT ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 17. Revision history Table 11. Revision history Release date 20061215 Data sheet status Product data sheet Change notice Supersedes Document ID 74LVC132A_1 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 13 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 14 of 15 NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Transfer characteristics. . . . . . . . . . . . . . . . . . . 8 Waveforms transfer characteristics . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 December 2006 Document identifier: 74LVC132A_1