74LVC1G02GM,132

74LVC1G02 Single 2-input NOR gate Rev. 11 — 29 June 2012 Product data sheet 1. General description The 74LVC1G02 provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits  Wide supply voltage range from 1.65 V to 5.5 V  High noise immunity  Complies with JEDEC standard:  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8-B/JESD36 (2.7 V to 3.6 V)  24 mA output drive (VCC = 3.0 V)  CMOS low power consumption  Latch-up performance exceeds 250 mA  Direct interface with TTL levels  Inputs accept voltages up to 5 V  Multiple package options  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Specified from 40 C to +85 C and 40 C to +125 C 74LVC1G02 NXP Semiconductors Single 2-input NOR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G02GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74LVC1G02GV 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753 74LVC1G02GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1  1.45  0.5 mm 74LVC1G02GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1  1  0.5 mm 74LVC1G02GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9  1.0  0.35 mm SOT1115 74LVC1G02GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0  1.0  0.35 mm SOT1202 74LVC1G02GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8  0.8  0.35 mm SOT1226 4. Marking Table 2. Marking Type number Marking code[1] 74LVC1G02GW VB 74LVC1G02GV V02 74LVC1G02GM VB 74LVC1G02GF VB 74LVC1G02GN VB 74LVC1G02GS VB 74LVC1G02GX VB [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram B 1 2 B Y A 1 4 ≥1 4 Y 2 A Fig 1. Logic symbol 74LVC1G02 Product data sheet mna105 mna104 mna103 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 Fig 3. Logic diagram © NXP B.V. 2012. All rights reserved. 2 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate 6. Pinning information 6.1 Pinning 74LVC1G02 74LVC1G02 B 1 A 2 GND 3 5 4 B 1 6 VCC A 2 5 n.c. GND 3 4 Y VCC Y 001aab611 Transparent top view 001aab610 Fig 4. Pin configuration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886 74LVC1G02 74LVC1G02 1 B B 1 6 VCC A 2 5 n.c. GND 3 4 Y VCC 4 Y 3 GND 2 A 001aaf052 aaa-003019 Transparent top view Transparent top view Fig 6. 5 Pin configuration SOT891, SOT1115 and SOT1202 Fig 7. Pin configuration SOT1226 (X2SON5) 6.2 Pin description Table 3. Symbol Pin description Pin Description TSSOP5 and X2SON5 XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 3 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate 7. Functional description Table 4. Function table[1] Inputs Outputs A B Y L L H L H L H L L H H L [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Conditions VI < 0 V [1] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V mA - 50 Active mode [1][2] 0.5 VCC + 0.5 V Power-down mode [1][2] 0.5 +6.5 V - 50 mA - +100 mA VO > VCC or VO < 0 V VO = 0 V to VCC Tamb = 40 C to +125 C [3] 100 - mA - 250 mW 65 +150 C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 and X2SON5 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 4 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 1.65 - 5.5 V VI input voltage 0 - 5.5 V VO output voltage Active mode 0 - VCC V VCC = 0 V; Power-down mode 0 - 5.5 V 40 - +125 C VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V Tamb ambient temperature t/V input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage 40 C to +85 C Conditions VCC = 1.65 V to 1.95 V Product data sheet Min Max Min Max 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.65 V to 1.95 V - - 0.35VCC - 0.35VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V VCC  0.1 - - VCC  0.1 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 0.95 - V IO = 8 mA; VCC = 2.3 V 1.9 - - 1.7 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 1.9 - V IO = 24 mA; VCC = 3.0 V 2.3 - - 2.0 - V IO = 32 mA; VCC = 4.5 V 3.8 - - 3.4 - V - - 0.1 - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.3 - 0.45 V LOW-level VI = VIH or VIL output voltage IO = 100 A; VCC = 1.65 V to 5.5 V 74LVC1G02 Unit VCC = 2.7 V to 3.6 V HIGH-level VI = VIH or VIL output voltage IO = 100 A; VCC = 1.65 V to 5.5 V input leakage current 40 C to +125 C Typ[1] IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.80 V - 0.1 5 - 100 A VI = 5.5 V or GND; VCC = 0 V to 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 5 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate Table 7. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Unit Min Max Min Max - 0.1 10 - 200 A IOFF power-off leakage current ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - 0.1 10 - 200 A ICC additional VCC = 2.3 V to 5.5 V; supply current VI = VCC  0.6 V; IO = 0 A; per pin - 5 500 - 5000 A CI input capacitance - 5 - - - pF [1] VCC = 0 V; VI or VO = 5.5 V 40 C to +125 C Typ[1] VCC = 3.3 V; VI = GND to VCC All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 9. Symbol Parameter tpd 40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 1.0 3.2 8.0 1.0 10.5 ns VCC = 2.3 V to 2.7 V 0.5 2.2 5.5 0.5 7.0 ns VCC = 2.7 V 0.5 2.5 5.5 0.5 7.0 ns VCC = 3.0 V to 3.6 V 0.5 2.1 4.5 0.5 6.0 ns 0.5 1.7 4.0 0.5 5.5 ns - 14 - - - pF propagation delay A, B to Y; see Figure 8 [2] VCC = 4.5 V to 5.5 V power dissipation capacitance CPD [1] 40 C to +125 C Unit Typ[1] VI = GND to VCC; VCC = 3.3 V [3] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 6 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate 12. Waveforms VI VM A, B input GND t PHL t PLH VOH VM Y output mna612 VOL Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output. Fig 8. Table 9. The input (A, B) to output (Y) propagation delay times Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5VCC 0.5VCC 2.3 V to 2.7 V 0.5VCC 0.5VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5VCC 0.5VCC VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Test circuit for measuring switching times 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 7 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate Table 10. Test data Supply voltage Input VCC VI tr = tf Load CL RL VEXT tPLH, tPHL 1.65 V to 1.95 V VCC  2.0 ns 30 pF 1 k open 2.3 V to 2.7 V VCC  2.0 ns 30 pF 500  open 2.7 V 2.7 V  2.5 ns 50 pF 500  open 3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  open 4.5 V to 5.5 V VCC  2.5 ns 50 pF 500  open 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 8 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 10. Package outline SOT353-1 (TSSOP5) 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 9 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate Plastic surface-mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT753 JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Fig 11. Package outline SOT753 (SC-74A) 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 10 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version SOT886 sot886_po References IEC JEDEC JEITA European projection Issue date 04-07-22 12-01-05 MO-252 Fig 12. Package outline SOT886 (XSON6) 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 11 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 e1 4 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 13. Package outline SOT891 (XSON6) 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 12 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1115_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1115 Fig 14. Package outline SOT1115 (XSON6) 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 13 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1202_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1202 Fig 15. Package outline SOT1202 (XSON6) 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 14 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 x 0.8 x 0.35 mm B A D SOT1226 X A E A1 A3 detail X terminal 1 index area e C v w b 1 2 terminal 1 index area C A B C y1 C y k D h 3 L 5 4 0 1 mm scale Dimensions Unit mm A(1) A1 A3 D Dh E b e k L max 0.35 0.04 0.128 0.85 0.30 0.85 0.27 0.27 nom 0.80 0.25 0.80 0.22 0.48 0.22 min 0.20 0.17 0.040 0.75 0.20 0.75 0.17 v 0.1 w y y1 0.05 0.05 0.05 Note 1. Dimension A is including plating thickness. 2. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version References IEC JEDEC EIAJ sot1226_po European projection Issue date 12-04-10 12-04-25 SOT1226 Fig 16. Package outline SOT1226 (X2SON5) 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 15 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G02 v.11 20120629 Product data sheet - 74LVC1G02 v.10 Modifications: 74LVC1G02 v.10 Modifications: 74LVC1G02 v.9 Modifications: • Added type number 74LVC1G02GX (SOT1226) 20120305 • - 74LVC1G02 v.9 Package outline drawing of SOT886 (Figure 12) modified. 20111209 • Product data sheet Product data sheet - 74LVC1G02 v.8 Legal pages updated. 74LVC1G02 v.8 20101020 Product data sheet - 74LVC1G02 v.7 74LVC1G02 v.7 20070718 Product data sheet - 74LVC1G02 v.6 74LVC1G02 v.6 20060914 Product data sheet - 74LVC1G02 v.5 74LVC1G02 v.5 20040907 Product specification - 74LVC1G02 v.4 74LVC1G02 v.4 20021002 Product specification - 74LVC1G02 v.3 74LVC1G02 v.3 20020515 Product specification - 74LVC1G02 v.2 74LVC1G02 v.2 20010411 Product specification - 74LVC1G02 v.1 74LVC1G02 v.1 20001114 Product specification - - 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 16 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC1G02 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 17 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 18 of 19 74LVC1G02 NXP Semiconductors Single 2-input NOR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 June 2012 Document identifier: 74LVC1G02