74LVC1G14

74LVC1G14 Single Schmitt-trigger inverter Rev. 07 — 18 July 2007 Product data sheet 1. General description The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger action. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at the input makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features s Wide supply voltage range from 1.65 V to 5.5 V s High noise immunity s Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V). s ±24 mA output drive (VCC = 3.0 V) s CMOS low power consumption s Latch-up performance exceeds 250 mA s Direct interface with TTL levels s Unlimited rise and fall times s Input accepts voltages up to 5 V s Multiple package options s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V. s Specified from −40 °C to +85 °C and −40 °C to +125 °C. 3. Applications s Wave and pulse shaper s Astable multivibrator s Monostable multivibrator NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 4. Ordering information Table 1. Ordering information Package Temperature range Name 74LVC1G14GW 74LVC1G14GV 74LVC1G14GM 74LVC1G14GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C TSSOP5 SC-74A XSON6 XSON6 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm plastic surface-mounted package; 5 leads Version SOT353-1 SOT753 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 5. Marking Table 2. Marking Marking code VF V14 VF VF Type number 74LVC1G14GW 74LVC1G14GV 74LVC1G14GM 74LVC1G14GF 6. Functional diagram 2 A Y 4 2 mna024 4 A Y mna025 mna023 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 2 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 7. Pinning information 7.1 Pinning 74LVC1G14 74LVC1G14 n.c. A 1 2 GND GND 3 001aab655 n.c. 5 VCC 1 6 VCC n.c. A 74LVC1G14 1 2 3 6 5 4 VCC n.c. Y A 2 5 n.c. 3 4 Y GND 4 Y 001aab656 001aae976 Transparent top view Transparent top view Fig 4. Pin configuration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891 7.2 Pin description Table 3. Symbol n.c. A GND Y n.c. VCC Pin description Pin SOT353-1/SOT753 1 2 3 4 5 SOT886/SOT891 1 2 3 4 5 6 not connected data input ground (0 V) data output not connected supply voltage Description 8. Functional description Table 4. Input A L H [1] H = HIGH voltage level; L = LOW voltage level Function table[1] Output Y H L 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 3 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions [1] Min −0.5 −0.5 −0.5 −0.5 −50 −100 −65 Max +6.5 +6.5 VCC + 0.5 +6.5 ±50 ±50 +100 +150 250 Unit V V V V mA mA mA mA mA °C mW Active mode Power-down mode VI < 0 V VO > VCC or VO < 0 V VO = 0 V to VCC [1][2] [1][2] Tamb = −40 °C to +125 °C [3] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 10. Recommended operating conditions Table 6. Symbol VCC VI VO Tamb Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature Active mode Power-down mode; VCC = 0 V Conditions Min 1.65 0 0 0 −40 Typ Max 5.5 5.5 VCC 5.5 +125 Unit V V V V °C 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 4 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VOH Parameter HIGH-level output voltage Conditions VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II IOFF input leakage current power-off leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI or VO = 5.5 V; VCC = 0 V 0.07 0.12 0.17 0.33 0.39 ±0.1 ±0.1 0.10 0.45 0.30 0.40 0.55 0.55 ±5 ±10 0.10 0.70 0.45 0.60 0.80 0.80 ±100 ±200 V V V V V V µA µA VCC − 0.1 1.2 1.9 2.2 2.3 3.8 1.54 2.15 2.50 2.62 4.11 VCC − 0.1 0.95 1.7 1.9 2.0 3.4 V V V V V V −40 °C to +85 °C Min Typ[1] Max −40 °C to +125 °C Min Max Unit ICC ∆ICC CI supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V additional VI = VCC − 0.6 V; IO = 0 A; supply current VCC = 2.3 V to 5.5 V input capacitance VCC = 3.3 V; VI = GND to VCC - 0.1 5 5.0 10 500 - - 200 5000 - µA µA pF [1] All typical values are measured at maximum VCC and Tamb = 25 °C. Table 8. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 8. Symbol Parameter VT+ positive-going threshold voltage Conditions see Figure 9 and Figure 10 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V 74LVC1G14_7 −40 °C to +85 °C Min 0.82 1.03 1.29 1.84 2.19 Typ[1] 1.0 1.2 1.5 2.1 2.5 Max 1.14 1.40 1.71 2.36 2.79 −40 °C to +125 °C Min 0.79 1.00 1.26 1.81 2.16 Max 1.14 1.40 1.71 2.36 2.79 Unit V V V V V © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 5 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter Table 8. Transfer characteristics …continued Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 8. Symbol Parameter VT− negative-going threshold voltage Conditions see Figure 9 and Figure 10 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V VH hysteresis voltage (VT+ − VT−); see Figure 9, Figure 10 and Figure 11 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V [1] All typical values are measured at Tamb = 25 °C −40 °C to +85 °C Min 0.46 0.65 0.88 1.32 1.58 Typ[1] 0.6 0.8 1.0 1.5 1.8 Max 0.75 0.96 1.24 1.84 2.24 −40 °C to +125 °C Min 0.46 0.65 0.88 1.32 1.58 Max 0.78 0.99 1.27 1.87 2.27 Unit V V V V V 0.26 0.28 0.31 0.40 0.47 0.4 0.4 0.5 0.6 0.6 0.51 0.57 0.64 0.77 0.88 0.19 0.22 0.25 0.34 0.41 0.51 0.57 0.64 0.77 0.88 V V V V V 12. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 8. Symbol Parameter tpd propagation delay Conditions A to Y; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance VCC = 3.3 V; VI = GND to VCC [3] [2] −40 °C to +85 °C Min 1.0 0.7 0.7 0.7 0.7 Typ[1] 4.1 2.8 3.2 3.0 2.2 15.4 Max 11.0 6.5 6.5 5.5 5.0 - −40 °C to +125 °C Unit Min 1.0 0.7 0.7 0.7 0.7 Max 14.0 8.5 8.5 7.0 6.5 ns ns ns ns ns pF [1] [2] [3] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V. 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 6 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 13. Waveforms VI A input GND t PHL VOH Y output VOL VM mna640 VM t PLH Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The data input (A) to output (Y) propagation delays Table 10. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Output VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Supply voltage VEXT VCC VI VO DUT RT CL RL RL G mna616 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuit for switching times 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 7 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter Table 11. VCC Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr = t f ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V 14. Waveforms transfer characteristics VO VT+ VI VT− VH VO VH VT− VT+ VI mna207 mna208 VT+ and VT− limits at 70 % and 20 %. Fig 9. Transfer characteristic Fig 10. Definition of VT+, VT− and VH mna641 10 ICC (mA) 8 6 4 2 0 0 1 2 VI (V) 3 VCC = 3.0 V. Fig 11. Typical transfer characteristics 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 8 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 15. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula: Padd = fi × (tr × ∆ICC(AV) + tf × ∆ICC(AV)) × VCC where: Padd = additional power dissipation (µW); fi = input frequency (MHz); tr = input rise time (ns); 10 % to 90 %; tf = input fall time (ns); 90 % to 10 %; ∆ICC(AV) = average additional supply current (µA). Average ∆ICC(AV) differs with positive or negative input transitions, as shown in Figure 12. An example of a relaxation circuit using the 74LVC1G14 is shown in Figure 13. 12 average I CC 10 (mA) 8 mna642 positive-going edge 6 4 negative-going edge 2 0 0 2 4 VCC (V) 6 Linear change of VI between 0.8 V to 2.0 V. All values given are typical unless otherwise specified. Fig 12. Average additional supply current as a function of supply voltage R C mna035 1 1 f = --- ≈ --------------------T 0.5 × RC Fig 13. Relaxation oscillator 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 9 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 16. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 D E A X c y HE vMA Z 5 4 A2 A1 (A3) θ A 1 e e1 bp 3 wM detail X Lp L 0 1.5 scale 3 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.1 0 A2 1.0 0.8 A3 0.15 bp 0.30 0.15 c 0.25 0.08 D(1) 2.25 1.85 E(1) 1.35 1.15 e 0.65 e1 1.3 HE 2.25 2.0 L 0.425 Lp 0.46 0.21 v 0.3 w 0.1 y 0.1 Z(1) 0.60 0.15 θ 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC MO-203 JEITA SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 14. Package outline SOT353-1 (TSSOP5) 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 10 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter Plastic surface-mounted package; 5 leads SOT753 D B E A X y HE vMA 5 4 Q A A1 c 1 2 3 detail X Lp e bp wM B 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.100 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT753 REFERENCES IEC JEDEC JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Fig 15. Package outline SOT753 (SC-74A) 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 11 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 16. Package outline SOT886 (XSON6) 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 12 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 4× (1) L1 e L 6 e1 5 e1 4 6× (1) A A1 D E terminal 1 index area 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 2 mm Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 Fig 17. Package outline SOT891 (XSON6) 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 13 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 17. Abbreviations Table 12. Acronym CMOS TTL HBM ESD MM DUT Abbreviations Description Complementary Metal Oxide Semiconductor Transistor-Transistor Logic Human Body Model ElectroStatic Discharge Machine Model Device Under Test 18. Revision history Table 13. Revision history Release date 20070718 Data sheet status Product data sheet Change notice Supersedes 74LVC1G14_6 Document ID 74LVC1G14_7 Modifications: • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 11 “Static characteristics”: Changed: Conditions for input leakage current and supply current. New package outline drawing for XSON6/SOT891. Product data sheet Product specification Product specification Product specification Product specification Product specification 74LVC1G14_5 74LVC1G14_4 74LVC1G14_3 74LVC1G14_2 74LVC1G14_1 - 74LVC1G14_6 74LVC1G14_5 74LVC1G14_4 74LVC1G14_3 74LVC1G14_2 74LVC1G14_1 20060615 20040910 20021119 20020521 20010406 20001212 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 14 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 19. Legal information 19.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 19.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVC1G14_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 18 July 2007 15 of 16 NXP Semiconductors 74LVC1G14 Single Schmitt-trigger inverter 21. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Waveforms transfer characteristics . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 July 2007 Document identifier: 74LVC1G14_7