74LVC2G14
Dual inverting Schmitt trigger with 5 V tolerant input
Rev. 7 — 30 November 2011
Product data sheet
1. General description
The 74LVC2G14 provides two inverting buffers with Schmitt-trigger input. It is capable of
transforming slowly changing input signals into sharply defined, jitter-free output signals.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at the inputs
makes the circuit tolerant of slower input rise and fall time. This device is fully specified for
partial power-down applications using IOFF. The IOFF circuitry disables the output,
preventing the damaging backflow current through the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Unlimited rise and fall times
Input accepts voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.
3. Applications
Wave and pulse shaper
Astable multivibrator
Monostable multivibrator
74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC2G14GW
40 C to +125 C
SC-88
plastic surface-mounted package; 6 leads
SOT363
74LVC2G14GV
40 C to +125 C
TSOP6
plastic surface-mounted package (TSOP6); 6 leads SOT457
74LVC2G14GM
40 C to +125 C
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1.45 0.5 mm
SOT886
74LVC2G14GF
40 C to +125 C
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1 0.5 mm
SOT891
74LVC2G14GN
40 C to +125 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
74LVC2G14GS
40 C to +125 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
SOT1202
5. Marking
Table 2.
Marking codes
Type number
Marking code[1]
74LVC2G14GW
VK
74LVC2G14GV
V14
74LVC2G14GM
VK
74LVC2G14GF
VK
74LVC2G14GN
VK
74LVC2G14GS
VK
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
1
3
1A
1Y
2A
2Y
mnb082
Fig 1. Logic symbol
74LVC2G14
Product data sheet
6
4
1
6
1A
3
4
2A
1Y
2Y
mnb083
Fig 2. IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 30 November 2011
mnb084
Fig 3. Logic diagram
© NXP B.V. 2011. All rights reserved.
2 of 20
74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
7. Pinning information
7.1 Pinning
74LVC2G14
74LVC2G14
1A
1
6
1A
1
6
1Y
GND
2
5
VCC
74LVC2G14
1Y
GND
2
5
VCC
2A
3
4
2Y
2A
4
1
6
1Y
GND
2
5
VCC
2A
3
4
2Y
2Y
001aaf957
001aab673
Transparent top view
Transparent top view
001aab672
Fig 4. Pin configuration SOT363
and SOT457
3
1A
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891,
SOT1115 and SOT1202
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
1A
1
data input
GND
2
ground (0 V)
2A
3
data input
2Y
4
data output
VCC
5
supply voltage
1Y
6
data input
8. Functional description
Table 4.
Function table[1]
Input
Output
nA
nY
L
H
H
L
[1]
H = HIGH voltage level;
L = LOW voltage level.
74LVC2G14
Product data sheet
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Rev. 7 — 30 November 2011
© NXP B.V. 2011. All rights reserved.
3 of 20
74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
output voltage
VO
IO
output current
ICC
supply current
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
Conditions
VI < 0 V
[1]
Min
Max
Unit
0.5
+6.5
V
50
-
mA
0.5
+6.5
V
-
50
mA
Active mode
[1][2]
0.5
VCC + 0.5
V
Power-down mode
[1][2]
0.5
+6.5
V
-
50
mA
-
100
mA
100
-
mA
-
250
mW
65
+150
C
VO > VCC or VO < 0 V
VO = 0 V to VCC
Tamb = 40 C to +125 C
[3]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For SC-88 and TSOP6 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
10. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Parameter
VCC
Min
Typ
Max
Unit
supply voltage
1.65
-
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
Active mode
0
-
VCC
V
Power-down mode; VCC = 0 V
0
-
5.5
V
40
-
+125
C
Tamb
Conditions
ambient temperature
74LVC2G14
Product data sheet
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Rev. 7 — 30 November 2011
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74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = 40 C to +85 C
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
VI = VT+ or VT
IO = 100 A; VCC = 1.65 V to 5.5 V
VCC 0.1 -
-
V
IO = 4 mA; VCC = 1.65 V
1.2
-
-
V
IO = 8 mA; VCC = 2.3 V
1.9
-
-
V
IO = 12 mA; VCC = 2.7 V
2.2
-
-
V
IO = 24 mA; VCC = 3.0 V
2.3
-
-
V
IO = 32 mA; VCC = 4.5 V
3.8
-
-
V
VI = VT+ or VT
IO = 100 A; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
V
IO = 8 mA; VCC = 2.3 V
-
-
0.3
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
V
IO = 32 mA; VCC = 4.5 V
-
-
0.55
V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
-
0.1
5
A
IOFF
power-off leakage current
VI or VO = 5.5 V; VCC = 0 V
-
0.1
10
A
ICC
supply current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
-
0.1
10
A
ICC
additional supply current
VI = VCC 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
5
500
A
CI
input capacitance
VCC = 3.3 V; VI = GND to VCC
-
3.5
-
pF
Tamb = 40 C to +125 C
VOH
VOL
II
HIGH-level output voltage
LOW-level output voltage
input leakage current
74LVC2G14
Product data sheet
VI = VT+ or VT
IO = 100 A; VCC = 1.65 V to 5.5 V
VCC 0.1 -
-
V
IO = 4 mA; VCC = 1.65 V
0.95
-
-
V
IO = 8 mA; VCC = 2.3 V
1.7
-
-
V
IO = 12 mA; VCC = 2.7 V
1.9
-
-
V
IO = 24 mA; VCC = 3.0 V
2.0
-
-
V
IO = 32 mA; VCC = 4.5 V
3.4
-
-
V
IO = 100 A; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.7
V
VI = VT+ or VT
IO = 8 mA; VCC = 2.3 V
-
-
0.45
V
IO = 12 mA; VCC = 2.7 V
-
-
0.6
V
IO = 24 mA; VCC = 3.0 V
-
-
0.8
V
IO = 32 mA; VCC = 4.5 V
-
-
0.8
V
-
-
20
A
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
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74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
IOFF
power-off leakage current
VI or VO = 5.5 V; VCC = 0 V
-
-
20
A
ICC
supply current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
-
-
40
A
ICC
additional supply current
VI = VCC 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
-
5000
A
[1]
All typical values are measured at maximum VCC and Tamb = 25 C.
Table 8.
Transfer characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 8
Symbol Parameter
positive-going
threshold voltage
VT+
negative-going
threshold voltage
VT
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
VCC = 1.8 V
0.70
1.10
1.50
0.70
1.70
V
VCC = 2.3 V
1.00
1.40
1.80
1.00
2.00
V
VCC = 3.0 V
1.30
1.76
2.20
1.30
2.40
V
VCC = 4.5 V
1.90
2.47
3.10
1.90
3.30
V
VCC = 5.5 V
2.20
2.91
3.60
2.20
3.80
V
see Figure 9 and Figure 10
see Figure 9 and Figure 10
VCC = 1.8 V
0.25
0.61
0.90
0.25
1.10
V
VCC = 2.3 V
0.40
0.80
1.15
0.40
1.35
V
VCC = 3.0 V
0.60
1.04
1.50
0.60
1.70
V
VCC = 4.5 V
1.00
1.55
2.00
1.00
2.20
V
VCC = 5.5 V
1.20
1.86
2.30
1.20
2.50
V
VCC = 1.8 V
0.15
0.49
1.00
0.15
1.20
V
VCC = 2.3 V
0.25
0.60
1.10
0.25
1.30
V
VCC = 3.0 V
0.40
0.73
1.20
0.40
1.40
V
VCC = 4.5 V
0.60
0.92
1.50
0.60
1.70
V
VCC = 5.5 V
0.70
1.02
1.70
0.70
1.90
V
hysteresis voltage (VT+ VT); see Figure 9,
Figure 10 and Figure 11
VH
[1]
40 C to +85 C
Conditions
All typical values are measured at Tamb = 25 C
74LVC2G14
Product data sheet
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74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
12. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter
40 C to +85 C
Conditions
power dissipation
capacitance
CPD
Unit
Min
Max
Min
Max
VCC = 1.65 V to 1.95 V
1.0
5.6
11.0
1.0
12.0
ns
VCC = 2.3 V to 2.7 V
0.5
3.7
6.5
0.5
7.2
ns
VCC = 2.7 V
0.5
4.1
7.0
0.5
7.7
ns
VCC = 3.0 V to 3.6 V
0.5
3.9
6.0
0.5
6.7
ns
VCC = 4.5 V to 5.5 V
0.5
2.7
4.3
0.5
4.7
ns
-
18.1
-
-
-
pF
[2]
propagation delay nA to nY; see Figure 7
tpd
40 C to +125 C
Typ[1]
[3]
VI = GND to VCC; VCC = 3.3 V
[1]
Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2]
tpd is the same as tPLH and tPHL.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
13. Waveforms
VI
VM
nA input
VM
GND
t PHL
t PLH
VOH
VM
nY output
VOL
VM
mna344
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The data input (nA) to output (nY) propagation delays
74LVC2G14
Product data sheet
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74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
Table 10.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
1.65 V to 1.95 V
0.5 VCC
0.5 VCC
2.3 V to 2.7 V
0.5 VCC
0.5 VCC
2.7 V
1.5 V
1.5 V
3.0 V to 3.6 V
1.5 V
1.5 V
4.5 V to 5.5 V
0.5 VCC
0.5 VCC
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuitry for switching times
Table 11.
Test data
Supply voltage
Input
VCC
VI
tr = tf
CL
RL
tPLH, tPHL
1.65 V to 1.95 V
VCC
2.0 ns
30 pF
1 k
open
2.3 V to 2.7 V
VCC
2.0 ns
30 pF
500
open
2.7 V
2.7 V
2.5 ns
50 pF
500
open
3.0 V to 3.6 V
2.7 V
2.5 ns
50 pF
500
open
4.5 V to 5.5 V
VCC
2.5 ns
50 pF
500
open
74LVC2G14
Product data sheet
Load
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Rev. 7 — 30 November 2011
VEXT
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74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
14. Waveforms transfer characteristics
VT+
VO
VI
VH
VT−
VO
VI
VH
VT−
VT+
mna208
mna207
VT+ and VT limits at 70 % and 20 %.
Fig 9. Transfer characteristic
Fig 10. Definition of VT+, VT and VH
ICC
(mA)
mdb627
14
12
10
8
6
4
2
0
0
0.5
1
1.5
VI (V)
2
VCC = 3.0 V
Fig 11. Typical transfer characteristics
74LVC2G14
Product data sheet
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74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
15. Application information
The slow input rise and fall times cause additional power dissipation, which can be
calculated using the following formula:
Padd = fi (tr ICC(AV) + tf ICC(AV)) VCC where:
Padd = additional power dissipation (W);
fi = input frequency (MHz);
tr = input rise time (ns); 10 % to 90 %;
tf = input fall time (ns); 90 % to 10 %;
ICC(AV) = average additional supply current (A).
ICC(AV) differs with positive or negative input transitions, as shown in Figure 12.
An example of a relaxation circuit using the 74LVC2G14 is shown in Figure 13.
mnb086
50
ΔICC(AV)
(mA)
(1)
40
30
20
(2)
10
0
2
3
4
5
VCC (V)
6
Linear change of VI between 0.8 V to 2.0 V. All values given are typical unless otherwise specified.
(1) Positive-going edge.
(2) Negative-going edge.
Fig 12. Average ICC as a function of VCC
R
C
mna035
1
1
f = --- --------------------T 0.8 RC
Fig 13. Relaxation oscillator
74LVC2G14
Product data sheet
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NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
16. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
E
B
y
X
A
HE
6
5
v M A
4
Q
pin 1
index
A
A1
1
2
e1
3
bp
c
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT363
JEITA
SC-88
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
Fig 14. Package outline SOT363 (SC-88)
74LVC2G14
Product data sheet
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Rev. 7 — 30 November 2011
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11 of 20
74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
Plastic surface-mounted package (TSOP6); 6 leads
D
SOT457
E
B
y
A
HE
6
5
X
v M A
4
Q
pin 1
index
A
A1
c
1
2
3
Lp
bp
e
w M B
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
bp
c
D
E
e
HE
Lp
Q
v
w
y
mm
1.1
0.9
0.1
0.013
0.40
0.25
0.26
0.10
3.1
2.7
1.7
1.3
0.95
3.0
2.5
0.6
0.2
0.33
0.23
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT457
JEITA
SC-74
EUROPEAN
PROJECTION
ISSUE DATE
05-11-07
06-03-16
Fig 15. Package outline SOT457 (TSOP6)
74LVC2G14
Product data sheet
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Rev. 7 — 30 November 2011
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12 of 20
74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L1
e
6
5
e1
4
e1
6×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
1.5
1.4
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
OUTLINE
VERSION
SOT886
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-07-15
04-07-22
MO-252
Fig 16. Package outline SOT886 (XSON6)
74LVC2G14
Product data sheet
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Rev. 7 — 30 November 2011
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13 of 20
74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
1
SOT891
b
3
2
4×
(1)
L
L1
e
6
5
4
e1
e1
6×
A
(1)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.20
0.12
1.05
0.95
1.05
0.95
0.55
0.35
0.35
0.27
0.40
0.32
Note
1. Can be visible in some manufacturing processes.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-04-06
07-05-15
SOT891
Fig 17. Package outline SOT891 (XSON6)
74LVC2G14
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 30 November 2011
© NXP B.V. 2011. All rights reserved.
14 of 20
74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
1
SOT1115
b
3
2
(4×)(2)
L
L1
e
6
5
4
e1
e1
(6×)(2)
A1
A
D
E
terminal 1
index area
0
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
b
D
E
e
e1
max 0.35 0.04 0.20 0.95 1.05
nom
0.15 0.90 1.00 0.55
min
0.12 0.85 0.95
L
L1
0.35 0.40
0.30 0.35
0.27 0.32
0.3
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1115_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-07
SOT1115
Fig 18. Package outline SOT1115 (XSON6)
74LVC2G14
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 30 November 2011
© NXP B.V. 2011. All rights reserved.
15 of 20
74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
1
SOT1202
b
3
2
(4×)(2)
L
L1
e
6
5
4
e1
e1
(6×)(2)
A1
A
D
E
terminal 1
index area
0
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
b
D
E
e
e1
L
L1
max 0.35 0.04 0.20 1.05 1.05
0.35 0.40
nom
0.15 1.00 1.00 0.55 0.35 0.30 0.35
min
0.12 0.95 0.95
0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1202_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-06
SOT1202
Fig 19. Package outline SOT1202 (XSON6)
74LVC2G14
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 30 November 2011
© NXP B.V. 2011. All rights reserved.
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74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
17. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
TTL
Transistor-Transistor Logic
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
DUT
Device Under Test
18. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
74LVC2G14 v.7
20111130
Product data sheet
Modifications:
•
Change notice
Supersedes
74LVC2G14 v.6
Legal pages updated.
74LVC2G14 v.6
20110923
Product data sheet
74LVC2G14 v.5
74LVC2G14 v.5
20101029
Product data sheet
74LVC2G14 v.4
74LVC2G14 v.4
20070904
Product data sheet
74LVC2G14 v.3
74LVC2G14 v.3
20070220
Product data sheet
74LVC2G14 v.2
74LVC2G14 v.2
20040908
Product specification
74LVC2G14 v.1
20030731
Product specification
74LVC2G14
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 30 November 2011
74LVC2G14 v.1
-
© NXP B.V. 2011. All rights reserved.
17 of 20
74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
74LVC2G14
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 30 November 2011
© NXP B.V. 2011. All rights reserved.
18 of 20
74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC2G14
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 30 November 2011
© NXP B.V. 2011. All rights reserved.
19 of 20
74LVC2G14
NXP Semiconductors
Dual inverting Schmitt trigger with 5 V tolerant input
21. Contents
1
2
3
4
5
6
7
7.1
7.2
8
9
10
11
12
13
14
15
16
17
18
19
19.1
19.2
19.3
19.4
20
21
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Waveforms transfer characteristics. . . . . . . . . 9
Application information. . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 November 2011
Document identifier: 74LVC2G14