74LVC2GU04GW

74LVC2GU04 Dual inverter Rev. 05 — 27 October 2009 Product data sheet 1. General description The 74LVC2GU04 provides two inverters. Each inverter is a single stage with unbuffered output. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. 2. Features I I I I I I I I I Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Input accepts voltages up to 5 V Multiple package options ESD protection: N HBM JESD22-A114F exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range 74LVC2GU04GW 74LVC2GU04GV 74LVC2GU04GM 74LVC2GU04GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name SC-88 TSOP6 XSON6 XSON6 Description plastic surface-mounted package; 6 leads plastic surface-mounted package (TSOP6); 6 leads plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1 × 0.5 mm Version SOT363 SOT457 SOT886 SOT891 Type number NXP Semiconductors 74LVC2GU04 Dual inverter 4. Marking Table 2. Marking codes Marking[1] YD VU4 YD YD Type number 74LVC2GU04GW 74LVC2GU04GV 74LVC2GU04GM 74LVC2GU04GF [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram VCC 1 1 6 100 Ω 1 1A 1Y 6 VCC A 3 2A 2Y 4 3 1 4 Y mnb106 mnb107 mna636 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74LVC2GU04 74LVC2GU04 1A GND 1 2 6 5 1Y GND VCC 2A 2A 3 001aab680 1A 1 6 1Y 1A GND 74LVC2GU04 1 2 3 6 5 4 1Y VCC 2Y 2 5 VCC 3 4 2Y 2A 4 2Y 001aab681 001aag421 Transparent top view Transparent top view Fig 4. Pin configuration SOT363 and SOT457 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 2 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter 6.2 Pin description Table 3. Symbol 1A GND 2A 2Y VCC 1Y Pin description Pin 1 2 3 4 5 6 Description data input ground (0 V) data input data output supply voltage data output 7. Functional description Table 4. Input nA L H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output nY H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 −50 [1][2] Max +6.5 +6.5 VCC + 0.5 ±50 100 +150 250 Unit V mA V mA V mA mA mA °C mW VO < 0 V Active mode VO = 0 V to VCC −0.5 −100 −65 Tamb = −40 °C to +125 °C [3] - The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 3 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V Active mode Conditions Min 1.65 0 0 −40 Typ Max 5.5 5.5 VCC +125 20 10 Unit V V V °C ns/V ns/V 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 VIH VIL VOH °C[1] VCC = 1.65 V to 5.5 V VCC = 1.65 V to 5.5 V IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II ICC CI input leakage current supply current input capacitance VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V VCC = 3.3 V; VI = GND to VCC [2] Conditions Min 0.75 × VCC VCC − 0.1 1.2 1.9 2.2 2.3 3.8 - Typ ±0.1 0.1 5 Max 0.25 × VCC 0.1 0.45 0.3 0.4 0.55 0.55 ±5 10 - Unit V V V V V V V V V V V V V V µA µA pF HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 4 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage VCC = 1.65 V to 5.5 V VCC = 1.65 V to 5.5 V IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II ICC input leakage current supply current VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V 0.1 0.7 0.45 0.6 0.8 0.8 ±20 40 V V V V V V µA µA 0.8 × VCC VCC − 0.1 0.95 1.7 1.9 2.0 3.4 0.2 × VCC V V V V V V V V Conditions Min Typ Max Unit HIGH-level output voltage VI = VIH or VIL [1] [2] All typical values are measured at Tamb = 25 °C. These typical values are measured at VCC = 3.3 V. 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 5 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter tpd Conditions [2] −40 °C to +85 °C Min Typ[1] 2.3 1.8 2.6 2.3 1.7 7.8 Max 5.0 4.0 4.5 3.7 3.0 - −40 °C to +125 °C Unit Min 0.5 0.3 0.3 0.3 0.3 Max 6.3 5.0 5.6 4.5 3.8 ns ns ns ns ns pF propagation delay nA to nY; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 0.5 0.3 0.3 0.3 0.3 [3] CPD power dissipation capacitance VI = GND to VCC; VCC = 3.3 V - [1] [2] [3] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 12. Waveforms VI nA input GND t PHL VOH nY output VOL VM VM mna344 VM VM t PLH Measurement points are given in Table 9. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The input (nA) to output (nY) propagation delay times 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 6 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter Table 9. VCC Measurement points Input VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC Output VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VEXT VCC VI VO DUT RT CL RL RL G mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Table 10. VCC Load circuitry for switching times Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr = t f ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 7 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter 160 gfs (mA/V) 120 mnb108 80 Rbias = 560 kΩ VCC 40 0.47 µF VI input output 100 µF 0 0 1 2 3 4 5 6 VCC (V) A IO mna638 Tamb = 25 °C. ∆I O g fs = --------∆V I fi = 1 kHz. VO is constant. Fig 9. Typical forward transconductance as a function of supply voltage Fig 10. Test set-up for measuring forward transconductance 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 8 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter 13. Application information Some applications are: • Linear amplifier (see Figure 11) • In crystal oscillator design (see Figure 12) Remark: All values given are typical unless otherwise specified. R2 R1 VCC 1 µF R2 R1 U04 ZL U04 C1 C2 out mna052 mna053 Vo(p-p) = VCC − 1.5 V centered at 0.5VCC. C1 = 47 pF (typical). C2 = 22 pF (typical). R1 = 1 MΩ to 10 MΩ (typical). R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC is typically 2 mA at VCC = 3.3 V and f = 10 MHz). A OL A u = – ----------------------------------------R1 1 + ------ ( 1 + A OL ) R2 AOL = open loop amplification. Au = voltage amplification. R1 ≥ 3 kΩ, R2 ≤ 1 MΩ. ZL > 10 kΩ; AOL = 20 (typical). Typical unity gain bandwidth product is 5 MHz. Fig 11. Linear amplifier configuration Fig 12. Crystal oscillator configuration 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 9 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter 14. Package outline Plastic surface-mounted package; 6 leads SOT363 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 13. Package outline SOT363 (SC-88) 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 10 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter Plastic surface-mounted package (TSOP6); 6 leads SOT457 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 c 1 2 3 Lp e bp wM B detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.1 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT457 REFERENCES IEC JEDEC JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Fig 14. Package outline SOT457 (TSOP6) 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 11 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 15. Package outline SOT886 (XSON6) 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 12 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 4× (1) L1 e L 6 e1 5 e1 4 6× (1) A A1 D E terminal 1 index area 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 2 mm Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 Fig 16. Package outline SOT891 (XSON6) 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 13 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter 15. Abbreviations Table 11. Acronym CMOS DUT ESD HBM MM Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model 16. Revision history Table 12. Revision history Release date 20091027 Data sheet status Product data sheet Change notice Supersedes 74LVC4GU04_4 Document ID 74LVC2GU04_5 Modifications: • • • Section 2: JESD22-A114E changed to JESD22-A114F Section 4 “Marking”: marking code for 74LVC2GU04GV changed from YU4 into VU4 Figure 8: drawing amended/improved Product data sheet Product specification Product specification Product specification 74LVC4GU04_3 74LVC2GU04_2 74LVC2GU04_1 - 74LVC2GU04_4 74LVC2GU04_3 74LVC2GU04_2 74LVC2GU04_1 20070521 20040921 20040524 20030829 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 14 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC2GU04_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 15 of 16 NXP Semiconductors 74LVC2GU04 Dual inverter 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 October 2009 Document identifier: 74LVC2GU04_5