74LVC646AD,112

74LVC646A Octal bus transceiver/register; 3-state Rev. 5 — 28 March 2013 Product data sheet 1. General description The 74LVC646A consists of non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the A or B bus is clocked in the internal registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH logic level. Output enable (OE) and direction (DIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the A or B register, or in both. With the select source inputs (SAB and SBA), stored and real-time (transparent mode) data can be multiplexed. The direction (DIR) input determines which bus receives data when OE is active (LOW). In the isolation mode (OE = HIGH), A data may be stored in the B register and/or B data may be stored in the A register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses A or B may be driven at a time. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits         5 V tolerant inputs/outputs for interfacing with 5 V logic Supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels 8-bit octal transceiver with D-type latch Back-to-back registers for storage Separate controls for data flow in each direction Supports partial power-down applications; inputs/outputs are high-impedance when VCC = 0 V  Complies with JEDEC standard:  JESD8-7A (1.65 V to 1.95 V)  JESD8-5A (2.3 V to 2.7 V)  JESD8-C/JESD36 (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-B exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Specified from 40 C to +85 C and 40 C to +125 C. 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC646AD 40 C to +125 C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 74LVC646ADB 40 C to +125 C SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 74LVC646APW 40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 4. Functional diagram 4 A0 B0 20 5 A1 B1 19 6 A2 B2 18 7 A3 B3 17 8 A4 B4 16 9 A5 B5 15 10 A6 B6 14 11 A7 B7 13 21 OE 3 DIR 2 SAB 22 SBA 1 CPAB 23 CPBA 001aab042 Fig 1. Functional diagram 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 2 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state 23 1 21 22 2 3 21 1 2 4 5 6 7 8 9 10 11 4 OE CPAB CPBA SAB SBA A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 DIR B7 23 C4 C5 G3 G6 G7 3EN2 3EN1 1 6 1 6 5D 22 5 1 4D 1 7 1 2 7 20 19 20 19 6 18 18 7 17 8 16 9 15 10 14 11 13 17 16 15 14 13 3 001aab041 001aab040 Fig 2. Logic symbol 74LVC646A Product data sheet Fig 3. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 3 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state OE DIR SBA CPBA SAB CPAB VCC S Y D1 An MUX D2 Q D FFn CP VCC S D1 Y Bn MUX D Q D2 FFn CP 8 identical channels 001aab043 Fig 4. Logic diagram 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 4 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state 5. Pinning information 5.1 Pinning CPAB 1 SAB 2 24 VCC 23 CPBA DIR 3 22 SBA A0 4 21 OE A1 5 20 B0 A2 6 A3 7 A4 8 17 B3 A5 9 16 B4 A6 10 15 B5 A7 11 14 B6 GND 12 13 B7 646A 19 B1 18 B2 001aab039 Fig 5. Pin configuration SO24 and (T)SSOP24 5.2 Pin description Table 2. Pin description Symbol Pin Description CPAB 1 A to B clock input (LOW to HIGH; edge-triggered) SAB 2 A to B select source input SBA 22 B to A select source input DIR 3 direction control input A[0:7] 4, 5, 6, 7, 8, 9, 10, 11 A data input/output B[0:7] 20, 19, 18, 17, 16, 15, 14, 13 B data input/output OE 21 output enable input (active LOW) CPBA 23 B to A clock input (LOW to HIGH, edge-triggered) GND 12 ground (0 V) VCC 24 supply voltage 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 5 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state 6. Functional description Function table[1] Table 3. Input Data I/O Function OE DIR CPAB CPBA SAB SBA A0 to A7 B0 to B7 X X  X X X input unspecified[2] store A and B unspecified X X X  X X unspecified[2] input store B and A unspecified H X   X X input input store A and B data H X H or L H or L X X input input hold storage; isolation L L X X X L output input real-time B data to A bus L L X H or L X H output input stored B data to A bus L H X X L X input output real-time A data to B bus L H H or L X H X input output stored A data to B bus [1] H = HIGH voltage level L = LOW voltage level X = don’t care  = LOW to HIGH level transition [2] The data output functions are enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled, i.e. data at the bus inputs are stored on every LOW to HIGH transition on the clock inputs. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V mA - 50 output HIGH or LOW state [2] 0.5 VCC + 0.5 V output 3-state [2] 0.5 +6.5 V - 50 mA VO > VCC or VO < 0 V IO output current ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot [1] VO = 0 V to VCC Tamb = 40 C to +125 C [3] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO24 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For (T)SSOP24 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 6 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions VI input voltage VO output voltage Min Typ Max Unit 1.65 - 3.6 V functional 1.2 - - V 0 - 5.5 V HIGH or LOW state 0 - VCC V 3-state 0 - 5.5 V 40 - +125 C Tamb ambient temperature in free air t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 40 C to +85 C Conditions VCC = 1.2 V Product data sheet Min Max Min Max Unit 1.08 - - 1.08 - V 0.65  VCC - - 0.65  VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V - - 0.35  VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC  0.2 - - VCC  0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V VCC = 1.65 V to 1.95 V 0.35  VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 3.6 V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V VI = VIH or VIL IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - 0.1 5 - 20 A input leakage VCC = 3.6 V; current VI = 5.5 V or GND 74LVC646A 40 C to +125 C Typ[1] All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 7 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions [2] 40 C to +125 C Unit Min Typ[1] Max Min Max - 0.1 10 - 20 A IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND; IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - 0.1 10 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC  0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF CI/O input/output capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 10.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. [2] For transceivers, the parameter IOZ includes the input leakage current. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 11. Symbol Parameter tpd propagation delay Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max - 17 - - - VCC = 1.65 V to 1.95 V 1.8 6.9 15.8 1.8 18.2 ns VCC = 2.3 V to 2.7 V 1.5 3.7 8.2 1.5 9.4 ns VCC = 2.7 V 1.5 3.6 7.8 1.5 10.0 ns 1.0 3.1 6.8 1.0 8.0 ns - 19 - - - ns VCC = 1.65 V to 1.95 V 2.4 8.6 17.8 2.4 20.5 ns VCC = 2.3 V to 2.7 V 1.7 4.5 9.1 1.7 10.5 ns An, Bn to Bn, An; see Figure 6 [2] VCC = 1.2 V VCC = 3.0 V to 3.6 V CPAB, CPBA to Bn, An; see Figure 7 [2] VCC = 1.2 V VCC = 2.7 V 1.5 4.1 8.6 1.5 11.0 ns VCC = 3.0 V to 3.6 V 1.0 3.8 7.6 1.0 9.5 ns - 19 - - - ns SAB, SBA to Bn, An; see Figure 8 [2] VCC = 1.2 V 74LVC646A Product data sheet ns VCC = 1.65 V to 1.95 V 1.5 7.6 19.8 1.5 22.9 ns VCC = 2.3 V to 2.7 V 1.5 4.0 10.2 1.5 11.8 ns VCC = 2.7 V 1.5 4.0 9.5 1.5 12.0 ns VCC = 3.0 V to 3.6 V 1.0 3.4 8.5 1.0 11.0 ns All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 8 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 11. Symbol Parameter Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions Min ten enable time OE to An and Bn; see Figure 9 - 20 - - - ns 7.2 17.8 2.4 20.6 ns VCC = 2.3 V to 2.7 V 2.0 4.1 9.8 2.0 11.3 ns VCC = 2.7 V 1.5 4.2 8.8 1.5 11.0 ns 1.0 3.3 7.8 1.0 10.0 ns - 20 - - - ns VCC = 1.65 V to 1.95 V 2.9 8.0 18.1 2.9 20.9 ns VCC = 2.3 V to 2.7 V 2.4 4.5 9.9 2.4 11.5 ns VCC = 2.7 V 1.5 4.2 8.9 1.5 11.5 ns 1.0 3.6 7.9 1.0 10.0 ns [2] VCC = 1.2 V VCC = 3.0 V to 3.6 V OE to An and Bn; see Figure 9 [2] VCC = 1.2 V - 10 - - - ns VCC = 1.65 V to 1.95 V 3.6 5.0 10.4 3.6 12.0 ns VCC = 2.3 V to 2.7 V 1.0 2.8 5.9 1.0 6.8 ns VCC = 2.7 V 1.5 3.6 7.1 1.5 9.0 ns 1.0 3.3 6.1 1.0 8.0 ns - 10 - - - ns 2.9 3.9 10.1 2.9 11.7 ns VCC = 3.0 V to 3.6 V DIR to An and Bn; see Figure 10 [2] VCC = 1.2 V VCC = 1.65 V to 1.95 V tsu pulse width set-up time 74LVC646A Product data sheet Max 2.4 VCC = 3.0 V to 3.6 V tW Min VCC = 1.65 V to 1.95 V DIR to An and Bn; see Figure 10 disable time Max [2] VCC = 1.2 V tdis Typ[1] VCC = 2.3 V to 2.7 V 1.0 2.1 5.7 1.0 6.6 ns VCC = 2.7 V 1.5 3.5 7.0 1.5 9.0 ns VCC = 3.0 V to 3.6 V 1.0 2.8 6.0 1.0 7.5 ns VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.3 - - 3.3 - ns VCC = 3.0 V to 3.6 V 3.3 1.9 - 3.3 - ns VCC = 1.65 V to 1.95 V 3.5 - - 3.5 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns clock HIGH or LOW of CPAB or CPBA; see Figure 7 An, Bn to CPAB, CPBA; see Figure 7 VCC = 2.7 V 1.6 - - 1.6 - ns VCC = 3.0 V to 3.6 V 1.5 0.35 - 1.5 - ns All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 9 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 11. Symbol Parameter Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions Min th hold time maximum frequency fmax Typ[1] Max Min Max An, Bn to CPAB, CPBA; see Figure 7 VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns VCC = 2.7 V 1.0 - - 1.0 - ns VCC = 3.0 V to 3.6 V 1.0 0.3 - 1.0 - ns VCC = 1.65 V to 1.95 V 100 - - 80 - MHz VCC = 2.3 V to 2.7 V 125 - - 100 - MHz VCC = 2.7 V 150 - - 120 - MHz 150 250 - 120 - MHz - - 1.0 - 1.5 see Figure 7 VCC = 3.0 V to 3.6 V tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] CPD power dissipation capacitance per input; VI = GND to VCC [4] ns VCC = 1.65 V to 1.95 V - 8.0 - - - pF VCC = 2.3 V to 2.7 V - 11.7 - - - pF VCC = 3.0 V to 3.6 V - 15.0 - - - pF [1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] [4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL  VCC2  fo) = sum of the outputs 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 10 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state 11. Waveforms VI An, Bn input VM GND t PLH t PHL VOH Bn, An output VM VOL 001aab044 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Input (An and Bn) to output (Bn and An) propagation delays VI An, Bn input VM GND th th tsu tsu VOH CPAB, CPBA input VM VOL tW 1/fmax tPHL tPLH VOH Bn, An output VM VOL 001aab045 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The An, Bn to CPAB, CPBA set-up and hold times, clock CPAB and CPBA pulse width, maximum frequency, and the CPAB, CPBA to output Bn, An propagation delays 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 11 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state VI SAB, SBA input VM GND t PLH t PHL VOH Bn, An output VM VOL 001aab046 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. The input SAB and SBA to output Bn and An propagation delay times VI OE input VM GND tPLZ tPZL VCC An, Bn output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH An, Bn tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aab047 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. The input OE to output An and Bn 3-state enable and disable times 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 12 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state VI DIR input VM GND tPHZ VOH tPZH VY An output VM GND tPLZ tPZL VCC An output VM VX VOL tPHZ tPZH VOH VY Bn output VM VOL tPZL tPLZ VOH Bn output VM VX VOL 001aab048 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. The input showing the input DIR to output An, Bn 3-state enable and disable times Table 8. Measurement points Supply voltage Input VCC VI VM VM VX VY 1.2 V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V 1.65 V to 1.95 V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V 2.3 V to 2.7 V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V 74LVC646A Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 13 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 11. Load circuitry for switching times Table 9. Test data Supply voltage Input VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC  2 ns 30 pF 1 k open 2  VCC GND 1.65 V to 1.95 V VCC  2 ns 30 pF 1 k open 2  VCC GND 2.3 V to 2.7 V VCC  2 ns 30 pF 500  open 2  VCC GND 2.7 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 74LVC646A Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 14 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state BUS B BUS A BUS B BUS A 12. Application information inputs inputs 001aab050 001aab049 Values for inputs are given in Table 10. Values for inputs are given in Table 10. Fig 12. Real-time transfer; bus B to bus A Table 10. Fig 13. Real-time transfer; bus A to bus B Real-time transfer[1] Direction Input OE DIR CPAB CPBA SAB SBA Bus B to bus A L L X X X L Bus A to bus B L H X X L X [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 15 of 23 74LVC646A NXP Semiconductors BUS B BUS A BUS B BUS A Octal bus transceiver/register; 3-state inputs inputs 001aab051 001aab052 Values for inputs are given in Table 11. Values for inputs are given in Table 11. Fig 14. Bus A and bus B to storage Table 11. Fig 15. Storage to bus A or bus B Storage transfer[1] Function Input OE DIR CPAB CPBA SAB SBA Bus A to storage X X  X X X Bus B to storage X X X  X X Bus A and B to storage H X   X X Storage to bus A L L X H or L X H Storage to bus B L H H or L X H X [1] H = HIGH voltage level L = LOW voltage level X = don’t care  = LOW to HIGH level transition 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 16 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state 13. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 13 24 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT137-1 (SO24) 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 17 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 17. Package outline SOT340-1 (SSOP24) 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 18 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 18. Package outline SOT355-1 (TSSOP24) 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 19 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic MM Machine Model 15. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC646A v.5 20130328 Product data sheet - 74LVC646A v.4 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges. 74LVC646A v.4 20040629 Product specification - 74LVC646A v.3 74LVC646A v.3 20000621 Product specification - 74LVC646A v.2 74LVC646A v.2 19980729 Product specification - 74LVC646A v.1 74LVC646A v.1 19980325 Product specification - - 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 20 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC646A Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 21 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC646A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 22 of 23 74LVC646A NXP Semiconductors Octal bus transceiver/register; 3-state 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 March 2013 Document identifier: 74LVC646A