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74LVT1403DR,118

74LVT1403DR,118

  • 厂商:

    NXP(恩智浦)

  • 封装:

    TSSOP32

  • 描述:

    IC BUFFER/DRIVER 32TSSOP

  • 数据手册
  • 价格&库存
74LVT1403DR,118 数据手册
Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia INTEGRATED CIRCUITS 74LVT1403 3.3V combined 8-bit bus receiver and 4-bit bus driver Product specification IC23 Data Handbook       1998 Nov 12 Philips Semiconductors Product specification 3.3V combined 8-bit bus receiver and 4-bit bus driver 74LVT1403 FEATURES DESCRIPTION • 4-bit 74LVT125-like bus driver • 8-bit 74LVT14-like Schmitt trigger • Bus drive +64mA/–32mA • 7 bus inputs with common inversion control pin • 32-pin TSSOP footprint • DE pin with resistive pull up and active LOW for easier live The 74LVT1403 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device combines the functionality of a 4-bit data path bus driver and 8-bit Schmitt trigger bus receiver, along with control logic in one 32-pin package. The receiver inputs are Schmitt trigger type capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The receiver outputs are 74LVT14 style with +32mA/–20mA drive capability. The receiver inputs include the bus hold feature. insertion • DE pin includes Schmitt trigger with typical 0.6V hysteresis The driver outputs feature power-up in 3-State/live insertion capability and are all controlled by the A/B, EN1, and EN2 control pins. The driver inputs include the bus hold feature. QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT ns tPLH Propagation delay An to Yn CL = 50pF; VCC = 3.3V 4.5 tPHL Propagation delay An to Yn CL = 50pF; VCC = 3.3V 4.0 ns CIN Input capacitance VI = 0V or 3.0V 3 pF ICC Total supply current Outputs low, VCC = 3.6V 4 mA ORDERING INFORMATION PACKAGES 32-pin plastic TSSOP TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER –40°C to +85°C 74LVT1403 DR 74LVT1403 DR SOT487-1 PIN CONFIGURATION PIN DESCRIPTION 32 VCC INV 1 RY0 PIN NUMBER SYMBOL NAME AND FUNCTION 31, 30, 29, 28, 27, 26, 25, 24 RA0–RA7 Receive Data inputs 2, 3, 4, 5, 6, 7, 8, 9 RY0–RY7 Receive Data outputs 2 31 RA0 RY1 3 30 RA1 RY2 4 29 RA2 12, 13, 14, 15 DA0–DA3 Driver Data inputs RY3 5 28 RA3 21, 20, 19, 18 DY0–DY3 Driver Data outputs 27 RA4 10, 11 EN1, EN2 Driver Output enables 26 RA5 23 A/B Mode control for enables 1 INV Inversion control 16, 22 GND Ground (0V) RY4 6 RY5 7 RY6 8 RY7 9 EN1 10 THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) 25 RA6 24 RA7 23 A/B EN2 11 22 GND 32 VCC Positive supply voltage DA0 12 21 DY0 17 DE Driver output enable active LOW with resistive pull up DA1 13 20 DY1 DA2 14 19 DY2 DA3 15 18 DY3 GND 16 17 DE SV00907 1998 Nov 12 2 853-2134 20359 Philips Semiconductors Product specification 3.3V combined 8-bit bus receiver and 4-bit bus driver 74LVT1403 LOGIC SYMBOL FUNCTION TABLE – RECEIVER INPUTS OUTPUTS INV RY1 RY0 RY1–RY7 L X H — H X L — L L — L H L — H L H — H H H — L RA1 RY7 RA7 H L X — A/B EN2 INV RA0 RY0 EN1 RA0–RA7 CONTROL BLOCK DE = = = = High voltage level Low voltage level Don’t care Reported on different line FUNCTION TABLE – DRIVER CONTROL INPUTS DA0 DA1 OUTPUT CONDITION DY0 DY1 DA2 DY2 DA3 DY3 DE A/B EN1 EN2 DY Status L L L L A L L X H Z L L H X Z L H H H A L H X L Z L H L X Z X X X Z SV00900 H H L X Z A = = = = = High voltage level Low voltage level Don’t care High impedance “off” state Active DATA PATH IN ACTIVE MODE 1998 Nov 12 3 INPUT OUTPUT DAn DYn L L H H Philips Semiconductors Product specification 3.3V combined 8-bit bus receiver and 4-bit bus driver 74LVT1403 ABSOLUTE MAXIMUM RATINGS1, 2 RATING UNIT VCC DC supply voltage PARAMETER –0.5 to +4.6 V VI DC input voltage3 –0.5 to +7.0 V Output in Off or High state –0.5 to +7.0 V Output in Low state 128 mA Output in High state –64 mA SYMBOL VOUT DC output CONDITIONS voltage3 DYn DC output current IOUT O Output in Low state –32 mA Output in High state 64 mA RYn DC output current IIK DC input diode current VI < 0 –50 mA IOK DC output diode current VO < 0 –50 mA Tstg Storage temperature range –65 to +150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER UNIT DC supply voltage VI Input voltage VIH High-level input voltage VIL Low-level Input voltage IOH O High level output current High-level MIN MAX 2.7 3.6 V 0 5.5 V 2.0 V 0.8 V DYn –32 mA RYn –20 mA DYn 32 mA RYn 32 mA DYn 64 mA 10 ns/V +85 °C Low level output current Low-level IOL Low-level output current; current duty cycle ≤ 50%, f ≥ 1kHz ∆t/∆V Input transition rise or fall rate; Outputs enabled Tamb Operating free-air temperature range 1998 Nov 12 –40 4 Philips Semiconductors Product specification 3.3V combined 8-bit bus receiver and 4-bit bus driver 74LVT1403 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER Temp = -40°C to +85°C TEST CONDITIONS UNIT MIN TYP1 VT+ Positive-going threshold RAn VCC = 3.3V 1.5 1.7 2.0 V VT– Negative-going threshold RAn VCC = 3.3V 0.9 1.1 1.3 V ∆VT Hysteresis RAn VCC = 3.3V 0.4 0.6 VIK Input clamp voltage VCC = 2.7V; IIK = –18mA RYn VOH RYn VOL output Low-level out ut voltage DYn V VCC = 2.7V; IOH = –6mA 2.4 V VCC = 3.0V; IOH = –20mA 2.0 VCC–0.1 V VCC = 2.7V; IOH = –8mA 2.4 2.5 V VCC = 3.0V; IOH = –32mA 2.0 2.2 0.2 V VCC = 2.7V; IOL = 24mA 0.5 V VCC = 3.0V; IOL = 32mA 0.5 V VCC = 2.7V; IOL = 100µA 0.1 0.2 V VCC = 2.7V; IOL = 24mA 0.3 0.5 V VCC = 3.0V; IOL = 16mA 0.25 0.4 V VCC = 3.0V; IOL = 32mA 0.3 0.5 V VCC = 3.0V; IOL = 64mA 0.4 0.55 V All inputs 1 10 Control pins ±0.1 ±1 INV, EN1, EN2, A/B ±0.1 6V; VI = GND VCC = 3 3.6V ±1 DE –60 –100 VCC = 3.6V; VI = VCC VCC = 3.6V; VI = GND IOFF V VCC = 2.7V; IOL = 100µA VCC = 3.6V; VI = VCC Input In ut leakage current V VCC–0.2 VCC = 0 or 3.6V; VI = 5.5V II V VCC–0.2 VCC = 2.7 to 3.6V; IOH = –100µA DYn V –1.2 VCC = 2.7 to 3.6V; IOH = –100µA High-level g output voltage MAX Data port ort4 µA 0.1 1 –1 –5 µA 1 ±100 µA Output off current VCC = 0V; VI or VO = 0 to 4.5V IHOLD Bus hold current RA and DA inputs VCC = 3V; VI = 0.8V 75 150 µA VCC = 3V; VI = 2.0V –75 –150 µA IEX Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 3.0V 60 125 µA Power-up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC; EN1, EN2, A/B, DE = Don’t care ±1 ±100 µA IOZH 3-State output high current VCC = 3.6V; VO = 3.0V 1 5 µA IOZL 3-State output low current VCC = 3.6V; VO = 0.5V IPU/PD ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 –1 –5 µA VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 0.13 0.19 mA VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 4 11 mA VCC = 3.6V; Outputs Disabled, VI = GND or VCC, IO = 05 0.13 0.19 mA VCC = 3V to 3.6V; One input at VCC–0.6V, Other inputs at VCC or GND 0.1 0.2 mA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V, a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. All RYn outputs High. All DYn outputs pulled up to VCC or pulled down to ground. 1998 Nov 12 5 Philips Semiconductors Product specification 3.3V combined 8-bit bus receiver and 4-bit bus driver 74LVT1403 AC CHARACTERISTICS RAn = Receive inputs; Ryn = Receive outputs DAn = Driver inputs; Dyn = Driver outputs LIMITS SYMBOL PARAMETER VCC = 3.3V ± 0.3V VCC = 2.7V MIN TYP MAX MAX 2 1.0 1.0 3.8 3.2 5.7 4.4 6.9 4.3 ns WAVEFORM UNIT tPLH tPHL Propagation delay RA0 to RY0 tPLH tPHL Propagation delay RAn to RYn (n = 1 to 7) 1, 2 2.0 2.0 4.5 4.0 6.7 5.7 7.8 6.4 ns tPLH tPHL Propagation delay Invert to RYn 1, 2 2.0 2.0 4.0 3.6 6.3 5.5 7.1 7.4 ns tPLH tPHL Propagation delay DAn to DYn 1 1.0 1.0 3.1 2.0 4.2 3.0 4.7 3.5 ns tPZH tPZL Output enable time ENn to DYn with A/B = 0 3 2.0 2.0 4.8 4.3 7.1 6.7 9.6 7.4 ns tPZH tPZL Output enable time ENn to DYn with A/B = 1 4 2.0 2.0 4.3 4.0 6.5 6.1 7.8 6.6 ns tPHZ tPLZ Output disable time ENn to DYn with A/B =0 3 2.0 2.0 4.7 4.0 7.1 6.3 8.2 6.9 ns tPHZ tPLZ Output disable time ENn to DYn with A/B =1 4 2.0 2.0 4.2 4.0 6.8 6.2 8.3 6.5 ns tPZH tPZL Output enable time A/B to DYn 3, 4 2.0 2.0 5.0 4.2 8.6 6.5 9.5 7.2 ns tPHZ tPLZ Output disable time A/B to DYn 3, 4 2.0 2.0 5.1 4.3 7.5 6.2 7.7 6.6 ns tPZH tPZL Output enable time DE to DYn 3 2.0 2.0 5.1 4.7 7.6 6.8 9.1 7.5 ns tPHZ tPLZ Output disable time DE to DYn 3 2.0 2.0 5.9 4.9 9.3 7.2 9.7 7.7 ns AC WAVEFORMS VM = 1.5V, VIN = GND to 2.7V 2.7V INV INPUT An INPUT 1.5V 2.7V INV INPUT RAn INPUT 1.5V 1.5V 1.5V 0V 0V tPHL tPLH tPHL tPLH VOH Yn OUTPUT 1.5V VOH RYn OUTPUT 1.5V VOL 1998 Nov 12 1.5V VOL SV00897 Waveform 1. 1.5V SV01015 Input (An) to Output (Yn) Propagation Delays Waveform 2. 6 Input (An) to Output (Yn) Propagation Delays Philips Semiconductors Product specification 3.3V combined 8-bit bus receiver and 4-bit bus driver 74LVT1403 AC WAVEFORMS (Continued) VM = 1.5V, VIN = GND to 2.7V 2.7V A/B INPUT OE INPUT 1.5V 2.7V A/B INPUT OE INPUT 1.5V 1.5V 1.5V 0V tPLZ tPZL Yn OUTPUT 0V tPLZ tPZL 3.0V Yn OUTPUT 1.5V 3.0V 1.5V VOL + 0.3V VOL tPZH VOL + 0.3V VOL tPZH tPHZ tPHZ VOH VOH – 0.3V VOH VOH – 0.3V Yn OUTPUT Yn OUTPUT 0V 0V SV00898 Waveform 3. SV01014 3-State Output Enable and Disable Times Waveform 4. 3-State Output Enable and Disable Times TEST CIRCUIT AND WAVEFORM 6.0V VCC Open VOUT VIN PULSE GENERATOR RL GND tW 90% NEGATIVE PULSE 90% VM VM 10% 10% D.U.T. RT 0V CL tTHL (tF) RL tTLH (tR) tTLH (tR) tTHL (tF) 90% Test Circuit for 3-State Outputs POSITIVE PULSE AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLH/tPHL Open tPLZ/tPZL 6V tPHZ/tPZH GND AMP (V) 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. 74LVT Amplitude Rep. Rate 2.7V 10MHz tW tR tF 500ns 2.5ns 2.5ns RT = Termination resistance should be equal to ZOUT of pulse generators. SV00092 1998 Nov 12 7 Philips Semiconductors Product specification 3.3V combined 8-bit bus receiver and 4-bit bus driver 74LVT1403 TSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm 1998 Nov 12 8 SOT487-1 Philips Semiconductors Product specification 3.3V combined 8-bit bus receiver and 4-bit bus driver 74LVT1403 NOTES 1998 Nov 12 9 Philips Semiconductors Product specification 3.3V combined 8-bit bus receiver and 4-bit bus driver 74LVT1403 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 05-98 Document order number:       1998 Nov 12 10 9397-750-04815
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