74LVT16245BDL

74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state Rev. 07 — 29 March 2010 Product data sheet 1. General description The 74LVT16245B; 74LVTH16245B is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The control function implementation minimizes external timing requirements. The device features an output enable input (nOE) for easy cascading and a direction input (nDIR) for direction control. 2. Features and benefits 16-bit bidirectional bus interface 3-state buffers Output capability: +64 mA and −32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection: JESD78B Class II exceeds 500 mA ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range 74LVT16245BDL 74LVTH16245BDL 74LVT16245BDGG 74LVTH16245BDGG 74LVT16245BEV 74LVT16245BBQ 74LVTH16245BBQ −40 °C to +85 °C −40 °C to +85 °C VFBGA56 −40 °C to +85 °C TSSOP48 −40 °C to +85 °C Name SSOP48 Description plastic shrink small outline package; 48 leads; body width 7.5 mm Version SOT370-1 Type number plastic thin shrink small outline package; 48 leads; SOT362-1 body width 6.1 mm plastic very thin fine-pitch ball grid array package; SOT702-1 56 balls; body 4.5 × 7 × 0.65 mm SOT1134-1 HXQFN60U plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 × 6 × 0.5 mm 4. Functional diagram 1DIR 1OE 1A0 1B0 1A1 1B1 1A2 1B2 1A3 1B3 1A4 1B4 1A5 1B5 1A6 1B6 1A7 1B7 2DIR 2OE 2A0 2B0 2A1 2B1 2A2 2B2 2A3 2B3 2A4 2B4 2A5 2B5 2A6 2B6 2A7 2B7 001aaa789 Pin numbers are shown for SSOP48 and TSSOP48 packages only. Fig 1. Logic symbol 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 2 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 1OE 1DIR 48 1 25 2OE 24 2DIR G3 3EN1 [BA] 3EN2 [AB] G6 6EN4 [BA] 6EN5 [AB] 1 2 2 3 5 6 8 9 11 12 4 5 13 14 16 17 19 20 22 23 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 mna709 Pin numbers are shown for SSOP48 and TSSOP48 packages only. Fig 2. IEC logic symbol 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 3 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 5. Pinning information 5.1 Pinning 74LVT16245B 74LVTH16245B 1DIR 1B0 1B1 GND 1B2 1B3 VCC 1B4 1B5 1 2 3 4 5 6 7 8 9 48 1OE 47 1A0 46 1A1 45 GND 44 1A2 43 1A3 42 VCC 41 1A4 40 1A5 39 GND 38 1A6 37 1A7 36 2A0 35 2A1 34 GND 33 2A2 32 2A3 31 VCC 30 2A4 29 2A5 28 GND 27 2A6 26 2A7 25 2OE 001aae474 74LVT16245B 1 A 1DIR 2 n.c. 3 n.c. 4 n.c. 5 n.c. 6 1OE B 1B1 1B0 GND GND 1A0 1A1 C 1B3 1B2 VCC GND VCC GND 1A2 1A3 GND 10 1B6 11 1B7 12 2B0 13 2B1 14 GND 15 2B2 16 2B3 17 VCC 18 2B4 19 2B5 20 GND 21 2B6 22 2B7 23 2DIR 24 001aae471 D 1B5 1B4 1A4 1A5 E 1B7 1B6 1A6 1A7 F 2B0 2B1 2A1 2A0 G 2B2 2B3 GND GND 2A3 2A2 H 2B4 2B5 VCC GND VCC GND 2A5 2A4 J 2B6 2B7 2A7 2A6 K 2DIR n.c. n.c. n.c. n.c. 2OE Transparent top view Fig 3. Pin configuration for SSOP48 and TSSOP48 Fig 4. Pin configuration for VFBGA56 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 4 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state terminal 1 index area D1 A32 A31 A30 A29 A28 A27 D4 A1 D5 B20 B19 B18 D8 A26 A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 A9 GND(1) B11 B12 B13 B15 B16 B17 A25 A24 A23 A22 74LVT16245B 74LVTH16245B B14 A21 A20 A19 A18 A10 D6 B8 B9 B10 D7 A17 D2 A11 A12 A13 A14 A15 A16 D3 001aaj656 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SOT1134-1 (HXQFN60U) 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 5 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 5.2 Pin description Table 2. Symbol Pin description Pin SOT370-1 and SOT362-1 1DIR, 2DIR 1B0 to 1B7 2B0 to 2B7 GND VCC 1OE, 2OE 2A0 to 2A7 1A0 to 1A7 n.c. 1, 24 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 SOT702-1 A1, K1 B2, B1, C2, C1, D2, D1, E2, E1 F1, F2, G1, G2, H1, H2, J1, J2 SOT1134-1 A30, A13 direction control input Description B20, A31, D5, D1, A2, data input/output B2, B3, A5 A6, B5, B6, A9, D2, D6, A12, B8 data input/output 4, 10, 15, 21, 28, 34, 39, B3, D3, G3, J3, J4, 45 G4, D4, B4 7, 18, 31, 42 48, 25 36, 35, 33, 32, 30, 29, 27, 26 47, 46, 44, 43, 41, 40, 38, 37 C3, H3, H4, C4 A6, K6 F6, F5, G6, G5, H6, H5, J6, J5 B5, B6, C5, C6, D5, D6, E5, E6 A2, A3, A4, A5, K2, K3, K4, K5 A32, A3, A8, A11, A16, ground (0 V) A19, A24, A27 A1, A10, A17, A26 A29, A14 A21, B13, B12, A18, D3, D7, A15, B10 B18, A28, D8, D4, A25, B16, B15, A22 A4, A7, A20, A23, B1, B4, B7, B9, B11, B14, B17, B19 supply voltage output enable input (active LOW) data input/output data input/output not connected 6. Functional description 6.1 Function table Table 3. Control nOE L L H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Function table [1] Input/output nDIR L H X nAn output nAn = nBn input Z nBn input output nBn = nAn Z 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 6 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO Tstg Tj Ptot Parameter supply voltage input voltage output voltage input clamping current output clamping current output current storage temperature junction temperature total power dissipation Tamb = −40 °C to +85 °C; (T)SSOP48 package VFBGA56 package HXQFN60U package [1] [2] [3] [4] [3] [4] [4] [2] [1] Conditions Min −0.5 −0.5 −0.5 −50 −50 −64 −65 - Max +4.6 +7.0 +7.0 128 +150 150 500 1000 1000 Unit V V V mA mA mA mA °C °C mW mW mW output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state output in HIGH-state [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Symbol VCC VI VIH VIL IOH IOL Recommended operating conditions Parameter supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current none current duty cycle ≤ 50 %; fi ≥ 1 kHz Tamb Δt/ΔV ambient temperature in free-air input transition rise and fall rate outputs enabled Conditions Min 2.7 0 2.0 −32 −40 Typ Max 3.6 5.5 0.8 32 64 +85 10 Unit V V V V mA mA mA °C ns/V 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 7 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 VIK VOH °C[1] VCC = 2.7 V; IIK = −18 mA IOH = −8 mA; VCC = 2.7 V IOH = −32 mA; VCC = 3.0 V VOL LOW-level output voltage VCC = 2.7 V IOL = 100 μA IOL = 24 mA VCC = 3.0 V IOL = 16 mA IOL = 32 mA IOL = 64 mA II input leakage current control pins VCC = 3.6 V; VI = VCC or GND VCC = 0 V or 3.6 V; VI = 5.5 V input/output data pins; VCC = 3.6 V VI = 5.5 V VI = VCC VI = 0 V IOFF IBHL IBHH IBHLO IBHHO ILO IO(pu/pd) ICC power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current output leakage current power-up/power-down output current supply current VCC = 3 V; VI = 0.8 V VCC = 3 V; VI = 2.0 V nAn input; VI = 0 V to 3.6 V; VCC = 3.6 V nAn input; VI = 0 V to 3.6 V; VCC = 3.6 V output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled ΔICC CI additional supply current input capacitance per input pin; VCC = 3.0 V to 3.6 V; one input at VCC − 0.6 V, other inputs at VCC or GND pins nDIR and nOE, VO = 0 V or 3.0 V [5] [6] [4] [3] [2] Conditions Min −1.2 2.4 2.0 −5 75 500 - Typ −0.85 2.5 2.3 0.07 0.3 0.25 0.3 0.4 0.1 0.1 0.1 0.5 −0.1 0.1 135 −135 75 40 Max 0.2 0.5 0.4 0.5 0.55 ±1 10 20 10 ±100 −75 −500 125 ±100 Unit V V V V V V V V V μA μA μA μA μA μA μA μA μA μA μA μA input clamping voltage HIGH-level output voltage IOH = −100 μA; VCC = 2.7 V to 3.6 V VCC − 0.2 VCC - 0.07 4.7 0.07 0.1 3 0.12 6.0 0.12 0.2 - mA mA mA mA pF 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 8 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Cio(off) off-state input/output capacitance Conditions pins nAn and nBn, outputs disabled; VO = GND or VCC Min Typ 9 Max Unit pF [1] [2] [3] [4] [5] [6] Typical values are measured at VCC = 3.3 V and at Tamb = 25 °C. Unused pins at VCC or GND. This is the bus hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only. ICC is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol tPLH Parameter LOW to HIGH propagation delay Conditions nAn to nBn or nBn to nAn; see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPHL HIGH to LOW propagation delay nAn to nBn or nBn to nAn; see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPZH OFF-state to HIGH propagation delay nOE to nAn or nBn; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPZL OFF-state to LOW propagation delay nOE to nAn or nBn; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPHZ HIGH to OFF-state propagation delay nOE to nAn or nBn; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPLZ LOW to OFF-state propagation delay nOE to nAn or nBn; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V [1] All typical values are at VCC = 3.3 V and Tamb = 25 °C. Min Typ[1] Max Unit Tamb = −40 °C to +85 °C 1.0 1.9 3.5 3.3 ns ns 1.0 1.0 1.0 1.5 1.5 1.7 2.8 2.8 3.2 3.0 3.5 3.3 5.3 4.5 5.1 4.1 5.7 5.1 4.6 4.6 ns ns ns ns ns ns ns ns ns ns 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 9 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 11. Waveforms VI nAn, nBn input GND t PHL VOH nBn, nAn output VOL VM mna477 VM t PLH Measurements points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay input (nAn, nBn) to output (nBn, nAn) VI nOE input 0V tPZL 3.0 V nAn or nBn output VOL tPZH VOH nBn or nAn output 0V 001aaj658 VM tPLZ VM VX tPHZ VY VM Measurements points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. 3-state output enable and disable times Table 8. Input VM 1.5 V Measurement points Output VM 1.5 V VX VOL + 0.3 V VY VOH − 0.3 V 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 10 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VEXT VCC PULSE GENERATOR VI DUT RT CL RL RL VO 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Table 9. Input VI 2.7 V Test circuit for measuring switching times Test data Load fi ≤ 10 MHz tW 500 ns tr, tf ≤ 2.5 ns CL 50 pF RL 500 Ω VEXT tPHZ, tPZH GND tPLZ, tPZL 6V tPLH, tPHL open 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 11 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE vM A Z 48 25 Q A2 A1 (A 3) θ Lp 1 24 A pin 1 index L wM detail X e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT370-1 (SSOP48) 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 12 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c y HE vMA Z 48 25 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp 24 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT362-1 (TSSOP48) 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 13 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm SOT702-1 D B A ball A1 index area E A A2 A1 detail X e1 e 1/2 b e CAB ∅w M C ∅v M C y1 C y K J H e G F E D C B A ball A1 index area 1 2 3 4 5 6 1/2 e2 e X DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.3 0.2 A2 0.7 0.6 b 0.45 0.35 D 4.6 4.4 E 7.1 6.9 e 0.65 e1 3.25 e2 5.85 v 0.15 w 0.08 y 0.08 y1 0.1 0 2.5 scale 5 mm OUTLINE VERSION SOT702-1 REFERENCES IEC JEDEC MO-225 JEITA EUROPEAN PROJECTION ISSUE DATE 02-08-08 03-07-01 Fig 11. Package outline SOT702-1 (VFBGA56) 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 14 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm D B A SOT1134-1 terminal 1 index area E A A1 detail X e2 e1 1/2 e v w L1 CAB C D2 D6 A10 eR B7 e b A11 B8 B10 A16 D7 A17 B11 D3 v w CAB C y1 C C y L e Eh 1/2 e B1 A1 terminal 1 index area D5 D1 B20 A32 Dh k 0 Dimensions Unit mm A A1 b D 4.1 4.0 3.9 Dh 1.90 1.85 1.80 E 6.1 6.0 5.9 Eh 3.90 3.85 3.80 e 0.5 e1 1 2.5 scale e2 2.5 B18 A27 D8 D4 B17 A26 e3 e4 X 5 mm e3 3 e4 4.5 eR 0.5 k L L1 0.125 0.075 0.025 v w y y1 0.1 sot1134-1_po max 0.50 0.05 0.35 nom 0.48 0.02 0.30 min 0.46 0.00 0.25 0.25 0.35 0.20 0.30 0.15 0.25 0.07 0.05 0.08 Outline version SOT1134-1 References IEC --JEDEC --JEITA --- European projection Issue date 08-12-17 09-01-22 Fig 12. Package outline SOT1134-1 (HXQFN60U) 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 15 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 13. Abbreviations Table 10. Acronym BiCMOS DUT ESD HBM MM TTL Abbreviations Description Bipolar Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20100329 Data sheet status Product data sheet Change notice Supersedes 74LVT_LVTH16245B_6 Document ID 74LVT_LVTH16245B_7 Modifications: 74LVT_LVTH16245B_6 Modifications: 74LVT_LVTH16245B_5 74LVT_LVTH16245B_4 74LVT16245B_3 74LVT16245B_2 74LVT16245B_1 • • • 74LVT16245BBQ and 74LVTH16245BBQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1) package. Product data sheet 74LVT_LVTH16245B_5 Section 2: Class II added for latch-up protection. Table 6: Conditions for bus hold overdrive current have changed. Product data sheet Product data sheet Product data sheet Product specification Product specification 74LVT_LVTH16245B_4 74LVT16245B_3 74LVT16245B_2 74LVT16245B_1 - 20090409 20090312 20060323 20021031 19980219 19940523 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 16 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVT_LVTH16245B_7 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 17 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVT_LVTH16245B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 29 March 2010 18 of 19 NXP Semiconductors 74LVT16245B; 74LVTH16245B 3.3 V 16-bit transceiver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 March 2010 Document identifier: 74LVT_LVTH16245B_7