74LVTH244A

74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state Rev. 04 — 3 September 2008 Product data sheet 1. General description The 74LVT244A; 74LVTH244A is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal buffer that is ideal for driving bus lines. The device features two output enables (1OE, 2OE), each controlling four of the 3-state outputs. 2. Features I I I I I I I I I I Octal bus interface 3-state buffers Output capability: +64 mA and −32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection N JESD78 Class II exceeds 500 mA I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVT244AD 74LVTH244AD 74LVT244ADB 74LVTH244ADB 74LVT244APW 74LVTH244APW 74LVT244ABQ 74LVTH244ABQ −40 °C to +85 °C −40 °C to +85 °C TSSOP20 −40 °C to +85 °C SSOP20 −40 °C to +85 °C SO20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm Version SOT163-1 SOT339-1 Type number plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm SOT764-1 DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state 4. Functional diagram 1A0 1Y0 2 18 4 1A1 1Y1 16 1 EN 18 16 14 12 6 1A2 1Y2 14 2 8 1 1A3 1OE 1Y3 12 4 6 8 11 2A0 2Y0 9 19 EN 9 7 5 3 mna826 13 2A1 2Y1 7 11 13 15 2A2 2Y2 5 15 17 17 19 2A3 2OE 2Y3 3 mna825 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 2 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state 5. Pinning information 5.1 Pinning 74LVT244A 74LVTH244A 1OE 2 3 4 5 6 7 8 9 GND 10 2A0 11 GND(1) 1 terminal 1 index area 1A0 2Y3 1OE 1A0 2Y3 1A1 2Y2 1A2 2Y1 1A3 2Y0 1 2 3 4 5 6 7 8 9 20 VCC 19 2OE 18 1Y0 17 2A3 16 1Y1 15 2A2 14 1Y2 13 2A1 12 1Y3 11 2A0 001aae510 74LVT244A 74LVTH244A 20 VCC 19 2OE 18 1Y0 17 2A3 16 1Y1 15 2A2 14 1Y2 13 2A1 12 1Y3 1A1 2Y2 1A2 2Y1 1A3 2Y0 GND 10 001aah764 Transparent top view (1) The die substrate is attached to this pad using a conductive die attach material. It cannot be used as a supply pin or input. Fig 3. Pin configuration for SO20 and (T)SSOP20 Fig 4. Pin configuration for DHVQFN20 5.2 Pin description Table 2. Symbol 1OE, 2OE 1A0, 1A1, 1A2, 1A3 2Y0, 2Y1, 2Y2, 2Y3 GND 2A0, 2A1, 2A2, 2A3 1Y0, 1Y1, 1Y2, 1Y3, VCC Pin description Pin 1, 19 2, 4, 6, 8 9, 7, 5, 3 10 Description output enable input (active low) data input data output ground (0 V) 11, 13, 15, 17 data input 18, 16, 14, 12 data output 20 supply voltage 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 3 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state 6. Functional description 6.1 Function table Table 3. Control nOE L H [1] Function table [1] Input nAn L H X Output nYn L H Z H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO Tstg Tj Ptot [1] [2] [3] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current storage temperature junction temperature total power dissipation Conditions [1] Min −0.5 −0.5 −0.5 −65 [2] Max +4.6 +7.0 +7.0 −50 −50 128 −64 +150 150 500 Unit V V V mA mA mA mA °C °C mW output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state output in HIGH-state [1] - Tamb = −40 to +85 °C [3] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. For SO20 packages: above 70 °C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K. 8. Recommended operating conditions Table 5. Symbol VCC VI IOH Operating conditions Parameter supply voltage input voltage HIGH-level output current Conditions Min 2.7 0 Typ Max 3.6 5.5 −32 Unit V V mA 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 4 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state Table 5. Symbol IOL Tamb ∆t/∆V Operating conditions …continued Parameter LOW-level output current ambient temperature Conditions none current duty cycle ≤ 50 %; fi ≥ 1 kHz in free-air input transition rise and fall rate outputs enabled Min −40 Typ Max 32 64 +85 10 Unit mA mA °C ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 °C VIK VIH VIL VOH [1] Conditions VCC = 2.7 V; IIK = −18 mA Min −1.2 2.0 - Typ −0.9 2.5 2.2 0.1 0.3 0.25 0.3 0.4 0.1 ±0.1 0.1 −1 1 150 −150 60 ±1 Max 0.8 0.2 0.5 0.4 0.5 0.55 10 ±1 1 − ±100 −75 −500 125 ±100 Unit V V V V V V V V V V V µA µA µA µA µA µA µA µA µA µA µA input clamping voltage HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 2.7 V to 3.6 V; IOH = −100 µA VCC = 2.7 V to 3.6 V; IOH = −8 mA VCC = 3.0 V; IOH = −32 mA VCC − 0.2 VCC − 0.1 2.4 2.0 [2] VOL LOW-level output voltage VCC = 2.7 V; IOL = 100 µA VCC = 2.7 V; IOL = 24 mA VCC = 3.0 V; IOL = 16 mA VCC = 3.0 V; IOL = 32 mA VCC = 3.0 V; IOL = 64 mA II input leakage current all input pins VCC = 0 V or 3.6 V; VI = 5.5 V control pins VCC = 3.6 V; VI = VCC or GND data pins VCC = 3.6 V; VI = VCC VCC = 3.6 V; VI = 0 V −5 [3] IOFF IBHL IBHH IBHLO IBHHO ILO IO(pu/pd) power-off leakage current bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current output leakage current power-up/power-down output current VCC = 0 V; VI or VO = 0 V to 4.5 V VCC = 3 V; VI = 0.8 V VCC = 3 V; VI = 2.0 V nAn input; VCC = 0 V to 3.6 V; VI = 3.6 V nAn input; VCC = 0 V to 3.6 V; VI = 3.6 V nYn output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care [4] 75 − 500 - 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 5 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IOZ OFF-state output current Conditions VCC = 3.6 V; VI = VIH or VIL VO = 3.0 V VO = 0.5 V ICC supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A output HIGH output LOW outputs disabled ∆ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input at VCC − 0.6 V and other inputs at VCC or GND VI = 0 V or 3.0 V outputs disabled; VO = 0 V or 3.0 V [5] [6] Min −5 Typ 1 −1 Max 5 − Unit µA µA - 0.13 3 0.13 0.1 0.19 12 0.19 0.2 mA mA mA mA CI CO [1] [2] [3] [4] [5] [6] input capacitance output capacitance All typical values are at Tamb = 25 °C. Unused pins at VCC or GND. - 4 8 - pF pF This is the bus hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. ICC is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol tPLH Parameter [1] Conditions nAn to nYn; see Figure 5 VCC = 2.7 V VCC = 3.0 V to 3.6 V nAn to nYn; see Figure 5 VCC = 2.7 V VCC = 3.0 V to 3.6 V see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V Min Typ Max Unit Tamb = −40 °C to +85 °C LOW to HIGH propagation delay 1 1 1 1.1 1.9 2.5 2.6 3.2 3.1 3.3 5.0 4.1 5.1 4.1 6.3 5.2 6.7 5.2 6.3 5.6 ns ns ns ns ns ns ns ns ns ns tPHL HIGH to LOW propagation delay tPZH OFF-state to HIGH propagation delay tPZL OFF-state to LOW propagation delay tPHZ HIGH to OFF-state propagation delay 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 6 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol tPLZ Parameter LOW to OFF-state propagation delay Conditions see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V [1] All typical values are at VCC = 3.3 V and Tamb = 25 °C. Min 1.8 Typ 3.3 Max 5.6 5.1 Unit ns ns 11. Waveforms VI nAn input GND tPLH VOH nYn output VOL VM VM mna171 VM VM tPHL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay input (nAn) to output (nYn) propagation delays VI nOE input GND tPZL 3.0 V nYn output VOL t PZH t PHZ VM tPLZ VM VX VOH nYn output 0V 001aae464 VM VY Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Table 8. Input VM 1.5 V 3-state output enable and disable times Measurement points Output VM 1.5 V VX VOL + 0.3 V VY VOH − 0.3 V 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 7 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VDD VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aai546 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 7. Table 9. Input VI 2.7 V Load circuitry for switching times Test data Load fi ≤ 10 MHz tW 500 ns tr, tf ≤ 2.5 ns CL 50 pF RL 500 Ω VEXT tPHZ, tPZH GND tPLZ, tPZL 6V tPLH, tPHL open 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 8 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 8. Package outline SOT163-1 (SO20) © NXP B.V. 2008. All rights reserved. 74LVT_LVTH244A_4 Product data sheet Rev. 04 — 3 September 2008 9 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 10 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 7.4 7.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.9 0.5 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT339-1 (SSOP20) © NXP B.V. 2008. All rights reserved. 74LVT_LVTH244A_4 Product data sheet Rev. 04 — 3 September 2008 10 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 10 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT360-1 (TSSOP20) 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 11 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 9 vMCAB wM C y1 C C y 1 Eh 20 10 e 11 19 Dh 0 12 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 11. Package outline SOT764-1 (DHVQFN20) 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 12 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state 13. Abbreviations Table 10. Acronym BiCMOS DUT ESD HBM MM TTL Abbreviations Description BIpolar Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20080903 Data sheet status Product data sheet Change notice Supersedes 74LVT_LVTH244A_3 Document ID 74LVT_LVTH244A_4 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3 “Ordering information” and Section 12 “Package outline” DHVQFN20 package added. Product specification Product specification 74LVT244A_2 74LVT244A_1 74LVT_LVTH244A_3 74LVT244A_2 20060315 19980219 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 13 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 September 2008 14 of 15 NXP Semiconductors 74LVT244A; 74LVTH244A 3.3 V octal buffer/line driver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 September 2008 Document identifier: 74LVT_LVTH244A_4