ADC1003S050

ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with voltage regulator Rev. 02 — 7 August 2008 Product data sheet 1. General description The ADC1003S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital Converters (ADC) for professional video and other applications. They convert the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz. All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible, although a low-level sine wave clock input signal is allowed. The device includes an internal voltage reference regulator. If the application requires that the reference is driven via external sources the recommendation is to use one of the ADC1004S030/040/050 family. 2. Features I I I I I I I I I I I I I I 10-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) No missing codes guaranteed In-Range (IR) CMOS output Levels TTL and CMOS compatible digital inputs 3 V to 5 V CMOS digital outputs Low-level AC clock input signal allowed Internal reference voltage regulator Power dissipation only 235 mW (typical) Low analog input capacitance, no buffer amplifier required No sample-and-hold circuit required 3. Applications High-speed analog-to-digital conversion for: I Video data digitizing I Radar I Transient signal analysis I Global Positioning System (GPS) receiver I Σ∆ modulators NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator I Cellular based stations I Barcode scanner I Medical imaging 4. Quick reference data Table 1. Quick reference data VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. Symbol VCCA VCCD VCCO ICCA ICCD ICCO INL DNL fclk(max) Parameter analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current integral non-linearity fclk = 40 MHz; ramp input fclk = 40 MHz; ramp input Conditions Min 4.75 4.75 3.0 30 40 50 Typ 5.0 5.0 3.3 30 16 1 ±0.8 ±0.5 235 Max 5.25 5.25 5.25 35 21 2 ±2.0 ±0.9 305 Unit V V V mA mA mA LSB LSB MHz MHz MHz mW differential non-linearity fclk = 40 MHz; ramp input maximum clock frequency ADC1003S030TS ADC1003S040TS ADC1003S050TS fclk = 40 MHz; ramp input Ptot total power dissipation 5. Ordering information Table 2. Ordering information Package Name ADC1003S030TS ADC1003S040TS ADC1003S050TS SSOP28 SSOP28 SSOP28 Description plastic shrink small outline package; 28 leads; body width 5.3 mm plastic shrink small outline package; 28 leads; body width 5.3 mm plastic shrink small outline package; 28 leads; body width 5.3 mm Version Sampling frequency (MHz) Type number SOT341-1 30 SOT341-1 40 SOT341-1 50 ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 2 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 6. Block diagram VCCA 3 DEC 5 CLK 1 VCCD2 11 OE 10 REFERENCE VOLTAGE REGULATOR RT 9 CLOCK DRIVER 2 TC 25 D9 24 D8 23 D7 Rlad analog voltage input VI 8 ANALOG - TO - DIGITAL CONVERTER LATCHES CMOS OUTPUTS 22 D6 21 D5 20 D4 19 D3 RM 7 18 D2 17 D1 16 D0 13 MSB data outputs LSB RB 6 VCCO ADC1003S030/040/050 IN-RANGE LATCH CMOS OUTPUT 26 IR output 28 4 AGND analog ground 12 DGND2 digital ground 14 OGND output ground 27 DGND1 VCCD1 digital ground 014aaa321 Fig 1. Block diagram ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 3 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 7. Pinning information 7.1 Pinning CLK TC VCCA AGND DEC RB RM VI RT 1 2 3 4 5 6 7 8 9 28 VCCD1 27 DGND1 26 IR 25 D9 24 D8 23 D7 22 D6 21 D5 20 D4 19 D3 18 D2 17 D1 16 D0 15 n.c. 014aaa320 ADC1003S 050TS OE 10 VCCD2 11 DGND2 12 VCCO 13 OGND 14 Fig 2. Pin configuration 7.2 Pin description Table 3. Symbol CLK TC VCCA AGND DEC RB RM VI RT OE VCCD2 DGND2 VCCO OGND n.c. D0 D1 D2 D3 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Description clock input two’s complement input (active LOW) analog supply voltage (5 V) analog ground decoupling input reference voltage BOTTOM input reference voltage MIDDLE analog input voltage reference voltage TOP input output enable input (CMOS level input, active LOW) digital supply voltage 2 (5 V) digital ground 2 supply voltage for output stages (3 V to 5 V) output ground not connected data output; bit 0 (Least Significant Bit (LSB)) data output; bit 1 data output; bit 2 data output; bit 3 ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 4 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator Pin description …continued Pin 20 21 22 23 24 25 26 27 28 Description data output; bit 4 data output; bit 5 data output; bit 6 data output; bit 7 data output; bit 8 data output; bit 9 (Most Significant Bit (MSB)) in-range data output digital ground 1 digital supply voltage 1 (5 V) Table 3. Symbol D4 D5 D6 D7 D8 D9 IR DGND1 VCCD1 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCA VCCD VCCO ∆VCC Parameter analog supply voltage digital supply voltage output supply voltage supply voltage difference staged VCCA − VCCD VCCA − VCCO VCCD −VCCO VI Vi(clk)(p-p) IO Tstg Tamb Tj [1] Conditions [1] [1] [1] Min −0.3 −0.3 −0.3 −1.0 −1.0 −1.0 −0.3 −55 −40 - Max +7.0 +7.0 +7.0 +1.0 +4.0 +4.0 +7.0 VCCD 10 +150 +85 150 Unit V V V V V V V V mA °C °C °C input voltage peak-to-peak clock input voltage output current storage temperature ambient temperature junction temperature referenced to AGND referenced to DGND The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply voltage differences ∆VCC are respected. 9. Thermal characteristics Table 5. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 110 Unit K/W ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 5 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 10. Characteristics Table 6. Characteristics VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. Symbol Supplies VCCA VCCD VCCO ∆VCC analog supply voltage digital supply voltage output supply voltage supply voltage difference VCCA − VCCD VCCA − VCCO VCCA − VCCO ICCA ICCD ICCO Ptot Inputs Clock input CLK (referenced to DGND)[1] VIL VIH IIL IIH Zi Ci VIL VIH IIL IIH IIL IIH Zi Ci VRB VRT Vref(dif) Iref LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input impedance input capacitance LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input current HIGH-level input current input impedance input capacitance voltage on pin RB voltage on pin RT differential reference voltage reference current VRT − VRB VIL = 0.8 V VIH = 2 V VI = VRB = 1.3 V VI = VRT = 3.67 V fi = 4.43 MHz Vclk = 0.8 V Vclk = 2 V fclk = 40 MHz 0 2 −1 0 2 −1 1.1 3.4 2.25 0 2 2 2 0 35 8 5 1.3 3.6 2.3 9.39 0.8 VCCD +1 10 0.8 VCCD 1 1.5 3.8 2.35 V V µA µA kΩ pF V V µA µA µA µA kΩ pF V V V mA © NXP B.V. 2008. All rights reserved. Parameter Conditions Min 4.75 4.75 3.0 −0.2 −0.2 −0.2 - Typ 5.0 5.0 3.3 30 16 1 235 Max 5.25 5.25 5.25 +0.20 +2.25 +2.25 35 21 2 305 Unit V V V V V V mA mA mA mW analog supply current digital supply current output supply current total power dissipation fclk = 40 MHz; ramp input fclk = 40 MHz; ramp input - Inputs OE and TC (referenced to DGND) VI (Analog input voltage referenced to AGND) Reference voltages for the resistor ladder using the internal voltage regulator see Table 7 ADC1003S030_040_050_2 Product data sheet Rev. 02 — 7 August 2008 6 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator Table 6. Characteristics …continued VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. Symbol Rlad TCRlad Voffset Vi(a)(p-p) Parameter ladder resistance ladder resistor temperature coefficient offset voltage peak-to-peak analog input voltage LOW-level output voltage HIGH-level output voltage OFF-state output current IOL = 1 mA IOH = −1 mA 0.5 V < VO < VCCO 4;[1] 30 40 50 8.5 5.5 MHz MHz MHz ns ns BOTTOM TOP [2] [2] [3] Conditions Min 1.90 Typ 245 456 175 175 1.95 Max 2.00 Unit Ω mΩ/K mV mV V Digital outputs D9 to D0 and IR (Referenced to OGND) VOL VOH IOZ fclk(max) 0 −20 0.5 VCCO +20 V V µA VCCO − 0.5 - Switching characteristics; clock input CLK see Figure maximum clock frequency ADC1003S030TS ADC1003S040TS ADC1003S050TS tw(clk)H tw(clk)L HIGH clock pulse width LOW clock pulse width full effective bandwidth full effective bandwidth Analog signal processing Linearity INL DNL Eoffset EG integral non-linearity differential non-linearity offset error gain error fclk = 40 MHz; ramp input fclk = 40 MHz; ramp input middle code from device to device, using internal reference voltage full-scale sine wave 75 % full-scale sine wave small signal at mid-scale; VI = ±10 LSB at code 512 ts(LH) ts(HL) LOW to HIGH settling time full-scale square wave; see Figure 6 HIGH to LOW settling time full-scale square wave; see Figure 6 [4] - ±0.8 ±0.5 ±1 ±3 ±2.0 ±0.9 - LSB LSB LSB % Bandwidth (fclk = 40 MHz) B bandwidth [5] [5] - 15 20 350 - MHz MHz MHz [5] [6] - 1.5 1.5 3.0 3.0 ns ns [6] ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 7 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator Table 6. Characteristics …continued VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. Symbol α1H α2H α3H THD S/N Parameter first harmonic level second harmonic level third harmonic level total harmonic distortion signal-to-noise ratio Conditions fi = 4.43 MHz fi = 4.43 MHz fi = 4.43 MHz fi = 4.43 MHz full-scale: without harmonics; fclk = 40 MHz; fi = 4.43 MHz Min 55 Typ −70 −72 −61 58 Max 0 −63 −63 Unit dB dB dB dB dB Harmonics (fclk = 40 MHz); see Figure 7 and Figure 8 Signal-to-noise ratio; see Figure 7 and Figure 8[7] Effective bits; see Figure 7 and Figure 8[7] ENOB effective number of bits ADC1003S030TS; fclk = 30 MHz fi = 4.43 MHz fi = 7.5 MHz fi = 4.43 MHz fi = 7.5 MHz fi = 10 MHz fi = 15 MHz fi = 4.43 MHz fi = 7.5 MHz fi = 10 MHz fi = 15 MHz Two-tone[8] αIM Bit error rate BER bit error rate fclk = 50 MHz; fi = 4.43 MHz; VI = ±16 LSB at code 512 fclk = 40 MHz; PAL modulated ramp 10−13 times/sample intermodulation suppression fclk = 40 MHz −69 dB 9.4 9.1 9.3 9.0 8.9 8.1 9.3 8.9 8.8 8.0 bit bit bit bit bit bit bit bit bit bit ADC1003S040TS; fclk = 40 MHz; ADC1003S050TS; fclk = 50 MHz Differential gain[9] Gdif differential gain 0.8 % ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 8 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator Table 6. Characteristics …continued VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. Symbol Differential ϕdif Parameter phase[9] differential phase fclk = 40 MHz; PAL modulated ramp 0.4 deg Conditions Min Typ Max Unit Timing (fclk = 40 MHz; CL = 15 pF); see Figure 4[10] td(s) th(o) td(o) CL tdZH tdZL tdHZ tdLZ sampling delay time output hold time output delay time load capacitance float to active HIGH delay time float to active LOW delay time active HIGH to float delay time active LOW to float delay time VCCO = 4.75 V VCCO = 3.15 V 3-state output delay times; see Figure 5 5.5 12 19 12 8.5 15 24 15 ns ns ns ns 4 3 10 12 13 15 15 ns ns ns ns pF [1] [2] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns Analog input voltages producing code 0 up to and including code 1023: a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB (VRB) at Tamb = 25 °C. b) Voffset TOP is the difference between reference voltage on pin RT (VRT) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 °C. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. a) The current flowing into the resistor ladder is I L = --------------------------------------- and the full-scale input range at the converter R +R +R OB L OT [3] V RT – V RB RL to cover code 0 to code 1023, is V I = R L × I L = --------------------------------------- × ( V RT – V RB ) = 0.848 × ( V RT – V RB ) R OB + R L + R OT b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio --------------------------------------- will be kept reasonably constant from device to device. Consequently, variation of the output codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [4] [5] [6] RL R OB + R L + R OT ( V 1023 – V 0 ) – V i ( P – P ) E G = -------------------------------------------------------- × 100 V i(P – P) The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSB, neither any significant attenuation are observed in the reconstructed signal. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. © NXP B.V. 2008. All rights reserved. ADC1003S030_040_050_2 Product data sheet Rev. 02 — 7 August 2008 9 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator [7] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to signal-to-noise ratio: SINAD = ENOB × 6.02 + 1.76 dB. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. Measurement carried out using video analyzer VM700A, where the video analog signal is reconstructed through a digital-to-analog converter. [8] [9] [10] Output data acquisition: the output data is available after the maximum delay time of td(o). For the 50 MHz version it is recommended to have the lowest possible output load. RT ROT code 1023 RL RL RM RL IL Rlad RL code 0 ROB RB 014aaa325 Fig 3. Explanation of Table 6 Table note 3 11. Additional information relating to Table 6 Table 7. Code Underflow 0 1 ↓ 511 ↓ 1022 1023 Overflow Output coding and input voltage (typical values; referenced to AGND) Vi(a)(p-p) (V) < 1.455 1.455 2.43 3.405 > 3.405 IR 0 1 1 ↓ ↓ ↓ 11 1 0 Binary outputs D9 to D0 00 0000 0000 00 0000 0000 00 0000 0001 ↓ 01 1111 1111 ↓ 11 1111 1110 11 1111 1111 11 1111 1111 Two’s complement outputs D9 to D0 10 0000 0000 10 0000 0000 10 0000 0001 ↓ 11 1111 1111 ↓ 01 1111 1110 01 1111 1111 01 1111 1111 ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 10 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator Mode selection OE 1 0 0 D9 to D0 high impedance active; two’s complement active; binary IR high impedance active active Table 8. TC X 0 1 sample N sample N + 1 tw(clk)L sample N + 2 tw(clk)H VCCO CLK 50% 0V sample N sample N + 1 sample N + 2 VI td(s) th(o) VCCO DATA D0 to D9 DATA N−2 DATA N−1 td(o) DATA N DATA N+1 50% 0V 014aaa326 Fig 4. Timing diagram ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 11 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator VCCD OE 50 % tdHZ HIGH 90 % output data tdLZ HIGH output data LOW 10 % tdZL tdZH 50 % LOW 50 % TEST VCCD 3.3 kΩ S1 VCCD VCCD DGND DGND tdLZ tdZL tdHZ tdZH ADC1003S050 15 pF S1 OE 014aaa334 frequency on pin OE = 100 kHz Fig 5. Timing diagram and test conditions of 3-state output delay time. ts(LH) code 1023 VI code 0 2 ns 50% ts(HL) 50% 2 ns CLK 50% 50% 0.5 ns 0.5 ns 014aaa327 Fig 6. Analog input settling-time diagram ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 12 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator +20 amplitude (dB) −20 014aaa328 −60 −100 −140 0 5.00 10.0 15.0 f (MHz) 20.0 (1) Effective bits: 9.42; THD = −71.8 dB (2) Harmonic levels (dB): 2nd = −83.19; 3rd = −78.09; 4th = −78.72; 5th = −78.33; 6th = −77.55 Fig 7. Typical fast Fourier transform (fclk = 40 MHz; fi = 4.43 MHz) +20 amplitude (dB) −20 014aaa329 −60 −100 −140 0 5.0 10.0 15.0 20.0 f (MHz) 25.0 (1) Effective bits: 8.91; THD = −62.96 dB (2) Harmonic levels (dB): 2nd = −71.38; 3rd = −71.54; 4th = −74.14; 5th = −65.15; 6th = −77.16 Fig 8. Typical fast Fourier transform (fclk = 50 MHz; fi = 10 MHz) ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 13 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator VCCA VCCO D9 to D0 IR VI OGND 014aaa330 AGND 014aaa332 Fig 9. CMOS data and in-range outputs Fig 10. Analog inputs DEC VCCA RT Rlad VCCO RM Rlad REGULATOR Rlad OE TC Rlad RB OGND 014aaa323 AGND 014aaa333 Fig 11. OE and TC input Fig 12. RB, RM and RT ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 14 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator VCCD CLK 1.5 V DGND 014aaa324 Fig 13. CLK input 12. Application information 12.1 Application diagram CLK TC VCCA (3) 100 nF 1 2 3 4 5 6 7 28 27 26 25 24 23 VCCD1 DGND1 IR D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 n.c.(2) (3) 100 nF AGND DEC 4.7 nF 1 nF RB(1) RM(1) 1 nF AGND AGND VI RT(1) OE VCCD2 ADC1003S050 8 9 10 11 12 13 14 22 21 20 19 18 17 16 15 AGND 100 nF AGND (3) 100 nF DGND2 VCCO (3) 100 nF OGND 014aaa322 The analog and digital supplies should be separated and well decoupled. A user manual is available that describes the demonstration board that uses the ADC1003S030/040/050 family in an application environment. (1) RB, RM and RT are decoupled to AGND. (2) Pin 15 may be connected to DGND in order to prevent noise influence. (3) Decoupling capacitor for supplies: must be placed close to the device. Fig 14. Application diagram ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 15 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 12.2 Alternative parts The following alternative parts are also available: Table 9. Alternative parts Description Single 10 bits ADC Single 10 bits ADC Single 10 bits ADC Single 10 bits ADC Single 8 bits ADC Single 8 bits ADC Single 8 bits ADC [1] [1] [1] [1] [1] [1] [1] Type number ADC1004S030 ADC1004S040 ADC1004S050 ADC1005S060 ADC0804S030 ADC0804S040 ADC0804S050 [1] Pin to pin compatible Sampling frequency 30 MHz 40 MHz 50 MHz 60 MHz 30 MHz 40 MHz 50 MHz ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 16 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 13. Package outline SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 D E A X c y HE vMA Z 28 15 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 14 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 15. Package outline SOT341-1 (SSOP28) ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 17 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 14. Revision history Table 10. Revision history Release date Data sheet status 20080807 Product data sheet Change notice Supersedes ADC1003S030_040_050_1 Document ID ADC1003S030_040_050_2 Modifications: • • Corrections made to the values of ∆VCC and the cross reference in subhead Reference voltages for the resistor ladder in Table 6. Corrections made to the table notes in Figure 14. Product data sheet - ADC1003S030_040_050_1 20080611 ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 18 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC1003S030_040_050_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 August 2008 19 of 20 NXP Semiconductors ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 17. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 12.1 12.2 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 6 . . . 10 Application information. . . . . . . . . . . . . . . . . . 15 Application diagram . . . . . . . . . . . . . . . . . . . . 15 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 August 2008 Document identifier: ADC1003S030_040_050_2