ADC1613D

ADC1613D series Dual 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface Rev. 02 — 23 April 2010 Preliminary data sheet 1. General description The ADC1613D is a dual-channel 16-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1613D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a 3.3 V source for analog and a 1.8 V source for the output driver, it embeds two serial outputs. Each lane is differential and complies with the JESD204A standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC configurations is also available via the binary level control pins taken, which are used at power-up. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). Excellent dynamic performance is maintained from the baseband to input frequencies of 170 MHz or more, making the ADC1613D ideal for use in communications, imaging, and medical applications. 2. Features and benefits SNR, 72.5 dBFS; SFDR, 88 dBc Sample rate up to 125 Msps Clock input divider by 2 for less jitter contribution 3 V, 1.8 V single supplies Flexible input voltage range: 1 V to 2 V (peak-to-peak) Two configurable serial outputs INL ± 1 LSB; DNL ± 0.5 LSB Pin compatible with the ADC1213D series HVQFN56 package Input bandwidth, 600 MHz Power dissipation, 995 mW at 80 Msps SPI register programming Duty cycle stabilizer High IF capability Offset binary, two’s complement, gray code Power-down mode and Sleep mode Compliant with JESD204A serial transmission standard NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 3. Applications Wireless and wired broadband communications Spectral analysis Ultrasound equipment Portable instrumentation Imaging systems Software defined radio 4. Ordering information Table 1. Ordering information Sampling frequency (Msps) 125 105 80 65 Package Name HVQFN56 HVQFN56 HVQFN56 HVQFN56 Description Version Type number ADC1613D125HN/C1 ADC1613D105HN/C1 ADC1613D080HN/C1 ADC1613D065HN/C1 plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 × 8 × 0.85 mm plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 × 8 × 0.85 mm plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 × 8 × 0.85 mm plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 × 8 × 0.85 mm ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 2 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 5. Block diagram CFG (0 to 3) SDIO/DCS CS SCLK/DCS ERROR CORRECTION AND DIGITAL PROCESSING SPI SYNCP SYNCN INAP T/H INPUT STAGE INAM 8-bit CLOCK INPUT STAGE & DUTY CYCLE CONTROL FRAME ASSEMBLY ADCA CORE 16-BIT PIPELINED D15 to D0 OTR SCRAMBLER A ENCODER 8-bit/10-bit A SWING_n SERIALIZER A 10-bit OUTPUT BUFFER A CMLPA 8-bit CMLNA CLKP DLL PLL CLKM ERROR CORRECTION AND DIGITAL PROCESSING ENCODER 8-bit/10-bit B SCRAMBLER B SERIALIZER B 10-bit OUTPUT BUFFER B CMLPB 8-bit 8-bit INBP T/H INPUT STAGE INBM ADCB CORE 16-BIT PIPELINED OTR D15 to D0 CMLNB SWING_n CLOCK INPUT STAGE & DUTY CYCLE CONTROL ADC1613D SCRAMBLER RESET REFBT SYSTEM REFERENCE AND POWER MANAGEMENT REFAB REFAT 005aaa168 REFBB VCMB VCMA SENSE VREF Fig 1. Block diagram ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 3 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 6. Pinning information 6.1 Pinning 48 SWING_1 47 SWING_0 44 SYNCN INAP INAM VCMA REFAT REFAB AGND CLKP CLKM AGND 1 2 3 4 5 6 7 8 9 43 SYNCP 42 DGND 41 DGND 40 VDDD 39 CMLPA 38 CMLNA 37 VDDD 36 DGND 35 DGND 34 VDDD 33 CMLNB 32 CMLPB 31 VDDD 30 DGND 29 DGND DGND 28 005aaa169 54 SENSE ADC1613D REFBB 10 REFBT 11 VCMB 12 INBM 13 INBP 14 VDDA 15 VDDA 16 SCLK/DCS 17 SDIO/DCS 18 CS 19 AGND 20 RESET 21 SCRAMBLER 22 CFG0 23 CFG1 24 CFG2 25 CFG3 26 VDDD 27 Transparent top view Fig 2. Pinning diagram 6.2 Pin description Table 2. Symbol INAP INAM VCMA REFAT REFAB AGND CLKP CLKM AGND REFBB REFBT VCMB INBM ADC1613D_SER_2 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Type [1] I I O O O G I I G O O O I Description channel A analog input channel A complementary analog input channel A output common voltage channel A top reference channel A bottom reference analog ground clock input complementary clock input analog ground channel B bottom reference channel B top reference channel B output common voltage channel B complementary analog input © NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 02 — 23 April 2010 45 DGND 52 AGND 51 AGND 46 VDDD 56 VDDA 53 VDDA 50 VDDA 55 VREF 49 DNC 4 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Pin description …continued Pin 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Type [1] I P P I I/O I G I I I/O I/O I/O I/O P G G G P O O P G G P O O P G G I I G P I I O P G G P Description channel B analog input analog power supply 3 V analog power supply 3 V SPI clock data format select SPI data IO duty cycle stabilizer chip select bar analog ground JEDEC digital IP reset scrambler enable and disable Table 29 (input) or OTRA (output)[2] Table 29 (input) or OTRB (output)[2] Table 29 (input) Table 29 (input) digital power supply 1.8 V digital ground digital ground digital ground digital power supply 1.8 V channel B output channel B complementary output digital power supply 1.8 V digital ground digital ground digital power supply 1.8 V channel A complementary output channel A output digital power supply 1.8 V digital ground digital ground synchronization from FPGA synchronization from FPGA digital ground digital power supply 1.8 V JESD204 serial buffer programmable output swing JESD204 serial buffer programmable output swing do not connect analog power supply 3 V analog ground analog ground analog power supply 3 V Table 2. Symbol INBP VDDA VDDA SCLK/DCS SDIO/DCS CS AGND RESET SCRAMBLER CFG0 CFG1 CFG2 CFG3 VDDD DGND DGND DGND VDDD CMLPB CMLNB VDDD DGND DGND VDDD CMLNA CMLPA VDDD DGND DGND SYNCP SYNCN DGND VDDD SWING_0 SWING_1 DNC VDDA AGND AGND VDDA ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 5 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Pin description …continued Pin 54 55 56 Type [1] I I/O P Description reference programming pin voltage reference input/output analog power supply 3 V Table 2. Symbol SENSE VREF VDDA [1] [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” B. 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDA VDDD ΔVCC Tstg Tamb Tj [1] [2] Parameter analog supply voltage digital supply voltage supply voltage difference storage temperature ambient temperature junction temperature Conditions [1] [2] Min −0.4 −0.4 −55 −40 - Max +4.6 +2.5 +125 +85 125 Unit V V V °C °C °C VDDA − VDDD The supply voltage VDDA may have any value between −0.5 V and +7.0 V provided that the supply voltage differences ΔVCC are respected. The supply voltage VDDD may have any value between −0.5 V and +5.0 V provided that the supply voltage differences ΔVCC are respected. 8. Thermal characteristics Table 4. Symbol Rth(j-a) Rth(j-c) [1] Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions [1] [1] Typ 17.8 6.8 Unit K/W K/W Value for six layers board in still air with a minimum of 25 thermal vias. ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 6 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 9. Static characteristics Table 5. Symbol Supplies VDDA VDDD IDDA IDDD Ptot analog supply voltage digital supply voltage analog supply current digital supply current total power dissipation fclk = 125 Msps; fi =70 MHz fclk = 125 Msps; fi = 70 MHz fclk = 125 Msps fclk = 105 Msps fclk = 80 Msps fclk = 65 Msps P Digital inputs Clock inputs: pins CLKP and CLKM, AC coupled LVPECL Vi(clk)dif LVDS Vi(clk)dif SINE wave Vi(clk)dif differential clock input voltage LOW-level input voltage HIGH-level input voltage LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance peak-to-peak ±0.8 ±1.5 V differential clock input voltage peak-to-peak ±0.4 V differential clock input voltage peak-to-peak ±0.8 V power dissipation power-down mode standby mode 2.85 1.65 3.0 1.8 343 150 1270 1150 995 885 30 200 3.4 1.95 V V mA mA mW mW mW mW mW mW Characteristics Parameter Conditions Min Typ Max Unit LVCMOS mode VIL VIH VIL VIH IIL IIH VIL VIH IIL IIH CI 0.7VDDA −6 −30 0 0.7VDDA −10 −50 0 0.66VDDD 4 0.3VDDA +6 +30 0.3VDDA VDDA +10 +50 V V V V μA μA V V μA μA pF Logic inputs: Power-down: pins CFG0 to CFG3, SCRAMBLER, SWING_0, and SWING_1 SPI: pins CS, SDIO/DCS, and SCLK/DCS ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 7 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Table 5. Symbol II RI CI VI(cm) Bi VI(dif) VO(cm) IO(cm) Characteristics …continued Parameter input current input resistance input capacitance common-mode input voltage input bandwidth differential input voltage common-mode output voltage common-mode output current voltage on pin VREF output input peak-to-peak Conditions track mode track mode track mode track mode Min −5 0.9 1 Typ 15 5 1.5 600 0.5VDDA Max +5 2 2 Unit μA Ω pF V MHz V V μA Analog inputs: pins INAP, INAM, INBP, and INBM Voltage controlled regulator output: pins VCMA and VCMB Reference voltage input/output: pin VREF VVREF 0.5 0.5 pin AGND; VVREF; VDDA 1 1 V V V Reference mode selection: pin SENSE VSENSE voltage on pin SENSE Data outputs: CMLPA, CMLNA Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 000 VOL VOH LOW-level output voltage HIGH-level output voltage DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled 1.5 1.65 1.8 1.35 1.45 1.625 1.8 1.275 1.4 1.6 1.8 1.2 1.35 1.575 1.8 1.125 V V V V V V V V V V V V V V V V Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 001 VOL VOH LOW-level output voltage HIGH-level output voltage Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 010 VOL VOH LOW-level output voltage HIGH-level output voltage Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 011 VOL VOH LOW-level output voltage HIGH-level output voltage ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 8 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Table 5. Symbol VOL VOH Characteristics …continued Parameter LOW-level output voltage HIGH-level output voltage Conditions DC coupled; output AC coupled DC coupled; output AC coupled differential; input differential; input Min −5 no missing codes guaranteed full-scale −0.95 Typ 1.3 1.55 1.8 1.05 0.95 1.47 ±1 ±0.5 ±2 ± 0.5 Max +5 +0.95 Unit V V V V V V LSB LSB mV % % Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 100 Serial configuration: SYNCCP, SYNCCN VIL VIH Accuracy INL DNL Eoffset EG MG(CTC) Supply PSRR power supply rejection ratio 100 mV (p-p) on VDDA 35 dBc integral non-linearity differential non-linearity offset error gain error channel-to-channel gain matching LOW-level input voltage High-level input voltage [1] Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless otherwise specified. ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 9 of 43 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10. Dynamic characteristics Table 6. Symbol Characteristics Parameter Conditions ADC1613D065 Min Typ Max Preliminary data sheet Rev. 02 — 23 April 2010 10 of 43 ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors ADC1613D080 Min Typ Max ADC1613D105 Min Typ Max ADC1613D125 Min Typ Max Unit Analog signal processing α2H second harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz α3H third harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz THD total harmonic distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz ENOB effective number of bits fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SNR signal-to-noise ratio fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SFDR spurious-free dynamic range fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz 89 88 87 84 88 87 86 83 87 86 85 82 11.7 11.6 11.5 11.4 72.3 71.5 70.9 70.4 88 87 86 83 89 88 87 84 88 87 86 83 87 86 85 82 11.7 11.6 11.5 11.4 72.2 71.4 70.9 70.3 88 87 86 83 88 88 86 83 87 87 85 82 86 86 84 81 11.7 11.6 11.5 11.4 72.0 71.4 70.8 70.2 87 87 85 82 90 89 87 85 89 88 86 84 88 87 85 83 11.6 11.6 11.5 11.4 71.6 71.3 70.7 70.1 89 88 86 84 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits ADC1613D series; serial JESD204A interface bits bits bits dBFS dBFS dBFS dBFS dBc dBc dBc dBc ADC1613D series xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 6. Symbol IMD Characteristics …continued Parameter intermodulation distortion Conditions fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz αct(ch) [1] Preliminary data sheet Rev. 02 — 23 April 2010 11 of 43 ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors ADC1613D065 Min Typ Max ADC1613D080 Min Typ Max ADC1613D105 Min Typ Max ADC1613D125 Min Typ Max Unit dBc dBc dBc dBc dBc - 89 88 87 84 100 - - 89 88 87 85 100 - - 88 88 86 83 100 - - 89 88 86 84 100 - channel crosstalk fi = 70 MHz Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless otherwise specified. ADC1613D series; serial JESD204A interface ADC1613D series xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 11. Clock and digital output timing Table 7. Symbol Characteristics Parameter Conditions ADC1613D065 Min Typ Max Preliminary data sheet Rev. 02 — 23 April 2010 12 of 43 ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors ADC1613D080 Min Typ Max ADC1613D105 Min Typ Max ADC1613D125 Min Typ Max Unit Clock timing input: pins CLKP and CLKM fclk tlat(data) δclk clock frequency data latency time clock duty cycle DCS_EN = 1: en DCS_EN = 0: dis td(s) twake [1] 20 17 30 45 - 50 50 0.8 65 20 70 55 - 60 17 30 45 - 50 50 0.8 80 20 70 55 - 75 17 30 45 - 50 50 0.8 105 20 70 55 - 100 17 30 45 - 50 50 0.8 125 20 70 55 - Msps clock cycle % % ns ns sampling delay time wake-up time - - - - Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified. ADC1613D series; serial JESD204A interface ADC1613D series NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 11.1 Serial output timings The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions are: • 3.125 Gbps data rate • Tamb = 25 °C • DC coupling with two different receiver common-mode voltages 005aaa088 Fig 3. Eye diagram at 1 V receiver common-mode 005aaa089 Fig 4. Eye diagram at 2 V receiver common-mode ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 13 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 12. SPI timing Table 8. Symbol tw(SCLK) tw(SCLKH) tw(SCLKL) tsu th fclk(max) [1] Characteristics Parameter SCLK pulse width SCLK HIGH pulse width SCLK LOW pulse width set-up time hold time maximum clock frequency data to SCLKH CS to SCLKH data to SCLKH CS to SCLKH Conditions Min 40 16 16 5 5 2 2 Typ Max 25 Unit ns ns ns ns ns ns ns MHz Serial peripheral interface timings Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM,INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless otherwise specified. tsu CS tsu th tw(SCLKL) tw(SCLK) tw(SCLKH) th SCLK SDIO R/W W1 W0 A12 A11 D2 D1 D0 005aaa065 Fig 5. SPI timings ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 14 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 13. Application information 13.1 Analog inputs 13.1.1 Input stage description The analog input of the ADC1613D supports differential or single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INP and INM set to 0.5VDDA. The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 13.2 and Table 21 for further details). Figure 6 shows the equivalent circuit of the sample and hold input stage, including ElectroStatic Discharge (ESD) protection and circuit and package parasitics. Package ESD Parasitics Switch INAP INBP 1, 14 Ron = 15 Ω 4 pF Cs Internal clock INAM INBM 2, 13 Ron = 15 Ω Switch 4 pF Cs Internal clock 005aaa069 Fig 6. Input sampling circuit The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. 13.1.2 Anti-kickback circuitry Anti-kickback circuitry (Figure 7) is needed to counteract the effects of a charge injection generated by the sampling capacitance. The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 15 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface R INAP INBP C R INAM INBM 005aaa176 Fig 7. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 9. 3 MHz 70 MHz 170 MHz RC coupling versus input frequency - typical values R 25 Ω 12 Ω 12 Ω C 12 pF 8 pF 8 pF Input frequency 13.1.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 8 would be suitable for a baseband application. 100 nF Analog input 100 nF ADT1-1WT 25 Ω 25 Ω INAP INBP 12 pF 100 nF 100 nF 25 Ω 25 Ω INAM INBM VCM 100 nF 100 nF 005aaa070 Fig 8. Single transformer configuration ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 16 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface ADT1-1WT 100 nF 50 Ω ADT1-1WT 50 Ω 12 Ω INAP INBP 8.2 pF Analog input 50 Ω 50 Ω 12 Ω 100 nF INAM INBM VCM 100 nF 100 nF 005aaa071 Fig 9. Dual transformer configuration The configuration shown in Figure 9 is recommended for high frequency applications. In both cases, the choice of transformer will be a compromise between cost and performance. 13.2 System reference and power management 13.2.1 Internal/external reference The ADC1613D has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF an SENSE (see Figure 11, Figure 12, Figure 13 and Figure 14), in 1 dB steps between 0 dB and −6 dB, via SPI control bits INTREF[2:0] (when bit INTREF_EN = 1; see Table 21). The equivalent reference circuit is shown in Figure 10. External reference is also possible by providing a voltage on pin VREF as described in Figure 13. ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 17 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface REFT REFERENCE AMP REFB VREF EXT_ref BANDGAP REFERENCE BUFFER EXT_ref ADC CORE SENSE SELECTION LOGIC 005aaa164 Fig 10. Reference equivalent schematic Table 10 shows how to choose between the different internal/external modes: Table 10. Mode Internal (Figure 11) Internal (Figure 12) External (Figure 13) Internal, SPI mode (Figure 14) Reference modes SPI bit, “Internal reference” 0 0 0 1 SENSE pin GND VREF pin Full Scale, V (p-p) 330 pF capacitor 2 to GND 1 VREF pin = SENSE pin and 330 pF capacitor to GND VDDA External voltage 1 to 2 from 0.5 V to 1 V 1 to 2 VREF pin = SENSE pin and 330 pF capacitor to GND ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 18 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface VREF 330 pF VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa116 005aaa117 Fig 11. Internal reference, 2 V (p-p) full scale Fig 12. Internal reference, 1 V (p-p) full scale VREF 0.1 μF VREF V 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE REFERENCE EQUIVALENT SCHEMATIC SENSE VDDA 005aaa119 005aaa118 Fig 13. External reference, 1 V (p-p) to 2 V (p-p) full-scale Fig 14. Internal reference via SPI, 1 V (p-p) to 2 V (p-p) full-scale Figure 11 to Figure 14 indicate how to connect the SENSE and VREF pins. 13.2.2 Reference gain control The reference gain is programmable between 0 dB to −6 dB in steps of 1 dB via the SPI (see Table 21). The corresponding full scale input voltage range varies between 2 V (p-p) and 1 V (p-p), as shown in Table 11: Table 11. 000 001 010 011 100 101 110 111 Reference SPI gain control Level 0 dB −1 dB −2 dB −3 dB −4 dB −5 dB −6 dB not used Full Scale, V (p-p) 2 1.78 1.59 1.42 1.26 1.12 1 x INTREF[2:0] ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 19 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 13.2.3 Common-mode output voltage (VI(cm)) An 0.1 μF filter capacitor should be connected between on the one hand the pins VCMA and VCMB and on the other hand ground to ensure a low-noise common-mode output voltage. When AC-coupled, these pins can be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. PACKAGE ESD PARASITICS COMMON MODE REFERENCE 1.5 V VCMA VCMB 0.1 μF ADC CORE 005aaa077 Fig 15. Reference equivalent schematic 13.2.4 Biasing The common-mode output voltage, VO(cm), should be set externally to 1.5 V (typical). The common-mode input voltage, VI(cm), at the inputs to the sample and hold stage (pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal performance. 13.3 Clock input 13.3.1 Drive modes The ADC1613D can be driven differentially (SINE, LVPECL or LVDS) with little or no influence on dynamic performances. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor). LVCMOS clock input CLKP CLKP CLKM LVCMOS clock input CLKM 005aaa174 005aaa053 a. Rising edge LVCMOS Fig 16. LVCMOS single-ended clock input b. Falling edge LVCMOS ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 20 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface CLKP Sine clock input Sine clock input CLKP CLKM CLKM 005aaa173 005aaa054 a. Sine clock input b. Sine clock input (with transformer) CLKP LVDS clock input LVPECL clock input CLKM CLKP CLKM 005aaa055 005aaa172 c. LVDS clock input Fig 17. Differential clock input d. LVPECL clock input 13.3.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode voltage of the differential input stage is set via internal resistors of 5 kΩ resistors. Package ESD Parasitics CLKP Vcm(clk) SE_SEL SE_SEL 5 kΩ 5 kΩ CLKM 005aaa081 Fig 18. Equivalent input circuit Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 21 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface If single-ended is implemented without setting SE_SEL accordingly, the unused pin should be connected to ground via a capacitor. 13.3.3 Clock input divider The ADC1613D contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see Table 20). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. 13.3.4 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performances of the ADC by compensating the input clock signal duty cycle. When the duty cycle stabilizer is active (bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the input clock signal should have a duty cycle of between 45 % and 55 %. Table 12. 0 1 Duty cycle stabilizer Description duty cycle stabilizer disable duty cycle stabilizer enable DCS_enable SPI 13.4 Digital outputs 13.4.1 Serial output equivalent circuit The JESD204A standard specify that in case of connecting the receiver and the transmitter in DC coupling, both of them need to be provided by the same supply. VDDD 50 Ω CMLPA/CLMPB 100 Ω RECEIVER CMLNA/CLMNB + − 12 mA to 26 mA AGND 005aaa082 Fig 19. CML output connection to the receiver in DC coupling The output should be terminated when 100 Ω (typical) has been reached at the receiver side. ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 22 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface VDDD 50 Ω CMLPA/CMLPB 10 nF CMLNA/CMLNB 10 nF 100 Ω RECEIVER + − 12 mA to 26 mA 005aaa083 Fig 20. CML output connection to the receiver in AC coupling 13.5 JESD204A serializer 13.5.1 Digital JESD204A formatter The block placed after the ADC cores is used to implement all functionalities of the JESD204A standard. This ensures signal integrity and guarantees the clock and the data recovery at the receiver side. The block is highly parameterized and can be configured in various ways depending on the sampling frequency and the number of lanes used. M CONVERTERS L LANES N bits from Cr0 + CS bits for control F octets TX transport layer FRAME TO OCTETS SCRAMBLER ALIGNMENT CHARACTER GENERATOR 8-bit/ 10-bit SER LANE0 SYNC~ TX CONTROLLER N bits from CrM−1 + CS bits for control samples stream to lane stream mapping F octets FRAME TO OCTETS SCRAMBLER ALIGNMENT CHARACTER GENERATOR 8-bit/ 10-bit SER LANE1 N' = N+CS S samples per frame cycle CF: position of controls bits HD: frame boundary break Padding with Tails bits (TT) Lx(F) octets L octets 005aaa084 Mx(N'xS) bits Fig 21. General overview of the JESD204A serializer ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 23 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface ADC_MODE[1:0] SCRAMB_IN_MODE[1:0] N & CS LANE_MODE[1:0] N + CS 8 00 SCR PRBS 01 8-bit/ 10-bit '0' ADCA 16 00 bypass alignment disable_char_repl ×1 PLL AND DLL ×F × 10F frame CLK char CLK bit CLK PRBS sync_request ADCB 16 00 '0' ADC_D PRBS N & CS 01 SCR N + CS 8 00 LANE_MODE[1:0] SCAMB_IN_MODE[1:0] 005aaa170 PRBS 11 DUMMY 16 10 16 10 00 ADC_PD LANE_POLARITY SER 01 '0/1' PRBS 10 11 FRAME ASSEMBLY FSM (f assy, char repl, ILA, test mode) 11 SWING_SEL[2:0] '0/1' 10 SER 01 LANE_POLARITY 8-bit/ 10-bit 10 00 DUMMY PRBS 16 10 16 11 ADC_MODE[1:0] Fig 22. Detailed view of the JESD204A serializer with debug functionality 13.5.2 ADC core output codes versus input voltage Table 13 shows the data output codes for a given analog input voltage. Table 13. < −1 −1 −0.99996948 −0.99993896 −0.99990845 −0.99987793 .... −0.00006104 −0.00003052 0 +0.00003052 +0.00006104 .... +0.99987793 ADC1613D_SER_2 Output codes versus input voltage Offset binary 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0011 0000 0000 0000 0100 .... 0111 1111 1111 1110 0111 1111 1111 1111 1000 0000 0000 0000 1000 0000 0000 0001 1000 0000 0000 0010 .... 1111 1111 1111 1011 Two’s complement 1000 0000 0000 0000 1000 0000 0000 0000 1000 0000 0000 0001 1000 0000 0000 0010 1000 0000 0000 0011 1000 0000 0000 0100 .... 1111 1111 1111 1110 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0010 .... 0111 1111 1111 1011 OTR 1 0 0 0 0 0 0 0 0 0 0 0 0 0 INP-INM (V) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 24 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Output codes versus input voltage …continued Offset binary 1111 1111 1111 1100 1111 1111 1111 1101 1111 1111 1111 1110 1111 1111 1111 1111 1111 1111 1111 1111 Two’s complement 0111 1111 1111 1100 0111 1111 1111 1101 0111 1111 1111 1110 0111 1111 1111 1111 0111 1111 1111 1111 OTR 0 0 0 0 1 Table 13. INP-INM (V) +0.99990845 +0.99993896 +0.99996948 +1 > +1 13.6 Serial Peripheral Interface (SPI) 13.6.1 Register description The ADC1613D serial interface is a synchronous serial communications port allowing for easy interfacing with many industry microprocessors. It provides access to the registers that control the operation of the chip in both read and write modes. This interface is configured as a 3-wire type (SDIO as bidirectional pin). SCLK acts as the serial clock, and CS acts as the serial chip select bar. Each read/write operation is sequenced by the CS signal and enabled by a LOW level to to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte (see Table 14). Table 14. Bit Description Instruction bytes for the SPI MSB 7 R/W[1] A7 [1] LSB 6 W1 A6 5 W0 A5 4 A12 A4 3 A11 A3 2 A10 A2 1 A9 A1 0 A8 A0 R/W indicates whether a read or write transfer occurs after the instruction byte Table 15. R/W[1] 0 1 [1] Read or Write mode access description Description Write mode operation Read mode operation Bits W1 and W0 indicate the number of bytes transferred after the instruction byte. Table 16. W1 0 0 1 1 Number of bytes to be transferred W0 0 1 0 1 Number of bytes 1 byte transferred 2 bytes transferred 3 bytes transferred 4 or more bytes transferred Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is incremented to access subsequent addresses. ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 25 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface The steps involved in a data transfer are as follows: 1. The falling edge on CS in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can be vary in length but will always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes): CSB SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction bytes Register N (data) Register N + 1 (data) 005aaa086 Fig 23. Transfer diagram for two data bytes (3-wire type) 13.6.2 Channel control The two ADC channels can be configured at the same time or separately. By using the register “Channel index”, the user can choose which ADC channel will receive the next SPI-instruction. By default the channel A and B will receive the same instructions in write mode. In read mode only A is active. ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 26 of 43 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Preliminary data sheet Rev. 02 — 23 April 2010 27 of 43 ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors Table 17. Addr Hex Register allocation map R/W[1] Bit definition Bit 7 Bit 6 SW_RST Bit 5 Bit 4 SE_SEL Bit 3 DIFF_SE INTREF_EN DIG_OFFSET[5:0] TESTPAT_2[13:6] TESTPAT_3[5:0] TESTPAT_1[2:0] Bit 2 Bit 1 ADCB PD[1:0] CLKDIV2_SEL INTREF[2:0] DCS_EN Bit 0 ADCA Default[2] Bin Register name ADC control register 0003 0005 0006 0008 0013 0014 0015 0016 Channel index R/W 1111 1111 0000 0000 0000 000X 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RESERVED 0000 0000 0 0000 0000 0000 **** 0100 1001 SWAP_ ADC_0_1 0000 00** 0000 00** 0000 0000 1111 1111 0 PRBS_TYPE[1:0] 0000 0000 1110 1101 Reset and R/W Operating modes Clock Vref Offset Test pattern 1 Test pattern 2 Test pattern 3 R/W R/W R/W R/W R/W R/W JESD204A control 0801 0802 0803 0805 0806 0808 0809 080A 080B 0820 Ser_Status Ser_Reset Ser_Cfg_Setup Ser_Control1 Ser_Control2 Ser_Analog_Ctrl Ser_ScramblerA Ser_ScramblerB Ser_PRBS_Ctrl Cfg_0_DID R R/W R/W R/W R/W R/W R/W R/W R/W R/W* 0 0 0 0 RXSYNC_ ERROR SW_RST 0 0 0 0 0 0 0 RESERVED[2:0] 0 0 0 0 SYNC_SING LEENDED 0 0 1 0 0 LSB_INIT[6:0] MSB_INIT[7:0] 0 DID[7:0] 0 0 FSM_SW_ RST 0 0 POR_TST 0 ADC1613D series; serial JESD204A interface CFG_SETUP[3:0] RESERVED[2:0] SWAP_ LANE_1_2 SWING_SEL[2:0] ADC1613D series TriState_ SYNC_POL CFG_PAD 0 0 0 0 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 17. Addr Hex 0821 0822 0823 0824 0825 0826 0827 0828 0829 082C 082D 084C 084D 0870 0871 0890 0891 [1] [2] All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Register allocation map …continued R/W[1] Bit definition Bit 7 Bit 6 0 0 0 0 0 CS[0] 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 0 0 FCHK[7:0] FCHK[7:0] 0 0 0 0 SCR_IN_ MODE SCR_IN_ MODE 0 0 LANE_MODE[1:0] LANE_MODE[1:0] ADC_MODE[1:0] ADC_MODE[1:0] 0 0 0 0 LANE_ POL LANE_ POL 0 0 LANE_CLK_ POS_EDGE LANE_CLK_ POS_EDGE 0 0 LANE_PD LANE_PD ADC_PD ADC_PD 0 0 0 0 0 0 NP[4:0] 0 0 LID[4:0] LID[4:0] 0 CF[1:0] S 0 Bit 4 0 0 0 0 0 K[4:0] 0 N[3:0] 0 M 0 Bit 3 Bit 2 Bit 1 BID[3:0] 0 F[2:0] L Bit 0 R/W* R/W* R/W* R/W* R/W* R/W* R R/W* R/W* R/W* R/W* 0 SCR 0 0 0 0 0 0 HD 0 0 Default[2] Bin 0000 1010 *000 000* 0000 0*** 000* **** 0000 000* 0100 0*** 0000 1111 0000 0000 *000 0000 0001 1011 0001 1100 **** **** **** **** 0000 000* Preliminary data sheet Rev. 02 — 23 April 2010 28 of 43 ADC1613D_SER_2 NXP Semiconductors Register name Cfg_1_BID Cfg_3_SCR_L Cfg_4_F Cfg_5_K Cfg_6_M Cfg_7_CS_N Cfg_8_Np Cfg_9_S Cfg_10_HD_CF Cfg_01_2_LID Cfg_02_2_LID Cfg01_13_FCHK R Cfg02_13_FCHK R LaneA_0_Ctrl LaneB_0_Ctrl ADCA_0_Ctrl ADCB_0_Ctrl R/W R/W R/W R/W ADC1613D series; serial JESD204A interface 0000 000* 0000 000* 0000 000* ADC1613D series an "*" in the Access column means that this register is subject to control access conditions in Write mode. an "*" in the Default column replaces a bit of which the value depends on the binary level of external pins (e.g. CFG[3:0], Swing[1:0], Scrambler). NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 13.6.3 Register description 13.6.3.1 Table 18. Bit 7 to 2 1 ADCB ADC control registers Register channel Index (address 0003h) Access R/W 0 1 Value 111111 Description not used ADCB will get the next SPI command: ADCB not selected ADCB selected ADCA will get the next SPI command: 0 1 ADCA not selected ADCA selected Symbol 0 ADCA R/W Table 19. Bit 7 Register reset and Power-down mode (address 0005h) Access R/W 0 1 Value Description reset digital part: no reset performs a reset of the digital part not used power-down mode: 00 01 10 11 normal (power-up) full power-down sleep normal (power-up) Symbol SW_RST 6 to 2 1 to 0 PD[1-0] R/W 00000 Table 20. Bit 7 to 5 4 - Register clock (address 0006h) Access R/W 0 1 Value 000 Description not used select SE clock input pin: Select CLKM input Select CLKP input differential/single ended clock input select: 0 1 Fully differential Single-ended not used select clock input divider by 2: 0 1 disable active duty cycle stabilizer enable: 0 1 disable active Symbol SE_SEL 3 DIFF_SE R/W 2 1 CLKDIV2_SEL R/W 0 0 DCS_EN R/W ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 29 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Table 21. Bit 7 to 4 3 - Register Vref (address 0008h) Access R/W 0 1 Value 0000 Description not used enable internal programmable VREF mode: disable active programmable internal reference: 000 001 010 011 100 101 110 111 0 dB (FS=2 V) −1 dB (FS=1.78 V) −2 dB (FS=1.59 V) −3 dB (FS=1.42 V) −4 dB (FS=1.26 V) −5 dB (FS=1.12 V) −6 dB (FS=1 V) not used Symbol INTREF_EN 2 to 0 INTREF[2:0] R/W Table 22. Decimal +31 ... 0 ... −32 Table 23. Bit 7 to 3 2 to 0 - Digital offset adjustment (address 0013h) DIG_OFFSET[5:0] 011111 ... 000000 ... 100000 Register test pattern 1 (address 0014h) Access R/W 000 001 010 011 100 101 110 111 Value 00000 Description not used digital test pattern: off mid-scale − FS + FS toggle ‘1111..1111’/’0000..0000’ custom test pattern, to be written in register 0015h and 0016h ‘010101...’ ‘101010...’ +31 LSB ... 0 ... −32 LSB Register offset: (address 0013h) Symbol TESTPAT_1[2:0] Table 24. Bit 7 to 0 Register test pattern 2 (address 0015h) Symbol TESTPAT_2[13:6] Access R/W Value Description 00000000 custom digital test pattern (bit 13 to 6) ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 30 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Table 25. Bit 7 to 3 2 to 0 Register test pattern 3 (address 0016h) Access R/W Value 00000 000 Description custom digital test pattern (bit 5 to 0) not used Symbol TESTPAT_3[5:0] - 13.6.4 JESD204A digital control registers Table 26. Bit 7 6 to 4 3 to 2 1 0 SER status (address 0801h) Access R/W ? Value 0 110 0 0 Description set to 1 when a synchronization error occurs reserved not used power-on-reset reserved Symbol RXSYNC_ERROR RESERVED[2:0] POR_TST RESERVED Table 27. Bit 7 6 to 4 3 2 to 0 SER reset (address 0802h) Access R/W R/W Value 0 000 0 000 Description initiates a software reset of the JEDEC204A unit not used initiates a software reset of the internal state machine of JEDEC204A unit not used Symbol SW_RST FSM_SW_RST - ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 31 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Table 28. Bit 7 to 4 3 to 0 - SER cfg set-up (address 0803h)[1] Access R R/W Value 0000 0000 (reset) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 to 1101 1110 1111 Description not used defines quick JESD204A configuration. These settings overrule the CFG_PAD configuration ADC0: ON; ADC1: ON; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9; M = 2; L = 2[2] ADC0: ON; ADC1: ON; Lane0: ON; Lane1: OFF; F = 4; HD = 0; K = 5; M = 2; L = 1[2] ADC0: ON; ADC1: ON; Lane0: OFF; Lane1: ON; F = 4; HD = 0; K = 5; M = 2; L = 1 SWAP_LANE_1_2 = 1[2] ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17; M = 1; L = 2[2] ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17; M = 1; L = 2; SWAP_ADC_0_1 = 1[2] ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9; M = 1; L = 1[2] ADC0: ON; ADC1: OFF; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9; M = 1; L = 1; SWAP_LANE_1_2 = 1[2] ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9; M = 1; L = 1; SWAP_ADC_0_1 = 1[2] ADC0: OFF; ADC1: ON; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9; M = 1; L = 1; SWAP_ADC_0_1[2] reserved ADC0: OFF; ADC1: OFF; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9; M = 2; L = 2; loop alignment = 1[2] ADC0: OFF; ADC1: OFF; Lane0: OFF; Lane1: OFF; F = 2; HD = 0; K = 9; M = 2; L = 2 → PD[2] Symbol CFG_SETUP[3:0] [1] [2] The default value for this register depends on the external pull-up/pull-down on CFG0, CFG1, CFG2 or CFG3. Writing to the register overwrites this value. F: number of byte per frame; HD: High density; K: number of frames per multi frame; M: number of converters; L: number of lanes See the information about the JESD204A standard on the JEDEC web site. Table 29. Bit 7 6 5 TRISTATE_CFG_PAD SYNC_POL SER control1 (address 0805h) Access R R/W R/W 0 1 4 SYNC_SINGLE_ENDED R/W 0 1 3 R 1 Value 0 1 Description not used CFG pads (3 to 0) are set to high-impedance. Switch to 0 automatically after start-up or reset. defines the sync signal polarity: synchronization signal is active low synchronization signal is active high defines the input mode of the sync signal: synchronization input mode is set in Differential mode synchronization input mode is set in Single-ended mode not used Symbol ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 32 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Table 29. Bit 2 SER control1 (address 0805h) …continued Access 0 1 LSB are swapped to MSB at the scrambler input enables swapping bits at the 8b/10b encoder input: 0 1 LSB are swapped to MSB at the 8b/10b encoder input enables swapping bits at the lane input (before serializer): 0 1 LSB are swapped to MSB at the lane input Value Description enables swapping bits at the scrambler input Symbol REV_SCR 1 REV_ENCODER - 0 REV_SERIAL - Table 30. Bit 7 to 2 1 - SER control2 (address 0806h) Access R R/W 0 1 outputs of the JESD204A unit are swapped. (Output0 is connected to Lane1, Output1 is connected to Lane0) controls the JESD204A input multiplexer: 0 1 inputs of the JESD204A unit are swapped. (ADC0 output is connected to Input1, ADC1 is connected to Input0) Value 000000 Description not used controls the JESD204A output multiplexer: Symbol SWAP_LANE_1_2 0 SWAP_ADC_0_1 R/W Table 31. Bit 7 to 3 2 to 0 - SER analog ctrl (address 0808h) Access R R/W Value 00000 0** Description not used defines the swing output for the lane pads Symbol SWING_SEL[2:0] Table 32. Bit 7 6 to 0 - SER scramblerA (address 0809h) Access R R/W Value 0 0000000 Description not used defines the initialization vector for the scrambler polynomial (lower) Symbol LSB_INIT[6:0] Table 33. Bit 7 to 0 SER scramblerB (address 080Ah) Access R/W Value 11111111 Description defines the initialization vector for the scrambler polynomial (upper) Symbol MSB_INIT[7:0] ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 33 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Table 34. Bit 7 to 2 1 to 0 - SER PRBS Ctrl (address 080Bh) Access R R/W 00 (reset) 01 10 11 Value 000000 Description not used defines the type of Pseudo-Random Binary Sequence (PRBS) generator to be used: PRBS-7 PRBS-7 PRBS-23 PRBS-31 Symbol PRBS_TYPE[1:0] Table 35. Bit 7 to 0 Cfg_0_DID (address 0820h) Access R Value Description 11101101 defines the device (= link) identification number Symbol DID[7:0] Table 36. Bit 7 to 4 3 to 0 - Cfg_1_BID (address 0821h) Access R R/W Value 0000 1010 Description not used defines the bank ID – extension to DID Symbol BID[3:0] Table 37. Bit 7 6 to 1 0 Cfg_3_SCR_L (address 0822h) Access R/W R R/W Cfg_4_F (address 0823h) Access R R/W Value 00000 *** Description not used defines the number of octets per frame, minus 1 Value * 000000 * Description scrambling enabled not used defines the number of lanes per converter device, minus 1 Symbol SCR L Table 38. Bit 7 to 3 2 to 0 - Symbol F[2:0] Table 39. Bit 7 to 5 4 to 0 - Cfg_5_K (address 0824h) Access R R/W Value 000 ***** Description not used defines the number of frames per multiframe, minus 1 Symbol K[4:0] Table 40. Bit 7 to 1 0 M Cfg_6_M (address 0825h) Access R R/W Value 0000000 * Description not used defines the number of converters per device, minus 1 Symbol ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 34 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Table 41. Bit 7 6 5 to 4 3 to 0 - Cfg_7_CS_N (address 0826h) Access R R/W R R/W Value 0 * 00 **** Description not used defines the number of control bits per sample, minus 1 not used defines the converter resolution Symbol CS[0] N[3:0] Table 42. Bit 7 to 5 4 to 0 - Cfg_8_Np (address 0827h) Access R R/W Value 000 ***** Description not used defines the total number of bits per sample, minus 1 Symbol NP[4:0] Table 43. Bit 7 to 1 0 S Cfg_9_S (address 0828h) Access R R/W Value 0000000 1 Description not used defines number of samples per converter per frame cycle Symbol Table 44. Bit 7 6 to 2 1 to 0 HD - Cfg_10_HD_CF (address 0829h) Access R/W R R/W Value * 00000 ** Description defines high density format not used defines number of control words per frame clock cycle per link. Symbol CF[1:0] Table 45. Bit 7 to 5 4 to 0 - Cfg01_2_LID (address 082Ch) Access R R/W Value 000 11011 Description not used defines lane1 identification number Symbol LID[4:0] Table 46. Bit 7 to 5 4 to 0 - Cfg02_2_LID (address 082Dh) Access R R/W Value 000 11100 Description not used defines lane2 identification number Symbol LID[4:0] Table 47. Bit 7 to 0 Cfg02_13_fchk (address 084Ch) Access R Value ******** Description defines the checksum value for lane1 checksum corresponds to the sum of all the link configuration parameters modulo 256 (as defined in JEDEC Standard No.204A) Symbol FCHK[7:0] ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 35 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Table 48. Bit 7 to 0 Cfg01_13_fchk (address 084Dh) Access R Value ******** Description defines the checksum value for lane1 checksum corresponds to the sum of all the link configuration parameters module 256 (as defined in JEDEC Standard No.204A) Symbol FCHK[7:0] Table 49. Bit 7 6 - LaneA_0_ctrl (address 0870h) Access R R/W 0 (reset) 1 Value 0 Description not used defines the input type for scrambler and 8-bit/10-bit units: (normal mode) = Input of the scrambler and 8-bit/10-bit units is the output of the frame assembly unit. input of the scrambler and 8-bit/10-bit units is the PRSB generator (PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl register) defines output type of Lane output unit: 00 (reset) 01 10 11 normal mode: Lane output is the 8-bit/10-bit output unit constant mode: Lane output is set to a constant (0 × 0) toggle mode: Lane output is toggling between 0 × 0 and 0 × 1 PRBS mode: Lane output is the PRSB generator (PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl register) not used defines lane polarity: 0 1 lane polarity is normal lane polarity is inverted defines lane clock polarity: 0 1 lane clock provided to the serializer is active on positive edge lane clock provided to the serializer is active on negative edge lane power-down control: 0 1 lane is operational lane is in Power-down mode Symbol SCR_IN_MODE 5 to 4 LANE_MODE[1:0] R/W 3 2 LANE_POL R R/W 0 1 LANE_CLK_POS_EDGE R/W 0 Lane_PD R/W Table 50. Bit 7 6 - LaneB_0_ctrl (address 0871h) Access R R/W 0 (reset) 1 Value 0 Description not used defines the input type for scrambler and 8b/10b units: (normal mode) = Input of the scrambler and 8b/10b units is the output of the Frame Assembly unit. input of the scrambler and 8b/10b units is the PRSB generator (PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl register) Symbol SCR_IN_MODE ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 36 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Table 50. Bit 5 to 4 LaneB_0_ctrl (address 0871h) …continued Access R/W 00 (reset) 01 10 11 Value Description defines output type of lane output unit: normal mode: Lane output is the 8b/10b output unit constant mode: Lane output is set to a constant (0x0) toggle mode: Lane output is toggling between 0x0 and 0x1 PRBS mode: Lane output is the PRSB generator (PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl register) not used defines lane polarity: 0 1 lane polarity is normal lane polarity is inverted defines lane clock polarity: 0 1 lane clock provided to the serializer is active on positive edge lane clock provided to the serializer is active on negative edge lane power-down control: 0 1 lane is in Power-down mode Symbol LANE_MODE[1:0] 3 2 LANE_POL R R/W 0 1 LANE_CLK_POS_EDGE R/W 0 Lane_PD R/W Table 51. Bit 7 to 6 5 to 4 - ADCA_0_ctrl (address 0890h) Access R R/W 00 (reset) 01 10 11 Value 00 Description not used defines input type of JESD204A unit: ADC output is connected to the JESD204A input Not used JESD204A input is fed with a dummy constant, set to: ADC[15:0] = “1001101110101000” JESD204A is fed with a PRBS generator (PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl register) not used ADC power-down control: 0 1 ADC is operational ADC is in Power-down mode Symbol ADC_MODE[1:0] 3 to 1 0 ADC_PD R R/W 000 ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 37 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface Table 52. Bit 7 to 6 5 to 4 - ADC02_0_ctrl (address 0891h) Access R R/W 01 10 11 Value 00 Description not used defines input type of JESD204A unit 00 (reset) ADC output is connected to the JESD204A input not used JESD204A input is fed with a dummy constant, set to: ADC[15:0] = “1001101110101000” JESD204A is fed with a PRBS generator (PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl register) not used ADC power-down control: 0 1 ADC is operational ADC is in Power-down mode Symbol ADC_MODE[1:0] 3 to 1 0 ADC_PD R R/W 000 ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 38 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 14. Package outline HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm SOT684-7 D B A terminal 1 index area E A A1 c detail X e1 e L 15 14 1/2 e b 28 29 e v w CAB C y1 C C y Eh 1/2 e e2 1 terminal 1 index area 56 Dh 43 42 X 0 Dimensions Unit mm A(1) A1 b c 0.2 D(1) 8.1 8.0 7.9 Dh 5.95 5.80 5.65 E(1) 8.1 8.0 7.9 Eh 6.55 6.40 6.25 e 0.5 2.5 scale e1 6.5 e2 6.5 5 mm L 0.5 0.4 0.3 v 0.1 w y y1 0.1 max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT684-7 References IEC --JEDEC MO-220 JEITA --European projection sot684-7_po Issue date 08-11-19 09-03-04 Fig 24. Package outline SOT684-1 (HVQFN56) ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 39 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 15. Revision history Table 53. Revision history Release date 20100423 Data sheet status Preliminary data sheet Objective data sheet Change notice Supersedes ADC1613D_SER_1 Document ID ADC1613D_SER_2 Modifications: ADC1613D_SER_1 • Product status changed from Objective to Preliminary 20100413 ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 40 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. © NXP B.V. 2010. All rights reserved. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 02 — 23 April 2010 41 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC1613D_SER_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 23 April 2010 42 of 43 NXP Semiconductors ADC1613D series ADC1613D series; serial JESD204A interface 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Thermal characteristics . . . . . . . . . . . . . . . . . . 6 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 11 Clock and digital output timing . . . . . . . . . . . 12 11.1 Serial output timings . . . . . . . . . . . . . . . . . . . 13 12 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 13 Application information. . . . . . . . . . . . . . . . . . 15 13.1 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 15 13.1.1 Input stage description . . . . . . . . . . . . . . . . . . 15 13.1.2 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 15 13.1.3 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13.2 System reference and power management . . 17 13.2.1 Internal/external reference . . . . . . . . . . . . . . . 17 13.2.2 Reference gain control . . . . . . . . . . . . . . . . . . 19 13.2.3 Common-mode output voltage (VI(cm)) . . . . . . 20 13.2.4 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 13.3 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 13.3.1 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 20 13.3.2 Equivalent input circuit . . . . . . . . . . . . . . . . . . 21 13.3.3 Clock input divider . . . . . . . . . . . . . . . . . . . . . 22 13.3.4 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 22 13.4 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 22 13.4.1 Serial output equivalent circuit . . . . . . . . . . . . 22 13.5 JESD204A serializer. . . . . . . . . . . . . . . . . . . . 23 13.5.1 Digital JESD204A formatter . . . . . . . . . . . . . . 23 13.5.2 ADC core output codes versus input voltage . 24 13.6 Serial Peripheral Interface (SPI) . . . . . . . . . . . 25 13.6.1 Register description . . . . . . . . . . . . . . . . . . . . 25 13.6.2 Channel control . . . . . . . . . . . . . . . . . . . . . . . 26 13.6.3 Register description . . . . . . . . . . . . . . . . . . . . 29 13.6.3.1 ADC control registers . . . . . . . . . . . . . . . . . . . 29 13.6.4 JESD204A digital control registers . . . . . . . . . 31 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 40 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 41 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 16.2 16.3 16.4 17 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 41 42 42 43 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 April 2010 Document identifier: ADC1613D_SER_2