ASL3416SHNY

ASL3416SHN Enhanced three channel LED buck driver Rev. 6 — 16 September 2019 Product data sheet 1. Introduction The ASL3416SHN is a three channel buck mode LED driver IC delivering constant average DC current to LEDs independent of the input voltage. The ASL3416SHN supports up to three output channels. It means that with one driver IC 1, 2 or 3 LED strings can be driven independently of each other. It provides a cost effective design solution, specifically targeting automotive exterior and interior lighting applications. 2. General description The ASL3416SHN has a hysteretic buck DC-to-DC topology. With input voltages from 10 V to 80 V, it allows maximum flexibility on output voltages for each channel, enabling applications with up to 20 LEDs. It also provides an output current of up to and above 1.5 A per channel.1 Furthermore, two output channels can be connected together to provide an even higher current. It drives an external high-side N channel MOSFET from an internally regulated adjustable supply. The ASL3416SHN buck driver gives a flexible system design which can be used to drive three LED strings with the same architecture. The ASL3416SHN provides an SPI interface for extensive control and diagnostic communication with an external microcontroller. The ASL3416SHN offers an adjustable hysteresis for optimizing external components as well as minimizing LED current ripple. In addition, the ASL3416SHN provides an output voltage of up to 70 V. It has a measurement capability that can be used to identify LED open or short circuit conditions. The microcontroller can read this voltage and use it to detect open or short circuit conditions. There are also additional diagnostic features such as current reached status. Additional features include input under-voltage lockout and thermal shutdown when the junction temperature of the ASL3416SHN exceeds +175 C. It is housed in a very small HVQFN32 pin package with an exposed thermal pad and is designed to meet the stringent requirements of automotive applications. It is fully AEC Q100 grade 1 qualified. It operates over the ambient automotive temperature range of 40 C to +125 C. 1. The ASL3416 provides an accurate current over a 1 : 12.5 range. This range can be scaled up or down using external components. Depending on the operating conditions and component choices, output currents of min 30 mA and more than 3 A can be achieved. ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 3. Features and benefits                       The ASL3416SHN is an automotive grade product that is AEC-Q100 grade 1 qualified. Operating ambient temperature range of 40 C to +125 C Wide operating input voltage range from +10 V to +80 V Able to drive up to 20 LEDs, wide operating LED voltage range regulated from 2.5 V to 70 V Output current of up to and above 1.5 A with high LED current accuracy of 5 % over the complete operating temperature range Output current programmable via SPI interface Read back programmed current via SPI Two output current ranges, programmable via SPI interface with 5 % accuracy Hysteretic converter Fast gate drive for high efficiency Programmable internal gate driver voltage regulator Support logic level and standard level FETs Integrated bootstrap diode PWM inputs for individual dimming of each channel Low Electro Magnetic Emission (EME) and high Electro Magnetic Immunity (EMI) Input voltage monitoring and input undervoltage protection Output voltage monitoring Control signal to enable the device Junction temperature monitoring via SPI Small package outline HVQFN32 Low quiescent current < 5A at 25 C when EN = 0 Short-circuit and open-circuit output protection 4. Applications  Automotive LED lighting  Daytime running lights  Position or park light  Low beam  High beam  Turn indicator  Fog light  Cornering light  Advanced front lighting ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 2 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 5. Ordering information Table 1. Ordering information Type number Package ASL3416SHN Name Description Version HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; SOT617-12 body 5  5  0.85 mm 6. Block diagram VDDA VDDD VGG UVOV GATE DRIVER 1 ERROR AMP AND CONTROL LOOP 1 POR Gate Driver 1 Signal VIN GATE DRIVER 2 OSCILLATOR ERROR AMP AND CONTROL LOOP 2 Gate Driver 2 Signal VCC PWM SDO EN SCLK SPI INTERFACE DIGITAL CONTROL LOGIC GATE DRIVER 3 ERROR AMP AND CONTROL LOOP 3 CSB SDI Gate Driver 3 Signal MISC, MTP GND aaa-017007 Fig 1. Block diagram ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 3 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 7. Pinning information 25 LX1 26 G1 27 BS1 28 n.c. 29 VGG 30 n.c. terminal 1 index area 31 VIN 32 n.c. 7.1 Pinning GND 1 24 RH1 SDO 2 23 RL1 VCC 3 22 n.c. EN 4 21 LX2 ASL3416SHN CSB 5 20 G2 SCLK 6 19 BS2 SDI 7 PWM3 8 18 RH2 GND LX3 16 G3 15 BS3 14 RH3 13 RL3 12 n.c. 11 PWM1 10 PWM2 9 17 RL2 aaa-018555 Transparent top view Fig 2. Pin configuration 7.2 Pin description ASL3416SHN Product data sheet Table 2. Pin description[1] Symbol Pin Description GND 1 chip ground SDO 2 SPI data out VCC 3 external 5 V supply EN 4 enable signal CSB 5 SPI chip select SCLK 6 SPI clock SDI 7 SPI data input PWM3 8 external PWM signal channel 3 PWM2 9 external PWM signal channel 2 PWM1 10 external PWM signal channel 1 n.c. 11 not connected RL3 12 sense resistor low side channel 3 RH3 13 sense resistor high side channel 3 BS3 14 boot supply channel 3 G3 15 channel 3 gate driver LX3 16 inductor connection to switching FET channel 3 All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 4 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver Table 2. Pin description[1] …continued Symbol Pin Description RL2 17 sense resistor low side channel 2 RH2 18 sense resistor high side channel 2 BS2 19 boot supply channel 2 G2 20 channel 2 gate driver LX2 21 inductor connection to switching FET channel 2 n.c. 22 not connected RL1 23 sense resistor low side channel 1 RH1 24 sense resistor high side channel 1 LX1 25 inductor connection to switching FET channel 1 G1 26 channel 1 gate driver BS1 27 boot supply channel 1 n.c. 28 not connected VGG 29 gate driver supply n.c. 30 not connected VIN 31 input voltage n.c. 32 not connected [1] Not connected (n.c.) pins are internally not connected and must be left floating to maintain high-voltage separation. For enhanced thermal and electrical performance, the exposed center pad of the package should be soldered to board ground (and not to any other voltage level). ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 5 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 8. Functional description 8.1 Operating modes EN = low Initial state EN = high EN = low Off VIN < VIN_UV Under voltage Operation VIN > VIN_UV EN = low Clr_errors = 1 Tj > Tsd(otp) or VGG_err = 1 Tj > Tsd(otp) EN = low Fail silent aaa-018556 Note: All outputs should be turned off at least 200 ns before the transition from operation to off mode is executed Fig 3. State diagram 8.1.1 Off mode If the input voltage drops below the power-off detection threshold (Vth(det)poff) or the EN pin is low, the ASL3416SHN switches to off mode. In Off mode, the SPI interface and all outputs are turned off. Before Off mode is entered, all channels should be turned off. 8.1.2 Operation mode The ASL3416SHN switches from Off mode to Operation mode when the input voltage is above the power-on detection threshold (Vth(det)pon) and the EN pin is high. In Operation mode, all outputs are available as configured via the SPI interface. 8.1.3 Undervoltage mode The ASL3416SHN switches from Operation mode to Undervoltage mode as soon as the input voltage drops below the programmed voltage. In Undervoltage mode, all outputs, including the gate voltage supply are off. 8.1.4 Fail silent mode The ASL3416SHN switches from Operation mode to Fail silent mode, when the junction temperature exceeds the over temperature shutdown threshold or a gate driver error is detected. ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 6 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver In Fail silent mode, all outputs are turned off and only the SPI interface remains operational. 8.2 Buck converter The ASL3416SHN is a buck converter IC delivering constant current to the LEDs. It is a hysteretic controller that regulates the inductor current. It switches off the external FET when the inductor current rises above the upper threshold current. It switches on when the current falls below the lower threshold. The width of the hysteresis window can be programmed via SPI to keep the switching frequency between bounds. The anode of the LED string is connected to the driver, while the cathode of the LED string is connected to ground. This arrangement helps to reduce the total number of connections to the LEDs. 8.3 Input voltage measurement The ASL3416SHN measures the supply voltage of the device and makes this measurement available via the SPI interface. Table 3. VIN voltage measurement register, address 0x38h[1] Bit Symbol Description Value Function 7:0 V_VIN[7:0] VIN voltage measurement 0x00h voltage measurement not available ... VIN voltage = 0.3548  V_VIN[7:0]  0.56 V [1] A write to the VIN voltage measurement register does not set the SPI error bit high. 8.4 Input undervoltage detection The ASL3416SHN offers a variable undervoltage detection threshold. When the supply voltage is above the undervoltage detection threshold, the bit VIN_stat is high, when the supply voltage is below, the bit is low. For effects of this bit on the functionality of the device, see Section 8.12.1.1. Table 4. Undervoltage threshold register, address 0x0Fh Bit Symbol Description Value Function 7:0 V_VIN_UV[7:0] undervoltage threshold 0x00h undervoltage detection threshold = 0 V ... undervoltage detection threshold = 0.3548  V_VIN_UV[7:0]  0.56 V 8.5 Output current programmability The ASL3416SHN provides the possibility to program the LED current and LED current hysteresis via the SPI interface. 8.5.1 Output target current programming The target output current of the ASL3416SHN can be programmed via the LED current range registers and the LED current registers of channel 1, channel 2 and channel 3. The sense voltage that is set via SPI, and the value of the external sense resistor, determine the actual level. V LEDcurrent I LED = ---------------------------R sense ASL3416SHN Product data sheet (1) All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 7 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver Table 5. Bit LED current range register, address 0x05h Symbol 7:3 2 1 0 I_CH3 I_CH2 I_CH1 Table 6. Description Value Function reserved 000000 reserved; keep clear for future use LED current range bit 0 channel 3 1 maximum sense voltage is approximately 300 mV LED current range bit 0 channel 2 1 maximum sense voltage is approximately 300 mV LED current range bit 0 channel 1 1 maximum sense voltage is approximately 300 mV maximum sense voltage is approximately 120 mV maximum sense voltage is approximately 120 mV maximum sense voltage is approximately 120 mV LED current channel 1 register, address 0x02h Bit Symbol Description Value Function 7:0 I_LED_CH1[7:0] LED current channel 1 0x00h; 0xF6h...0xFFh not recommended ... When I_CH1 is 0: 1.179 mV  I_LED_CH1 + 0.74 mV When I_CH1 is 1: 0.47882 mV  I_LED_CH1  0.6 mV Table 7. LED current channel 2 register, address 0x03h Bit Symbol Description Value Function 7:0 I_LED_CH2[7:0] LED current channel 2 0x00h; 0xF6h...0xFFh not recommended ... When I_CH2 is 0: 1.179 mV  I_LED_CH2 + 0.74 mV When I_CH2 is 1: 0.47882 mV  I_LED_CH2  0.6 mV Table 8. LED current channel 3 register, address 0x04h Bit Symbol Description Value Function 7:0 I_LED_CH3[7:0] LED current channel 3 0x00h; 0xF6h...0xFFh not recommended ... When I_CH3 is 0: 1.179 mV  I_LED_CH3 + 0.74 mV When I_CH3 is 1: 0.47882 mV  I_LED_CH3  0.6 mV The LED current is the result of the voltage drop across the Rsense resistor in mV. Example: To achieve an output current of e.g. 300 mA with 200 m Rsense resistor on channel 1, two settings are possible: 1. Set bit I_CH1 to 1 and the LED current channel 1 register to 0x7Eh 2. Set bit I_CH1 to 0 and the LED current channel 1 register to 0x32h For higher granularity and higher accuracy, use setting 1. When the LED current is dynamically adjusted to higher levels than offered when bit I_CHx = 1, deviations are possible. ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 8 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 8.5.2 Hysteresis programming via SPI ASL3416SHN provides an option to program the level of hysteresis via the SPI interface. The hysteresis setting is independent of the I_CH1, I_CH2 and I_CH3 bits in LED current range registers. The hysteresis voltage that is set via SPI, and the value of the external sense resistor, determine the actual level. V Hyst I Hyst = --------------R sense (2) The switching frequency varies depending on the hysteresis level, the values of the external components, and the input and the output voltages. The ASL3416SHN is specified for switching frequencies from 100 kHz to 2 MHz. Note: For all hysteresis settings, the hysteresis, specified in mV, corresponds with the lowest average LED current in the static characteristics section. Table 9. Bit Hysteresis channel 1 register, address 0x0Bh Symbol 7:2 1:0 HCH1[1:0] Table 10. Bit Symbol HCH2[1:0] Table 11. Bit Function reserved 000000 reserved; keep clear for future use hysteresis channel 1 00 setting 0 01 setting 1 10 setting 2 11 setting 3 Description Value Function reserved 000000 reserved; keep clear for future use hysteresis channel 2 00 setting 0 01 setting 1 10 setting 2 11 setting 3 Hysteresis channel 3 register, address 0x0Dh Symbol 7:2 1:0 Value Hysteresis channel 2 register, address 0x0Ch 7:2 1:0 Description HCH3[1:0] ASL3416SHN Product data sheet Description Value Function reserved 000000 reserved; keep clear for future use hysteresis channel 3 00 setting 0 01 setting 1 10 setting 2 11 setting 3 All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 9 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver By increasing the hysteresis level, the switching frequency is reduced, leading to less switching events and consequently lower overall switching losses. However, the ripple of the LED current increases. Calculation example: A system has 40 V input voltage, an LED voltage of 15 V, a 200 m Rsense, and an inductor of 220 H. It operates with a hysteresis of 20 mV at: 2 V IN  V LED – V LED 1 1 1 f = --- = ----------------------- = ------------------------------------------------------------------------------- = -----------------------------------------------  426 kHz T T on + T off L L I Hyst  L  V IN I Hyst  --------------------------- + I Hyst  ------------V IN – V LED V LED (3) Remarks: The calculation above does not account for delays in the switching. Due to these delays, the measured switching frequency is lower than calculated here. To avoid that the device is operating with undesired settings, pull the PWM pin high only when a channel is completely configured. In case the PWM functionality is not needed, it is possible to connect the PWM pin directly to pin VCC. In this case, the PWM pin control bits can be used to enable or disable the channel. To avoid operation at an undesired frequency, the hysteresis for the channel should be set before the LED current register is set. The hysteresis and LED current level can be adapted during operation of the device to enable smooth fade-in/fade-out scenarios down to very low output currents. It does it in combination with the PWM inputs. ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 10 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 8.5.3 Overcurrent protection The ASL3416SHN offers an overcurrent protection feature in addition to the set trip points to protect the system. If the output voltage suddenly changes very fast, the upper and lower hysteretic thresholds may deviate from actual target values. In case the deviation is too large the built-in overcurrent protection feature prevents the system from excessive current build-up. In case such an event is detected, the gate driver will immediately be turned off for approximately 16 ms after which the system is restarted. 8.5.4 Output diagnostics The diagnostic options for the outputs are: • measurement of the output voltages during the LED on and off state - details can be found in Section 8.6 • indication that the target LED current is reached - details can be found in Section 8.11 • indication that a channel is operating with low voltage headroom - details can be found in Section 8.12.3.1 8.6 Output voltage measurement The ASL3416SHN measures the output voltage of all channels every tmeas. On a transition from the PWM pin of a channel, the measurement results are stored in the corresponding registers. The registers V_LEDx_on, contain the voltage information when the PWM input of the channel is high. The registers V_LEDx_off, contain the voltage information when the PWM input is low. It ensures that the registers contain the latest measured value of the individual channels with respect to the status of the PWM pin. If the PWM input of one channel stays constant for tmeas(LED), the V_LEDx_on voltage register and the V_LEDx_off voltage register of this channel are updated. Table 12. LED on voltage channel 1 register, address 0x20h Bit Symbol Description Value 7:0 V_LED1_on[7:0] LED on voltage channel 1 0x00h ... Table 13. LED on voltage = 0 V LED on voltage = 0.3548  V_LED1_on[7:0]  0.56 V LED off voltage channel 1 register, address 0x21h Bit Symbol Description 7:0 V_LED1_off[7:0] LED off voltage channel 1 0x00h Value ... Table 14. Function Function LED off voltage = 0 V LED off voltage = 0.3548  V_LED1_off[7:0]  0.56 V LED on voltage channel 2 register, address 0x22h Bit Symbol Description Value 7:0 V_LED2_on[7:0] LED on voltage channel 2 0x00h ... ASL3416SHN Product data sheet Function LED on voltage = 0 V LED on voltage = 0.3548  V_LED2_on[7:0]  0.56 V All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 11 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver Table 15. LED off voltage channel 2 register, address 0x23h Bit Symbol Description Value 7:0 V_LED2_off[7:0] LED off voltage channel 2 0x00h ... Table 16. LED off voltage = 0 V LED on voltage = 0.3548  V_LED2_off[7:0]  0.56 V LED on voltage channel 3 register, address 0x24h Bit Symbol Description 7:0 V_LED3_on[7:0] LED on voltage channel 3 0x00h Value ... Table 17. Function Function LED on voltage = 0 V LED on voltage = 0.3548  V_LED3_on[7:0]  0.56 V LED off voltage channel 3 register, address 0x25h Bit Symbol Description Value 7:0 V_LED3_off[7:0] LED off voltage channel 3 0x00h ... Function LED off voltage = 0 V LED on voltage = 0.3548  V_LED3_off[7:0]  0.56 V 8.7 External PWM input The ASL3416SHN provides a dedicated PWM input for each of the three channels. It allows full control over the PWM frequency and duty cycle and allows phase shifting of the PWM cycles to balance the input current variations. Pin PWM1 controls channel 1, pin PWM2 controls channel 2 and PWM3 controls channel 3. A high level at the pins represents that the corresponding channel is turned on and the configured current is delivered to the output. As soon as the pin is pulled high, pin Gx of the corresponding channel starts toggling. It switches the MOSFET attached to the pin on and off and the system starts to deliver the configured output current. As soon as the pin is pulled low, pin Gx of the corresponding channel is no longer turned on. The MOSFET stays off and no current is delivered to the output of the corresponding channel. 8.7.1 Control for PWM pins The ASL3416SHN provides the option to disable the PWM input for each of the three channels individually. In case the PWM input of one channel is disabled, this channel stays off, independent of any other conditions. The bits to disable the PWM inputs are located in the function control register (refer to Section 8.8 for details of the function control register). 8.7.2 Diagnostics for PWM functionality The diagnostic options for the PWM functionality comprise the toggle information for the individual PWM pins. Details of the functionality can be found in Section 8.8. 8.8 Function control register To monitor the status of the SPI interface, use the function control register. It allows a reset of the fail silent mode and offers the control of the PWM inputs. ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 12 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver After enabling the device, the SPI_status bit should be set. When a query returns that the bit is set, the SPI interface is operational and the device can be configured. Configuration of the device is not permitted before this bit is set. When the device enters fail silent mode due to an error condition, bit Clr_error can be set to bring the device back into operation mode. Once the error bits are cleared, the device clears the Clr_error bit automatically. If the Clr_error bit is set, when no error is present, the Clr_error bit remains set, until an error occurs. This error is cleared automatically. The functionality of bits PWMctrl1, PWMctrl2 and PWMctrl3 is described in Section 8.7.1. Table 18. Function control register, address 0x00h Bit Symbol Description Value Function 7 SPI_status SPI status bit 0 SPI is not available 1 SPI is operating 6 Clr_error 5:4 3 2 1 PWMctrl3 PWMctrl2 PWMctrl1 0 clear error bits 0 no pending clear request 1 request to clear error bits and reset fail silent mode pending reserved 0 reserved; keep clear for future use PWM control for pin PWM3 0 PWM3 is disabled, channel stays off 1 PWM3 is enabled, LED current depends on PWM state and Register settings PWM control for pin PWM2 0 PWM2 is disabled, channel stays off 1 PWM2 is enabled, LED current depends on PWM state and Register settings PWM control for pin PWM1 0 PWM1 is disabled, channel stays off 1 PWM1 is enabled, LED current depends on PWM state and Register settings reserved 0 reserved; keep clear for future use 8.9 Gate voltage supply The ASL3416SHN has an integrated linear regulator to generate the supply voltage of the gate drivers. The voltage generated by the linear regulator can be set via the VGG control register. Table 19. VGG control register, address 0x01h Bit Symbol Description Value Function 7:0 VGG[7:0] VGG control 0x00h not allowed ... not allowed 0x5Dh maximum output voltage = 10.20 V ... 16.1 V  VGG[7:0]  63.4 mV 0xA6h minimum output voltage = 5.58 V ... not allowed 0xFFh not allowed The actual value of VGG can deviate from the target setting due to the tolerances of the VGG regulation loop (see Vo(reg)acc in Table 35). ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 13 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver When a setting between 0x00h and 0x5Dh is used, the resulting gate driver target voltage exceeds the limiting values of the IC. The limiting values of the VGG pin can also be violated with target settings of 0xA6h to 0x5Dh due to these tolerances. A violation of the limiting values with the actual VGG voltage must be avoided. To ensure that only allowed settings are used for the gate driver target voltage, an immediate read back of the programmed value is required after setting the registers. If a setting between 0xFFh and 0xA6h is used, the device may shut down. 8.9.1 Gate voltage supply diagnostics The diagnostic options for the gate voltage supply are: • VGG available. Details can be found in Section 8.12 • VGG overload protection active. Details can be found in Section 8.12 8.10 Junction temperature information The ASL3416SHN provides a measurement of the IC junction temperature. The measurement information is available in the junction temperature register. Table 20. Junction temperature register, address 0x26h Bit Symbol Description Value Function 7:0 T_junction[7:0] junction temperature 0xD8h device junction temperature = 40 C ... device junction temperature = (256  T_juction[7:0]) C 0xFFh device junction temperature = 1 C 0x00h device junction temperature = 0 C 0x01h device junction temperature = 1 C ... device junction temperature = T_juction[7:0]* C 0xAFh device junction temperature = 175 C The reading of the junction temperature register should be in the range as given in Table 20. If not, the Tj_err bit (Bit 5 in diagnostic register 1, address 0x37h) can be used to indicate whether the temperature is below 175 °C (Tj_err = Low) or above 175 C (Tj_err = High). 8.11 Bootstrap recharge mechanism The gate drivers and current delivered to the gate pins of the ASL3416SHN is supplied by the bootstrap capacitors. These capacitors are attached between the LXx and the BSx pins of the device. To allow a proper drive of the external FET, the voltage across this capacitor must remain near the target level of the gate drive voltage. During device operation, if the external FET switches periodically at quite high frequency, the bootstrap capacitor is charged when the Lx node is low. It is the case when the external FET is off and the converter coil is delivering current to the output. When the external FET is not switching periodically, the bootstrap capacitor is recharged regularly every tp when: • the PWM pin is low for more than Tmeas(LED) • the PWM is high and the CR0 bit is low ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 14 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 8.11.1 Bootstrap charge maintaining To avoid a discharge of the bootstrap capacitors when the system is operated with long PWM off times and short PWM on times, an additional mechanism maintains the bootstrap charge. The ASL3416SHN compensates for the current consumption of the IC on the BS pins. As a result, the BS cap no longer discharges, but slowly settles around VBS-LX. The compensating mechanism is enabled when the gate driver is enabled, the PWM is low, and no Bootstrap undervoltage or low voltage headroom condition is detected. 8.12 Diagnostic information Diagnostic registers contain useful information for diagnostic purposes. Details of each bit can be found in the following subchapters. 8.12.1 Diagnostic Register 1 The diagnostic register 1 contains information about the operational status of the ASL3416SHN. Table 21. Diagnostic register 1, address 0x37h Bit Symbol Description Value Function 7 VIN_stat VIN status 0 VIN below undervoltage detection threshold 1 VIN above undervoltage detection threshold 0 last SPI command was executed correctly 1 last SPI command was erroneous and has been discarded device temperature is too high 0 device temperature below 175 C 1 device temperature above 175 C VGG error 0 VGG overload protection not active 1 VGG overload protection has turned on and VGG is deactivated 0 VGG is not available 1 VGG is available target current reached on channel 3 0 target current was not reached during last PWM cycle 1 target current was reached during last PWM cycle target current reached on channel 2 0 target current was not reached during last PWM cycle 1 target current was reached during last PWM cycle target current reached on channel 1 0 target current was not reached during last PWM cycle 1 target current was reached during last PWM cycle 6 5 4 3 2 1 0 SPI_err Tj_err VGG_err VGG_ok I-CH3 I-CH2 I-CH1 8.12.1.1 SPI error VGG regulation ok Bit VIN_stat The bit VIN_stat indicates the VIN voltage status of the device. This bit is set once the VIN voltage is higher than programmed undervoltage threshold value. When VIN is less than the programmed undervoltage threshold value, the bit is cleared (see Section 8.4 for details about the input undervoltage detection functionality). When the bit is high, the gate pins start switching. The device starts to deliver the output current as requested via the PWM inputs of the corresponding channels. The bits VGG_ok and VGG_err indicate the functional status of VGG. ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 15 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver When the bit is low, the VGG regulator and gate drivers are turned off. The gate pins stop switching, resulting in a turn-off of the output currents. The bit VGG_ok is reset, the bit VGG_err is not changed and the VLED measurement registers are no longer updated. Table 22. Effect of VIN_stat on device functionality Status of VIN VIN_stat VGG_ok VGG_err Output current VLED measurement below undervoltage detection threshold 0 reset cannot be set disabled no update above undervoltage detection threshold 1 no influence no influence enabled updated when VGG_ok is 1 8.12.1.2 Bit SPI_err The bit SPI_err indicates if some error has occurred during the last SPI transfer. When this bit is set after a write access to the device, the device discards the command. When the bit is set after a read command, the microcontroller should discard the information delivered by the device. The SPI_err bit is set in the following cases: • SPI write is attempted to a read-only location or reserved location • SPI read is attempted from a reserved location • SPI command does not consist of a multiple of 16 clock counts The SPI_err bit is cleared on a write to the diagnostic register 1. In case a SPI_error has been detected, the device will return the diagnostic register 1 (default read) and diagnostic register 2 for the next SPI access. 8.12.1.3 Bit Tj_err When the junction temperature rises above the maximum allowable temperature (Tsd(otp)), bit Tj_err is set high. It turns off the gate driver and the gate driver voltage regulator, and clears bit VGG_ok. If VGG_ok was already set high, bit VGG_err is set. The output current is no longer delivered. Only the SPI remains operational. Bit Tj_err must only be cleared with the Clr_errors command when the junction temperature is below the maximum allowable temperature threshold again. Bit VGG_err, that is set together with bit Tj_err, is cleared together with bit Tj_err. 8.12.1.4 Bit VGG_err The bit VGG_err is set when VGG cannot be regulated to its target value. During start-up, the device waits for terr(startup) until the bit is set, during normal operation the device waits only terr(oper). Once the bit is set, it turns off the gate driver and the gate driver voltage regulator, and clears bit VGG_ok. Consequently, output current can no longer be delivered. Only the SPI remains operational. In case the VGG_err bit is set, the LED voltage measurement is no longer updated. To reset the bit, the bit Clr_errors in the function control register can be set. Alternatively, the device must be set to off mode, e.g. by EN going low, or a power-on reset. 8.12.1.5 Bit VGG_ok The bit VGG_ok is set, as soon as the VGG output is regulated to the target value. The bit is cleared on an undervoltage condition at VIN, or an error on VGG. ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 16 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 8.12.1.6 Bit I-Ch1, I-CH2 and I-CH3 The bits I-CH1, I-CH2 and I-CH3 indicate, whether the targeted output current was reached or not in the last PWM cycle. Reasons for not reaching the target current can be e.g. an open LED string or a too low input voltage. The bits are updated for a: • falling edge of the PWM • write of the CR copy pulse bit The bits are cleared for a: • VIN undervoltage event • low voltage headroom event on the representative channel 8.12.1.7 CR copy pulse The bits CCH1, CCH2 and CCH3 can be used to force an update of the LED current reached information. Setting a bit high, initiates an update of the I-CHx bit in the diagnostic register 1 and clears the CR0_CHx bit. The device automatically clears the bit that was set high after the update. Table 23. Bit CR copy pulse register, address 0x06h Symbol 7:3 Description Value Function reserved 000000 reserved; keep clear for future use 2 CCH3 update request for bit I-CH3 0 1 update request for bit I-CH3 1 CCH2 update request for bit I-CH2 0 no pending update request 1 update request for bit I-CH2 update request for bit I-CH1 0 no pending update request 1 update request for bit I-CH1 0 CCH1 no pending update request 8.12.2 Diagnostic register 2 The diagnostic register 2 contains the PWM toggle information of the ASL3416SHN. Table 24. Bit Diagnostic register 2, address 0x36h Description Value Function 7 Symbol reserved 0 reserved; keep clear for future use 6 reserved 1 reserved; keep clear for future use 5:3 reserved 000 reserved; keep clear for future use 2 PWM3 toggle information for pin PWM3 0 1 PWM2 toggle information for pin PWM2 0 1 1 0 PWM1 toggle information for pin PWM1 0 1 ASL3416SHN Product data sheet PWM3 has not toggled since last time the register was read PWM3 has toggled since last time the register was read PWM2 has not toggled since last time the register was read PWM2 has toggled since last time the register was read PWM1 has not toggled since last time the register was read PWM1 has toggled since last time the register was read All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 17 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 8.12.2.1 PWM toggle information (bits PWM1, PWM2 and PWM3) To allow the detection of errors in the control of the PWM pins, the ASL3416SHN allows some diagnostics of the PWM inputs via diagnostic register 2. This register contains the toggle information of the PWM inputs. The bits are set when a change in the level of the pin is detected. The bits are reset on a write to diagnostic register 2. 8.12.3 Diagnostic register 3 Diagnostic register 3 contains the low voltage headroom warning information and the output current state bits. 8.12.3.1 Low voltage headroom warning When the ASL3416SHN operates with low voltage headroom, it could lead to very high duty cycles. Subsequent long on-times for the external FET, could result in low switching frequencies. To avoid long on-times of the external FET, the supply voltage and output voltages are continuously monitored while the channel is on and VIN_stat is high. Once the output voltage is measured to be above Vin minus the low voltage headroom, the gate pin is pulled low. It results in the FET being turned off. At the same moment in time, the low voltage headroom bit (LV_CHx in diagnostic register 3) for the corresponding channel is set. If the voltage difference is again above the low voltage headroom, the device starts to operate again. Bits LV_CH1, LV_CH2 and LV_CH3 remain set until a write to the diagnostic register 3 is performed. If the bits are cleared while the channels are turned off or VIN_stat is low, the bits might be set again if the last sampled voltage indicates a low voltage headroom condition. 8.12.3.2 Output current state Diagnostic register 3 also contains bits CR0_CH1, CR0_CH2 and CR0_CH3. The bits indicate the target current reached information of the individual channels for the current PWM cycle. The bits are set as soon as the target current of the channel is reached. The bits are cleared under the following conditions: • • • • 8.12.3.3 Table 25. Bit a VIN undervoltage event a CR0 copy pulse request via SPI the gate is driven high for more than 1 ms while PWM is high Register content Diagnostic register 3, address 0x35h Symbol 7:6 5 a falling edge on the PWM pin CR0_CH3 ASL3416SHN Product data sheet Description Value Function reserved 00 reserved; keep clear for future use current reached CH3 0 output current is not reached 1 output current is reached All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 18 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver Table 25. Diagnostic register 3, address 0x35h Bit Symbol Description Value Function 4 CR0_CH2 current reached CH2 0 output current is not reached 1 output current is reached 0 output current is not reached 1 output current is reached 0 no low headroom event occurred 1 at least one low headroom event occurred no low headroom event occurred 3 CR0_CH1 current reached CH1 2 LV_CH3 low voltage headroom in CH3 1 LV_CH2 low voltage headroom in CH2 0 1 at least one low headroom event occurred 0 LV_CH1 low voltage headroom in CH1 0 no low headroom event occurred 1 at least one low headroom event occurred 8.12.4 Diagnostic register 4 Diagnostic register 4 contains the BS undervoltage detection bits. 8.12.4.1 Bootstrap undervoltage detection The integrated bootstrap undervoltage detection monitors the voltage between the BS and the LX pins during the off time of the LX pin. If the voltage drops below VBS_UV, the ASL3416SHN prevents the gate from being turned-on and prevent the MOSFET being driven at a low voltage. When this condition is detected on a channel, the channel is turned off and the appropriate error bit is set. A write command to the device clears the error bit and any bits to be cleared are set high. Once the error is cleared, the channel is enabled again. Table 26. Bit BS_UV register - read access, address 0x34h Symbol 7:3 2 1 0 BS_UV3 BS_UV2 BS_UV1 Table 27. Bit Value Function reserved 00000 reserved; keep clear for future use low BS warning CH3 low BS warning CH2 low BS warning CH1 0 no low BS event occurred 1 at least one low BS event occurred 0 no low BS event occurred 1 at least one low BS event occurred 0 no low BS event occurred 1 at least one low BS event occurred BS_UV register - write access, address 0x34h Symbol Description Value Function reserved 00000 reserved; keep clear for future use BS_UV3 low BS warning CH3 0 no action 1 clear low BS warning for channel 3 no action 7:3 2 Description 1 BS_UV2 low BS warning CH2 0 1 clear low BS warning for channel 2 0 BS_UV1 low BS warning CH1 0 no action 1 clear low BS warning for channel 1 ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 19 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 8.13 SPI The ASL3416SHN uses an SPI interface to communicate with an external microcontroller. The SPI interface can be used for setting the LEDs current, reading and writing the control register. 8.13.1 Introduction The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave operations. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing the application to read back the registers without changing the register content. The SPI uses four interface signals for synchronization and data transfer: • • • • CSB - SPI chip select; active LOW SCLK - SPI clock - default level is LOW due to low-power concept SDI - SPI data input SDO - SPI data output - floating when pin CSB is HIGH Bit sampling is performed on the falling clock edge and data is shifted on the rising clock edge as illustrated in Figure 4. SCLK CSB SDI b15 MSB b14 b13 b12 b11 b10 b9 b3 b2 b1 b0 SDO b15 MSB b14 b13 b12 b11 b10 b9 b3 b2 b1 b0 Sampling Edge Driving Edge aaa-016623 Fig 4. SPI timing protocol The data bits of the ASL3416SHN are arranged in registers of 1 byte length. Each register is assigned to a 7-bit address. For writing into a register, 2 bytes must be sent to the LED driver. The first byte is an identifier byte that consists of the 7-bit address and one read-only bit. For writing, the read-only bit must be set to “0”. The second byte is the data that shall be written into the register. So an SPI access consists of at least 16 bits. Figure 5 together with Table 28 and Table 29 demonstrate the SPI frame format. ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 20 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver R/W Address b15 b14 b13 b12 b11 b10 b9 Table 28. b7 b6 b3 b2 b1 b0 aaa-016624 SPI frame format for a transition to the device Symbol Description Value Function 15 b15 R/W bits 0 write access 1 read access 14:8 b14:8 address bits ... selected address 7:0 data bits ... transmitted data Bit b4 SPI frame format Bit b7:0 Table 29. b5 b15 = MSB = first transmitted bit R/W Fig 5. Data b8 SPI frame format for a transition from the device Symbol Description Value Function 15:8 b15:8 diagnostic register 1 ... content of diagnostic register 1 7:0 data bits ... when previous command was a valid read command, content of the register that is supposed to be read ... When previous command was a valid write command, new content of the register that was supposed to be written b7:0 Note: The first SPI command after a leaving of off mode returns 0x00h. The Master initiates the command sequence. The sequence begins with CSB pin pulled low and lasts until it is asserted high. The ASL3416SHN also tolerates SPI accesses with a multiple of 16 bits. It allows a daisy chain configuration of the SPI. MOSI SDI CSB CSB SCLK SCLK ASLxxxxSHN SDO SOMI µC SDI CSB SCLK ASL3416SHN SDO SDI CSB SCLK ASL3416SHN SDO aaa-018557 Fig 6. ASL3416SHN Product data sheet Daisy chain configuration All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 21 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver MOSI SDI CSB1 CSB SCLK SCLK ASLxxxxSHN SDO SOMI CSB2 µC CSB3 SDI CSB SCLK ASL3416SHN SDO SDI CSB SCLK ASL3416SHN SDO aaa-018558 Fig 7. Physical parallel slave connection During the SPI data transfer, the identifier byte and the actual content of the addressed registers is returned via the SDO pin. The same happens for pure read accesses. Here the read-only bit must be set to 1. The content of the data bytes that are transmitted to the ASL3416SHN is ignored. The ASL3416SHN monitors the number of data bits that are transmitted. If the number is not 16, or a multiple of 16, then a write access is ignored and the SPI error indication bit is set. 8.13.2 Typical use case illustration (write/read) Consider a daisy chain scheme with one master connected to 4 slaves in Daisy chain fashion. The following commands are performed during one sequence (first sequence). • • • • ASL3416SHN Product data sheet write data 0xFFh to register 0x1Ah slave 1 read from register 0x02 of slave 2 write data 0xAFh to register 0x2Fh of slave 3 read from register 0x44h of slave 4 All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 22 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 1st Sequence 2nd Sequence CSB SCLK 1 x 16 SCLK’s 2 x 16 SCLK’s 3 x 16 SCLK’s 4 x 16 SCLK’s 1 x 16 SCLK’s 2 x 16 SCLK’s 3 x 16 SCLK’s Next command for Slave4 Next command for Slave3 Next command for Slave2 Next command for Slave1 4 x 16 SCLK’s Master SDO/ Slave1 SDI b15 = 1 b14-b8 = 0x44 b7-b0 = xx b15 = 0 b14-b8 = 0x2F b7-b0 = 0xAF b15 = 1 b14-b8 = 0x2 b7-b0 = xx Slave 1 b15 = 0 b14-b8 = 0x1A b7-b0 = 0xFF Slave1 SDO/ Slave2 SDI XXX b15 = 1 b14-b8 = 0x44 b7-b0 = xx b15 = 0 b14-b8 = 0x2F b7-b0 = 0xAF Slave 2 b15 = 1 b14-b8 = 0x2 b7-b0 = xx b15-b8 = Default read reg of slave1 b7-b0 = xx Next command for Slave4 Next command for Slave3 Next command for Slave2 Slave2 SDO/ Slave3 SDI XXX XXX b15 = 1 b14-b8 = 0x44 b7-b0 = xx Slave 3 b15 = 0 b14-b8 = 0x2F b7-b0 = 0xAF b15-b8 = Default read reg of slave2 b7-b0 = Data from 0x2 of Slave2 b15-b8 = Default read reg of slave1 b7-b0 = xx Next command for Slave4 Next command for Slave3 Slave3 SDO/ Slave4 SDI XXX XXX XXX Slave 4 b15 = 1 b14-b8 = 0x44 b7-b0 = xx b15-b8 = Default read reg of slave3 b7-b0 = xx b15-b8 = Default read reg of slave2 b7-b0 = Data from 0x2 of Slave2 b15-b8 = Default read reg of slave1 b7-b0 = xx Next command for Slave4 Slave4 SDO/ Master SDI XXX XXX XXX XXX b15-b8 = Default read reg of slave4 b7-b0 = Data from 0x44 of Slave4 b15-b8 = Default read reg of slave3 b7-b0 = xx b15-b8 = Default read reg of slave2 b7-b0 = Data from 0x2 of Slave4 b15-b8 = Default read reg of slave1 b7-b0 = xx Current sequence Command decoded by Slave Response from previous sequence Fig 8. aaa-016627 SPI frame format 8.13.3 Diagnostics for the SPI interface The diagnostic options for the SPI interface are Error during last SPI transfer. For details, refer to Section 8.11. 8.13.4 Register map The addressable register space amounts to 128 registers from 0x00h to 0x7Fh. They are separated in two groups as shown in Table 30. The register mapping is shown in Table 31 and Table 32. The functional description of each bit can be found in the dedicated chapter. Table 30. ASL3416SHN Product data sheet Grouping of the register space Address range Description Content 0x00h ... 0x1Fh control registers thresholds, LED currents 0x20h ... 0x7Fh diagnostic registers LED voltages, PWM toggle information All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 23 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 8.13.4.1 Control registers Table 31 provides an overview of the control registers and their reset state. Table 31. Control register group overview Address Name Reset value 7 6 0x00h function control 0x0Eh 0x01h VGG control 0xFFh 0x02h LED current channel 1 0x00h I_LED_CH1[7:0] 0x03h LED current channel 2 0x00h I_LED_CH2[7:0] 0x04h LED current channel 3 0x00h I_LED_CH3[7:0] SPI_status Clr_errors 5 4 - - 3 2 1 0 PWMctrl3 PWMctrl2 PWMctrl1 - VGG[7:0] 0x05h LED current range 0x07h - - - - - I_CH3 I_CH2 I_CH1 0x06h CR copy pulse 0x00h - - - - - CCH3 CCH2 CCH1 0x0Bh hysteresis channel 1 0x03h - - - - - - HCH1[1:0] 0x0Ch hysteresis channel 2 0x03h - - - - - - HCH2[1:0] 0x0Dh hysteresis channel 3 0x03h - - - - - - HCH3[1:0] 0x0Fh undervoltage threshold 0x00h 8.13.4.2 V_VIN_UV[7:0] Diagnostic registers Table 32 provides an overview of the diagnostic registers. As the device continuously updates these registers, they do not have a default value. Table 32. Diagnostic register group overview Address Name 7 6 5 4 3 2 1 0 0x20h LED on voltage channel 1 0x21h LED off voltage channel 1 V_LED1_off[7:0] 0x22h LED on voltage channel 2 V_LED2_on[7:0] 0x23h LED off voltage channel 2 V_LED2_off[7:0] 0x24h LED on voltage channel 3 V_LED3_on[7:0] 0x25h LED off voltage channel 3 V_LED3_off[7:0] 0x26h junction temperature 0x34h diagnostic register 4 - - - - 0x35h diagnostic register 3 - - CR0_CH 3 CR0_CH 2 0x36h diagnostic register 2 - 1 - - - PWM3 PWM2 PWM1 0x37h diagnostic register 1 (default read register) Tj_er VGG_er VGG_ok I-CH3 I-CH2 I-CH1 0x38h VIN voltage measurement[1] [1] V_LED1_on[7:0] T_junction[7:0] VIN_Stat SPI_er - BS_UV BS_UV2 BS_UV1 3 CR0_CH LV_CH3 LV_CH2 LV_CH1 1 V_VIN[7:0] A write to the VIN voltage measurement register does not set the SPI error bit high. ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 24 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 9. Limiting values Table 33. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VIN voltage on pin VIN EN = low 0.3 +80 V EN = high 10 80 V VVCC voltage on pin VCC 0.3 +5.5 V VI(dig) digital input voltage voltage on pins SDO, SDI, CSB, SCLK, EN, PWM1, PWM2 and PWM3 0.3 +5.5 V VVGG voltage on pin VGG 0.3 +10 V VLX voltage on pin LX LX1, LX2 and LX3 1.0 +80 V SRf(max) maximum falling edge slew rate on pins LX1, LX2 and LX3; at maximum input voltage - 5.0[1] V/ns Vsense sense voltage voltage on sense pins RH1, RL1, RH2, RL2, RH3 and RL3 1.0 +70[2] V VRH-RL(max) maximum voltage drop between pins RH and RL maximum drop between the RH and RL pins of one channel 0.3 +0.8 V VBSx voltage on bootstrap pins BS1, BS2 and BS3 0.3 +90 V VGx voltage on gate pins G1, G2 and G3 1.0 +90 V Vmax maximum voltage difference between pins G and LX of one channel - 12 V between pins BS and LX of one channel - 12 V 40 +175 °C 55 +175 °C at any pin 2 +2 kV at pins RLx with respect to GND and 100 nF at pin 6 +6 kV 500 +500 V Tj junction temperature Tstg storage temperature VESD electrostatic discharge voltage HBM[3] CDM[4] at any pin [1] The limitation of the slew rate is an IC constraint. When the IC is operating in an application circuit, the external circuitry influences the slew rate capability. An example guideline for some specific MOSFET parameters to be considered when selecting the appropriate resistor values, can be found in the table below. Nonetheless, each application should be validated to determine the final solution when considering EMC performance and correct gate driver operation. [2] 76 V for t  10 seconds guaranteed by design. [3] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k). [4] Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF). ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 25 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 9.1 External circuitry Table 34. Guideline for external circuitry Symbol Component MOSFET configuration typical values Config. 1 Config. 2 Config. 3 RG [1] 1.0 4.7 1.7  QGS [1] 0.6 1.2 0.8 nC QGD [1] 0.9 1.8 1.2 nC RDSon [1] 175 80 72 m Rgate gate resistor 33 15 33  RLx sense resistor low side channel 10 10 10  1 1 1 F C5 [1] Unit MOSFET M5 VIN C15 Gx ASL3416SHN Rgate BSx C5 LXx RLx M5 L5 R5 C12 RHx D9 D10 RLx D11 D5 aaa-022816 Fig 9. ASL3416SHN Product data sheet External components All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 26 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 10. Thermal characteristics 10.1 Thermal model of the ASL3416SHN The ASL3416SHN has several power sources on the die, but for thermal modeling they can be simplified to one generic power source. Pd Tj 13.3 K/W Tsense 8 K/W Tcase Rth (exposed pad ambient) aaa-016628 Fig 10. Thermal model of the ASL3416SHN The power can be calculated using Equation 4 and Equation 5: I gates = fsw1  Qg1 + fsw2  Qg2 + fsw3  Qg3 (4) P d = V Vin   3.5 mA + 1.3 mA  #channels_active + I gates  + V VCC  10 mA (5) Note, the Tsense is the location of the IC internal temperature measurement. Due to the location of the sensor, it is possible that the junction temperature has already exceeded 175 C, while the temperature measurement still returns a value of lower than 175C. ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 27 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 11. Static characteristics Table 35. Static characteristics Min and Max values are specified for the following conditions: VVIN = 10 V to 80 V, VEN = 4.5 V to 5.5 V, VVCC = 4.5 V to 5.5 V and Tj = 40 °C to +175 °C.[1] All voltages are defined with respect to ground, positive currents flow into the IC. Typical values are given at VVIN = 40 V. VEN = 5 V, VVCC = 5 V and Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IDD supply current on pin VIN; operating no load on gate and VGG not set - 3.5 10 mA current on pin EN when EN = high - - 150 A EN = low; VIN < 12 V - - 5 A Ioff off-state current Supply pin VCC IVCC VUVLO(VCC) supply current on pin VCC EN = high; CSB = low - 10 15 mA [2] 3.7 - 4.4 V [2] 3.7 - 4.4 V LED1; VIN  VO(LED) + Vhr(low) 2.5 - 70 V LED2; VIN  VO(LED) + Vhr(low) 2.5 - 70 V LED3; VIN  VO(LED) + Vhr(low) 2.5 - 70 V setting 0 5 - 11 mV setting 1 13 - 21 mV setting 2 22 - 31 mV setting 3 32 - 42 mV nominal average; VO(LED) = 2.5 V to 70 V; VIN  VO(LED) + Voff(hr)low; Rsense = 200 m VO(min)/ Rsense - 1500 mA 4 - +4 % undervoltage lockout on pin VCC Enable pin EN VUVLO(EN) undervoltage lockout on pin EN LED output characteristics VO(LED) VO(min) IO(LED) LED output voltage minimum output voltage average values LED output current Vsense(AV)acc average sense voltage accuracy I_CHx = 1; Vsense(AV)  24 mV I_CHx = 0; Vsense(AV)  120 mV VO(acc) output voltage accuracy related to currently applied value Voff(hr)low low headroom turn-off voltage Vocp overcurrent protection voltage VIN  VO(LED) [3] [3] 4 - +4 % 0.02  VLEDx  1.0644 V - 0.02  VLEDx  1.0644 V % 0.02  VVIN  1.0644 V - 0.02  VVIN  1.0644 V % 5 - 7 V - 400 - mV VGG output characteristics (CVGG = 1 F, ESR  0.1 ) VO(reg) regulator output voltage 4.5 - 10.04 V VO(reg)acc regulator output voltage accuracy 5 - +5 % Vdo(reg) regulator dropout voltage Ireg  50 mA; regulator in saturation - 0.5 1.0 V Ireg  160 mA; regulator in saturation - 1.6 3.2 V ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 28 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver Table 35. Static characteristics …continued Min and Max values are specified for the following conditions: VVIN = 10 V to 80 V, VEN = 4.5 V to 5.5 V, VVCC = 4.5 V to 5.5 V and Tj = 40 °C to +175 °C.[1] All voltages are defined with respect to ground, positive currents flow into the IC. Typical values are given at VVIN = 40 V. VEN = 5 V, VVCC = 5 V and Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Bootstrap characteristics; pins BS1, BS2 and BS3 (capacitance between BS and LX pins = 1 F) Vd(bs) bootstrap diode voltage Ibs  100 mA - - Ibs bootstrap current current consumption of gate driver; output is turned on - 300 - A Vth(bs)OV bootstrap overvoltage detection threshold 5.5 - 8 V Vth(bs)UV bootstrap undervoltage detection threshold 3.5 4.5 5.3 V 1.5 V PWM inputs; pins PWM1, PWM2 and PWM3 Vth(sw) switching threshold voltage 0.7 - 3.5 V Rpd(int) internal pull-down resistance 50 - 130 k Serial peripheral interface inputs; pins SDI, SCLK and CSB Vth(sw) switching threshold voltage 0.7 - 3.5 V Vth(sw)hys switching threshold voltage hysteresis 0.1 - 1.1 V IIL LOW-level input current 10 - +10 A IIH HIGH-level input current 15 40 110 A Rpd(int)SCLK internal pull-down resistance on pin SCLK 50 - 130 k Rpd(int)CSB internal pull-down resistance on pin CSB 50 - 130 k Rpd(int)SDI internal pull-down resistance on pin SDI 50 - 130 k Serial peripheral interface data output; pin SDO VOH HIGH-level output voltage IOH = 4 mA 0.9 VVCC - - V VOL LOW-level output voltage IOL = 4 mA - - 0.1 VVCC V IOH HIGH-level output current 30.0 - 1.6 mA IOL LOW-level output current 1.6 - 30.0 mA ILOZ OFF-state output leakage current 5 - +5 A 165 175 185 C 5 - C VCSB = VVCC; VO = 0 V to VVCC Temperature protection Tsd(otp) overtemperature protection shutdown temperature Tj junction temperature variation [1] Tj = 130 C; measurement provided via register 0x26h [4] +5 All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. [2] Undervoltage lockout pulls the gate pins low but the other functions of the IC remain operational. [3] Excluding influence of load and line regulation due to total delay of gate driver and comparators of hysteretic converter. [4] Guaranteed by wafer testing at 125 °C. ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 29 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 12. Dynamic characteristics Table 36. Dynamic characteristics Min and Max values are specified for the following conditions: VVIN = 10 V to 80 V, VEN = 4.5 V to 5.5 V, VVCC = 4.5 V to 5.5 V and Tj = 40 °C to +175 °C[1]. All voltages are defined with respect to ground, positive currents flow into the IC. Typical values are given at VVIN = 40 V. VEN = 5 V and VVCC = 5 V, unless otherwise specified. Symbol Parameter Min Typ Max Unit fPWM PWM frequency Conditions 100 - 1000 Hz PWM PWM duty cycle 0 - 100 % td(on)PWM PWM turn-on delay time 90 % of LED current - - 100 s td(off)PWM PWM turn-off delay time 10 % of LED current - - 100 s td(i)PWM PWM input delay time including start-up time of the boost - 20 - ms fDCDC DC-to-DC converter frequency 100 - 2000 kHz ton(drv)G(max) maximum on time of one gate driver - 1 - ms td(drv)G gate driver delay time tblank blanking time toff(drv)G(min) minimum off time of one gate driver total delay of gate driver and comparators of hysteretic converter [2] 25 - 75 ns total delay of gate driver and comparators of hysteretic converter [3] 10 - 75 ns 70 - 130 ns - 125 - ns of sense amplifier after switching Serial peripheral interface timing; pins CSB, SCLK, SDI and SDO tcy(clk) clock cycle time 285 - - ns tSPILEAD SPI enable lead time 140 - - ns tSPILAG SPI enable lag time 140 - - ns tclk(H) clock HIGH time 140 - - ns tclk(L) clock LOW time 140 - - ns tsu(D) data input set-up time 50 - - ns th(D) data input hold time 50 - - ns tv(Q) data output valid time tWH(S) chip select pulse width HIGH pin SDO; CL = 50 pF td(SPI) SPI delay time trst(reg) register reset time - - 130 ns 285 - - ns EN = 0 V  5 V - - 100 s time to reset all registers to default value; EN = 0 V  5 V - - 400 s Gate driver characteristics for pins G1, G2 and G3 tch(G) gate charge time 20 % to 80 %; Vbsx - LXx = 10 V; Cgate = 1000 pF - - 50 ns tdch(G) gate discharge time 20 % to 80 %; Vbsx - LXx = 10 V; Cgate = 1000 pF - - 25 ns tp pulse duration applies to BS pins recharge pulse time - 80 - s period for recharge pulses - 360 - s ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 30 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver Table 36. Dynamic characteristics …continued Min and Max values are specified for the following conditions: VVIN = 10 V to 80 V, VEN = 4.5 V to 5.5 V, VVCC = 4.5 V to 5.5 V and Tj = 40 °C to +175 °C[1]. All voltages are defined with respect to ground, positive currents flow into the IC. Typical values are given at VVIN = 40 V. VEN = 5 V and VVCC = 5 V, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Voltage measurements tmeas measurement time period for voltage measurements at outputs - 80 - s tmeas(LED) LED measurement time period for the LED voltage measurement update when the PWM pin is static - 16 - ms period for voltage measurement at VIN - 15 - s LV headroom detection - 8 - s VGG characteristics terr(startup) start-up error time time to detect an error on VGG at start-up - 20.2 - ms terr(oper) operation error time time to detect an error on VGG during operation - 200 s - [1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. [2] Lower hysteresis trip point until external FET is turned on. [3] Higher hysteresis trip point until external FET is turned off. CSB tSPILEAD tSPILAG tcy(clk) tclk(H) tclk(L) tsu(D) th(D) tWH(S) SCLK SDI MSB X LSB X tv(Q) floating SDO floating X MSB LSB aaa-018559 Fig 11. SPI timing diagram ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 31 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 13. Application information Figure 12 provides an example for the ASL3416SHN in a typical external front lighting application driving 3 independent LED strings. D8 battery C1 C2 L1 D1 M1 G1 VGG1 C8 VIN SNH1 VGG C16 R1 L2 SNL1 G1 D2 C15 BS1 VGG2 G2 C17 M2 L5 R5 LED1 C12 C9 SNH2 M5 C5 LX1 D9 PWM1 RH1 VBAT D10 PWM2 R2 SNL2 C18 RL1 PWM3 FB1 D11 D5 FB2 VCC EN L3 ASLxxxxSHN D3 M3 CSB G2 G3 SDI C10 BS2 SNH3 SDO ASL3416SHN SCLK R3 SNL3 GND L4 G4 GND2 M4 C11 R6 LED2 C13 LX2 EN RH2 D13 RL2 D14 CSB SNH4 GND3 L6 D12 D4 VCC GND1 M6 C6 D6 SDI R4 GND4 SDO SNL4 SCLK G3 BS3 M7 L7 C7 R7 LED3 C14 LX3 C20 VCC VBAT RSTN C19 GND TJA1028 LIN LIN EN TXD RXD D15 VCC EN_1 RSTN EN_2 EN CSB1 TXD CSB2 RXD µC RH3 D16 GND RL3 D17 D7 SDI SDO GND SCLK PWM1 PWM2 PWM3 aaa-018560 Fig 12. Application example in a typical external front lighting 14. Test information 14.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism-based stress test qualification for integrated circuits. It is suitable for use in automotive applications. ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 32 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 15. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-12 terminal 1 index area E A A1 c detail X e1 1/2 e e 9 16 C C A B C v w b y1 C y L 8 17 e e2 Eh 1/2 e 1 24 terminal 1 index area 32 k 25 X Dh 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh e e1 e2 0.2 5.1 5.0 4.9 3.1 3.0 2.9 5.1 5.0 4.9 3.1 3.0 2.9 0.5 3.5 3.5 k L v 0.1 0.5 0.50 0.44 0.30 w y y1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version References IEC SOT617-12 JEDEC JEITA sot617-12_po European projection Issue date 13-10-14 13-11-05 MO-220 Fig 13. Package outline HVQFN32 ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 33 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 16. Revision history Table 37. Revision history Document ID Release date Data sheet status Change notice Supersedes ASL3416SHN v.6 20190916 Product data sheet - ASL3416SHN v.5.1 Modifications: ASL3416SHN v.5.1 Modifications: ASL3416SHN v.5 Modifications: ASL3416SHN v.4.1 Modifications: ASL3416SHN v.4 Modifications: ASL3416SHN v.3 Modifications: ASL3416SHN v.2 Modifications: ASL3416SHN v.1 ASL3416SHN Product data sheet • • • Section 8.5.1: corrected results in calculation example Table 19: changed formula for VGG setting Table 35: clarified minimum LED output current 20171026 • 20170222 • • • • Product data sheet - ASL3416SHN v.5 Section 8.9: clarified exceeding of limiting values Product data sheet - ASL3416SHN v.4.1 Formula for voltage conversion updated Figure 10: updated Equation 4 and Equation 5: updated Table 35: maximum value for low headroom turn-off voltage changed 20160602 Product data sheet - ASL3416SHN v.4 • A number of values have been updated in Table 6 “LED current channel 1 register, address 0x02h”, Table 7 “LED current channel 2 register, address 0x03h” and Table 8 “LED current channel 3 register, address 0x04h”. • Additions made to Table 35 “Static characteristics” 20160413 Product data sheet - ASL3416SHN v.3 • A number of values have been updated in Table 33 “Limiting values” and Table 36 “Dynamic characteristics” • • Text corrections have been made throughout the data sheet. Specification status changed to Product data sheet. 20150925 • • - ASL3416SHN v.2 Minor text corrections have been made throughout the data sheet. A number of values have been updated in Table 33 “Limiting values”, Table 35 “Static characteristics” and Table 36 “Dynamic characteristics” 20150818 • • • Preliminary data sheet Preliminary data sheet - ASL3416SHN v.1 Minor corrections made to Figure 11. Text has been corrected and aligned with the ASLxxxxSHN series of data sheets. A number of symbols have been upgraded to NXP standards. 20150716 Preliminary data sheet - All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 - © NXP Semiconductors N.V. 2019. All rights reserved. 34 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. ASL3416SHN Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 35 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — While NXP Semiconductors has implemented advanced security features, all products may be subject to unidentified vulnerabilities. Customers are responsible for the design and operation of their applications and products to reduce the effect of these vulnerabilities on customer’s applications and products, and NXP Semiconductors accepts no liability for any vulnerability that is discovered. Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 36 of 38 ASL3416SHN NXP Semiconductors Enhanced three channel LED buck driver 19. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Pin description[1] . . . . . . . . . . . . . . . . . . . . . . . .4 VIN voltage measurement register, address 0x38h[1] . . . . . . . . . . . . . . . . . . . . . . . . .7 Undervoltage threshold register, address 0x0Fh . . . . . . . . . . . . . . . . . . . . . . . . . .7 LED current range register, address 0x05h . . . .8 LED current channel 1 register, address 0x02h .8 LED current channel 2 register, address 0x03h .8 LED current channel 3 register, address 0x04h .8 Hysteresis channel 1 register, address 0x0Bh . .9 Hysteresis channel 2 register, address 0x0Ch .9 Hysteresis channel 3 register, address 0x0Dh . .9 LED on voltage channel 1 register, address 0x20h . . . . . . . . . . . . . . . . . . . . . . . . . 11 LED off voltage channel 1 register, address 0x21h . . . . . . . . . . . . . . . . . . . . . . . . . 11 LED on voltage channel 2 register, address 0x22h . . . . . . . . . . . . . . . . . . . . . . . . . 11 LED off voltage channel 2 register, address 0x23h . . . . . . . . . . . . . . . . . . . . . . . . .12 LED on voltage channel 3 register, address 0x24h . . . . . . . . . . . . . . . . . . . . . . . . .12 LED off voltage channel 3 register, address 0x25h . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Function control register, address 0x00h . . . . . 13 VGG control register, address 0x01h. . . . . . . . 13 Junction temperature register, address 0x26h. 14 Diagnostic register 1, address 0x37h. . . . . . . . 15 Effect of VIN_stat on device functionality. . . . . 16 CR copy pulse register, address 0x06h . . . . . . 17 Diagnostic register 2, address 0x36h. . . . . . . . 17 Diagnostic register 3, address 0x35h. . . . . . . . 18 BS_UV register - read access, address 0x34h . . . . . . . . . . . . . . . . . . . . . . . . . 19 BS_UV register - write access, address 0x34h . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI frame format for a transition to the device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI frame format for a transition from the device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Grouping of the register space. . . . . . . . . . . . . 23 Control register group overview . . . . . . . . . . . 24 Diagnostic register group overview . . . . . . . . . 24 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 25 Guideline for external circuitry . . . . . . . . . . . . . 26 Static characteristics . . . . . . . . . . . . . . . . . . . . 28 Dynamic characteristics . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 34 20. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4 State diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 SPI timing protocol. . . . . . . . . . . . . . . . . . . . . . . .20 SPI frame format . . . . . . . . . . . . . . . . . . . . . . . . .21 Daisy chain configuration. . . . . . . . . . . . . . . . . . .21 Physical parallel slave connection . . . . . . . . . . . .22 SPI frame format . . . . . . . . . . . . . . . . . . . . . . . . .23 External components . . . . . . . . . . . . . . . . . . . . . .26 Thermal model of the ASL3416SHN . . . . . . . . . .27 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . .31 Application example in a typical external front lighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Fig 13. Package outline HVQFN32 . . . . . . . . . . . . . . . . .33 ASL3416SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 September 2019 © NXP Semiconductors N.V. 2019. All rights reserved. 37 of 38 NXP Semiconductors ASL3416SHN Enhanced three channel LED buck driver 21. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 6 8.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 6 8.1.1 Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1.2 Operation mode . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1.3 Undervoltage mode . . . . . . . . . . . . . . . . . . . . . 6 8.1.4 Fail silent mode . . . . . . . . . . . . . . . . . . . . . . . . 6 8.2 Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.3 Input voltage measurement . . . . . . . . . . . . . . . 7 8.4 Input undervoltage detection . . . . . . . . . . . . . . 7 8.5 Output current programmability . . . . . . . . . . . . 7 8.5.1 Output target current programming . . . . . . . . . 7 8.5.2 Hysteresis programming via SPI . . . . . . . . . . . 9 8.5.3 Overcurrent protection . . . . . . . . . . . . . . . . . . 11 8.5.4 Output diagnostics . . . . . . . . . . . . . . . . . . . . . 11 8.6 Output voltage measurement . . . . . . . . . . . . . 11 8.7 External PWM input . . . . . . . . . . . . . . . . . . . . 12 8.7.1 Control for PWM pins . . . . . . . . . . . . . . . . . . . 12 8.7.2 Diagnostics for PWM functionality . . . . . . . . . 12 8.8 Function control register . . . . . . . . . . . . . . . . . 12 8.9 Gate voltage supply . . . . . . . . . . . . . . . . . . . . 13 8.9.1 Gate voltage supply diagnostics . . . . . . . . . . . 14 8.10 Junction temperature information . . . . . . . . . . 14 8.11 Bootstrap recharge mechanism . . . . . . . . . . . 14 8.11.1 Bootstrap charge maintaining . . . . . . . . . . . . . 14 8.12 Diagnostic information . . . . . . . . . . . . . . . . . . 15 8.12.1 Diagnostic Register 1 . . . . . . . . . . . . . . . . . . . 15 8.12.1.1 Bit VIN_stat. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.12.1.2 Bit SPI_err . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.12.1.3 Bit Tj_err . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.12.1.4 Bit VGG_err . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.12.1.5 Bit VGG_ok. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.12.1.6 Bit I-Ch1, I-CH2 and I-CH3 . . . . . . . . . . . . . . 17 8.12.1.7 CR copy pulse . . . . . . . . . . . . . . . . . . . . . . . . 17 8.12.2 Diagnostic register 2 . . . . . . . . . . . . . . . . . . . . 17 8.12.2.1 PWM toggle information (bits PWM1, PWM2 and PWM3). . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.12.3 Diagnostic register 3 . . . . . . . . . . . . . . . . . . . . 18 8.12.3.1 Low voltage headroom warning . . . . . . . . . . . 18 8.12.3.2 Output current state . . . . . . . . . . . . . . . . . . . . 8.12.3.3 Register content. . . . . . . . . . . . . . . . . . . . . . . 8.12.4 Diagnostic register 4 . . . . . . . . . . . . . . . . . . . 8.12.4.1 Bootstrap undervoltage detection . . . . . . . . . 8.13 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.2 Typical use case illustration (write/read) . . . . 8.13.3 Diagnostics for the SPI interface . . . . . . . . . . 8.13.4 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.4.1 Control registers. . . . . . . . . . . . . . . . . . . . . . . 8.13.4.2 Diagnostic registers . . . . . . . . . . . . . . . . . . . . 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 9.1 External circuitry . . . . . . . . . . . . . . . . . . . . . . 10 Thermal characteristics . . . . . . . . . . . . . . . . . 10.1 Thermal model of the ASL3416SHN . . . . . . . 11 Static characteristics . . . . . . . . . . . . . . . . . . . 12 Dynamic characteristics. . . . . . . . . . . . . . . . . 13 Application information . . . . . . . . . . . . . . . . . 14 Test information . . . . . . . . . . . . . . . . . . . . . . . 14.1 Quality information . . . . . . . . . . . . . . . . . . . . . 15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information . . . . . . . . . . . . . . . . . . . . . . 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information . . . . . . . . . . . . . . . . . . . . 19 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 19 19 20 20 22 23 23 24 24 25 26 27 27 28 30 32 32 32 33 34 35 35 35 35 36 36 37 37 38 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2019. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 September 2019 Document identifier: ASL3416SHN