CX24109

CX24109 Digital Satellite Tuner Rev. 01 — 13 November 2008 Product data sheet Document information Info Keywords Abstract Content NXP Semiconductors CX24109 Digital Satellite Tuner Ordering information Type number CX24109-11 CX24109-11Z Digital Satellite Tuner Description Package 48-pin eTQFP Revision history Revision 01 20081113 Date Description First NXP version based on the Conexant 102031A data sheet. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 2 NXP Semiconductors CX24109 Digital Satellite Tuner General description The CX24109 is a highly integrated, direct down-conversion satellite tuner intended for high-volume digital video, audio, and data receivers. When combined with the CX24121 QPSK demodulator/FEC decoder, the chip set provides a complete broadband satellite front-end solution capable of operating from 1–45 MSps in the most demanding satellite environments. It is compatible with international standards such as DVB and DSS. The highly integrated CX24109 reduces the tuner BOM cost and simplifies the RF layout. Features Zero-IF architecture eliminates the need for image reject filtering Integrated LNA Integrated LO with onboard VCO and synthesizer Single +5 V supply Reference oscillator output for demodulator Applications DBS set-top boxes Commercial digital video, audio, and data receivers Digital VCRs Block diagram Variable Low Pass Filter VGA1 VGA2 I Channel Output VCA RF Input 90 0 VGA1 Variable Low Pass Filter VGA2 Q Channel Output Reference Oscillator VCO PLL Dividers, Phase Detector, and Charge Pump Reference Programming Lock to DEMOD and Control Detect CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 3 NXP Semiconductors CX24109 Digital Satellite Tuner CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 4 NXP Semiconductors CX24109 Digital Satellite Tuner Contents Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 Pinout Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5 AGC and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.6 Local Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.7 Programming Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.7.1 Gain Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.7.2 Frequency Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.7.3 Recommended Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1 AGC Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 VCO Power Pin Ripple Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4 Example Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3 Parametric Data and Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.1 Standard Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Legal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 5 NXP Semiconductors CX24109 Digital Satellite Tuner CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 6 NXP Semiconductors CX24109 Digital Satellite Tuner Figures Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 10 Fig. 11 Fig. 12 Fig. 13 Fig. 14 Fig. 15 Fig. 16 Fig. 17 CX24109 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPSK Demodulation Typical Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified Application Schematic (Page 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified Application Schematic (Page 2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflection Coefficient at Input of CX24109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband Filter Gain vs. Frequency and FILTUNE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter –3 dB Bandwidth vs. FILTUNE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain and IIP3 vs. AGC Voltage at 950 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain and IIP3 vs. AGC Voltage at 2150 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain and NF vs. AGC Voltage at 950 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain and NF vs. AGC Voltage at 2150 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-pin eTQFP Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-pin eTQFP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 14 16 16 24 25 26 27 27 28 28 29 29 33 36 37 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 7 NXP Semiconductors CX24109 Digital Satellite Tuner CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 8 NXP Semiconductors CX24109 Digital Satellite Tuner Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Band Select Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended AGC Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended VCO Frequency vs. Charge Pump Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Charge Pump Polarity and Reference Divider Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 16 18 19 20 21 22 22 22 31 31 32 32 33 36 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 9 NXP Semiconductors CX24109 Digital Satellite Tuner CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 10 CX24109 Chapter 1: Functional Description Rev. 01 — 13 November 2008 Product data sheet 1.1 Figure 1. Pinout Information CX24109 Pin Diagram GND GND GND GND GND GND 48 47 46 45 44 43 42 41 40 39 38 VCC GND GND RFIN RFGND GND GND DCIP DCIN DCQP DCQN TUNERES 37 36 35 34 33 32 31 AGC VCC VCC VCC VCC VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FILTUNE IOUTN IOUTP GND QOUTN QOUTP GND VCC CLK DATA EN LD CX24109 30 29 28 27 26 25 CLKREFOUT VCC GND GND VCC GND GND VCC XTAL1 XTAL2 LPFILT GND 102031_002 1.2 Table 1. Pin Description Pin Description Pin Name RFIN AGC Pin No. 4 37 I/O I I RF input signal pin. Description AGC control input from the demodulator/FEC IC. It controls the gain of the RF attenuator and both baseband amplifiers. Minimum gain occurs at minimum voltage. Input impedance zin = 1 MΩ//20 pF.. Baseband filter control input from the demodulator/FEC IC. Minimum BW occurs at minimum voltage. Zin = 17 kΩ//20 pF. FILTUNE 36 I CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 11 NXP Semiconductors CX24109 Chapter 1: Functional Description Table 1. Pin Description Pin Name TUNERES IOUTP, IOUTN QOUTP, QOUTN DCIP, DCIN DCQP, DCQN LPFILT Pin No. 12 34, 35 31, 32 8, 9 10, 11 20 I/O — O O — — — Description Filter reference. A resistor to ground from this pin sets the reference current for the tunable filter. See Figure 6 and Figure 7. I channel output to the demodulator/FEC IC. Can be used balanced or single-ended. Zout = 1 kΩ//10 pF. Q channel output to the demodulator/FEC IC. Can be used balanced or single-ended. Zout = 1 kΩ//10 pF. I channel DC offset cancellation. A capacitor must be placed between these pins. See Figure 6 and Figure 7. Q channel DC offset cancellation. A capacitor must be placed between these pins. See Figure 6 and Figure 7. Loop filter. A network with a capacitor in parallel with a series resistor and capacitor connected from this pin to ground determines the loop filter bandwidth. See Figure 6 and Figure 7. Clock reference output. This pin provides the reference clock for the demodulator/FEC IC. The maximum load allowed at this node is ZLOAD = 10 kΩ//20 pF. Crystal inputs. A 10.111 MHz, series-resonant, fundamental crystal is placed between these two pins to create the system clock. See Figure 6 and Figure 7. Serial bus clock signal. Serial bus latch enable. Serial bus data pin. The lock detect signal to the demodulator/FEC IC. ZLOAD = 10 kΩ//20 pF. High is the locked state. CLKREFOUT XTAL1, XTAL2 CLK EN DATA LD 24 16, 17 28 26 27 25 O — I I I O Table 2. Power Supply and Ground Pins Pin Name VCC Pin No. 1, 13, 18, 22, 29, 38, 40, 42, 44, 47 2, 3, 5, 6, 7, 14, 15, 19, 21, 23, 30, 33, 39, 41, 43, 45, 46, 48 I/O P +5 V power supply Description GND P Ground 1.3 Application Overview Several million Satellite Set-Top Boxes (STBs) are deployed in many different entertainment networks around the world today. The standards for each network may vary a little but the requirements for the tuner in the STB are essentially the same. Each receiver system in the CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 12 NXP Semiconductors CX24109 Chapter 1: Functional Description network requires an antenna, a Low Noise Block (LNB) downconverter, a drop cable, and an STB. The LNB converts the satellite downlink frequency to an intermediate L-band frequency where it is passed to the STB via the drop cable. The STB front end consists of a tuner and a demodulator/FEC IC. The satellite tuner must tune to the L-band frequency, downconvert the carrier, and separate it to baseband I and Q signals. The demodulator/FEC IC includes QPSK Demodulation, carrier tracking, AGC control, bit timing, and the required FEC for a given network service. Figure 2 illustrates a typical application block diagram for the CX24109/CX24121 chip set in an STB front end. Figure 2. QPSK Demodulation Typical Application Block Diagram LNB Dish Antenna CX24109 RF Tuner IC IOUTP IOUTN I_N Q_N CX24121 Demod/FEC IC 8 To MPEG Processor RS_DATA[7:0] RS_CLK RSCntl1 Drop Cable RFIN QOUTN QOUTP XTAL1 AGC AGCV RSCntl2 XTAL2 CLKREFOUT FILTUNE FILTERV Tuner_Data Tuner_Clk CONTROL LD TUNERES LD Tuner_En Tuner Control 3 XTAL_IN LPFILT 102031_003 1.4 Signal Path The CX24109 is a highly integrated, direct-down conversion satellite tuner. It consists of an LNA, variable RF attenuator, quadrature downconverter, variable IF gain amplifiers, variable low-pass filters, VCO, and synthesizer. A detailed block diagram of the IC is illustrated in Figure 3. CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 13 NXP Semiconductors CX24109 Chapter 1: Functional Description Figure 3. Detailed Functional Block Diagram VGA1 Variable Low Pass Filter VGA2 IOUTP IOUTN VCA 90 Degree Splitter and Divide by 2 or 4 TUNERES RFIN QOUTP QOUTN FILTUNE AGC AGC Control Crystal Cell XTAL1 XTAL2 CLKREFOUT Divide by 10, 20, 40 Phase Detector Charge Pump Voltage Controlled Oscillator 32/33 Prescaler Divide by 2 Lock Detect LPFILT CLK DATA EN 9 Bit Counter Control Interface 5 Bit Counter LD 102031_004 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 14 NXP Semiconductors CX24109 Chapter 1: Functional Description The L-band output from the LNB enters the IC through the RFIN pin and is immediately amplified by the Voltage Controlled Attenuator block (VCA). The VCA functions as a variable gain LNA. The noise figure and gain of the VCA are the dominant factors for the tuner’s noise figure. The signal is then quadrature downconverted to I and Q baseband channels. Additional amplifiers at baseband provide more variable gain for the AGC loop. Also at baseband, variable low-pass filters provide anti-alias filtering and eliminate noise power from adjacent carriers and spurious signals before they can impact the A/Ds in the demodulator IC. 1.5 AGC and Control The AGC functionality for the CX24109 is split between the RF and baseband sections, and provides 80 dB of variable gain. The primary control for the AGC is an analog voltage from the demodulator IC. Programmable adjustments to the slope and offset of each variable gain component in the tuner are available through the AGC control registers. Programming information for the VGA and VCA is provided in Tables 4 and 5, respectively. The recommended default values for the programmable control bits versus symbol rate are listed in Table 8. 1.6 Local Oscillator The local oscillator consists of a synthesizer and a VCO block, and is contained entirely within the CX24109. The VCO block uses an innovative architecture that requires only a 5 V source, eliminating the need for a 28 V power supply. It includes the required tank circuit. The VCO block consists of a bank of eight oscillators operating at twice and four times the input frequency with a continuous range from 2200 MHz to 4400 MHz. The VCOs overlap to cover the frequency range from 950 MHz to 2150 MHz under all voltage, temperature, and process variations. The VCO tuning range, combined with programmable ÷2 or ÷4 frequency dividers, creates the continuous frequencies from 950 MHz to 2150 MHz for the local oscillator. A simple tuning algorithm must be run by the host processor one time at power-up to calibrate the VCO block. Conexant provides this program. The synthesizer is also contained within the CX24109. It uses a 10.111 MHz reference frequency and a reference divider, ÷R, to set the phase comparison frequency. Two programming bits are used to configure the reference divider to divide by 10, 20, or 40, which in turn sets the comparison frequency to 1.0111 MHz, 505 kHz, or 253 kHz, respectively. A reference divider of 10 is recommended. The comparison frequency also determines the frequency step size of the local oscillator. Another programmable divider is provided for the VCO output. It consists of a 32/33 prescaler, a 9-bit N-counter (N-divider), a 5-bit A-counter (A-divider), and a fixed ÷ 2 block. The programmable divider divides the VCO output from its highest frequency to the minimum phase comparison frequency. The programmable charge pump includes output currents of 1 mA, 2 mA, 3 mA, and 4 mA. Programming information for the synthesizer can be found in Table 7. The recommended values for charge pump current, polarity, and referenced dividers are listed in Tables 9 and 10. The typical loop filter bandwidth is set with external passive components and should be set between 8 kHz and 15 kHz. 1.7 Programming Interface A three-wire serial interface with Clock, Data, and Enable lines is used to program the CX24109. All digital signals are CMOS-compatible. The serial data carries the binary settings for the programmable dividers, the VCO band select, the voltage-controlled attenuator, and the voltage-controlled amplifiers. When the Enable line is low, data is shifted into an internal shift register on the rising edge of the clock, and when the Enable line goes high, the stored data is latched. The clock signal should be kept low when inactive. The maximum clock rate is 1 MHz. Figure 4 illustrates the relationship between the Clock, Data, and Enable signals. CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 15 NXP Semiconductors CX24109 Chapter 1: Functional Description Figure 4. Serial Interface Programming Example Clock ... ... Data Enable 102031_005 The internal shift register in the CX24109 is 21 bits long. When the data is latched into the IC, the two MSBs act as control bits, and the lower 19 bits are the data bits as illustrated in Figure 5. Data must be entered MSB first. Figure 5. MSB d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 Programming Word Configuration LSB d0 Control Bits Data Bits 102031_006 The control bits determine the functional block that is being programmed, while the data bits contain the specific control information. Table 3 provides a detail mapping of the control and data bits. Table 3. Programming Bit Mapping (Sheet 1 of 2) Programming Bit Mapping 20 MSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB Band Select 0 0 R R R R R R R R(1) R V R(1) Band Select VGA Programming 0 1 R VGA2 Offset VCA Programming 1 0 R VCA Offset PLL Programming VCA Slope VGA1 Offset CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 16 NXP Semiconductors CX24109 Chapter 1: Functional Description Table 3. Programming Bit Mapping (Sheet 2 of 2) Programming Bit Mapping 1 1 ÷R Divider P Charge Pump Current MSB ÷ N Divider(2) LSB MSB ÷A Divider(2) LSB GENERAL NOTES: 1. R means Reserved except for ÷R which means reference divider. P means Charge Pump Polarity V means VCO Divide Select FOOTNOTES: (1) These Reserved locations must be set to zero. All other Reserved location values do not matter. (2) These Divide ratios are binary coded. CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 17 NXP Semiconductors CX24109 Chapter 1: Functional Description Table 4. Band Select Programming Band Select Bit 7 0 1 0 0 0 0 0 0 0 1 Bit 6 1 0 0 0 0 0 0 0 1 0 Bit 5 0 0 0 0 0 0 0 1 0 0 Bit 4 0 0 0 0 0 0 1 0 0 0 Bit 3 0 0 0 0 0 1 0 0 0 0 Bit 2 0 0 0 0 1 0 0 0 0 0 Bit 1 0 0 0 1 0 0 0 0 0 0 Bit 0 0 0 1 0 0 0 0 0 0 0 Typical Receive Frequency Range (MHz) 950–1019 1019–1075 1075–1178 1178–1296 1296–1432 1432–1576 1576–1718 1718–1856 1856–2036 2036–2150 VCO Number 7 8 1 2 3 4 5 6 7 8 VCO Divider 4 4 2 2 2 2 2 2 2 2 VCO Divide Select Bit 9 0 1 Function ÷4 ÷2 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 18 NXP Semiconductors CX24109 Chapter 1: Functional Description Table 5. VGA Programming VGA1 Offset Bit 8 1 1 1 1 1 1 1 1 0 Bit 7 1 1 1 1 1 1 1 0 0 Bit 6 1 1 1 1 1 1 0 0 0 Bit 5 1 1 1 1 1 0 0 0 0 Bit 4 1 1 1 1 0 0 0 0 0 Bit 3 1 1 1 0 0 0 0 0 0 Bit 2 1 1 0 0 0 0 0 0 0 Bit 1 1 0 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0 0 Offset in dB –27.0 –28.5 –30.0 –31.5 –33.0 –34.5 –36.0 –37.5 –39.0 VGA2 Offset Bit 17 1 1 1 1 1 1 1 1 0 Bit 16 1 1 1 1 1 1 1 0 0 Bit 15 1 1 1 1 1 1 0 0 0 Bit 14 1 1 1 1 1 0 0 0 0 Bit 13 1 1 1 1 0 0 0 0 0 Bit 12 1 1 1 0 0 0 0 0 0 Bit 11 1 1 0 0 0 0 0 0 0 Bit 10 1 0 0 0 0 0 0 0 0 Bit 9 0 0 0 0 0 0 0 0 0 Offset in dB 35 32 29 26 23 20 17 14 11 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 19 NXP Semiconductors CX24109 Chapter 1: Functional Description Table 6. VCA Programming VCA Slope Bit 8 0 0 0 0 0 0 0 0 1 Bit 7 0 0 0 0 0 0 0 1 1 Bit 6 0 0 0 0 0 0 1 1 1 Bit 5 0 0 0 0 0 1 1 1 1 Bit 4 0 0 0 0 1 1 1 1 1 Bit 3 0 0 0 1 1 1 1 1 1 Bit 2 0 0 1 1 1 1 1 1 1 Bit 1 0 1 1 1 1 1 1 1 1 Bit 0 1 1 1 1 1 1 1 1 1 Slope in dB/V 47.0 49.5 52.0 54.5 57.0 59.5 62.0 64.5 67.0 VCA Offset Bit 17 0 0 0 0 0 0 0 0 1 Bit 16 0 0 0 0 0 0 0 1 1 Bit 15 0 0 0 0 0 0 1 1 1 Bit 14 0 0 0 0 0 1 1 1 1 Bit 13 0 0 0 0 1 1 1 1 1 Bit 12 0 0 0 1 1 1 1 1 1 Bit 11 0 0 1 1 1 1 1 1 1 Bit 10 0 1 1 1 1 1 1 1 1 Bit 9 1 1 1 1 1 1 1 1 1 Offset in dB 90.00 94.25 98.50 102.75 107.00 111.25 115.50 119.75 124.00 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 20 NXP Semiconductors CX24109 Chapter 1: Functional Description Table 7. PLL Programming Charge Pump Current Bit 15 0 0 1 1 Bit 14 0 1 0 1 Current (mA) 1 2 3 4 Charge Pump Polarity Bit 16 0 1 Function Positive Negative Reference Dividers Bit 18 0 0 1 1 Bit 17 0 1 0 1 Function — Reserved Reserved ÷10 1.7.1 Gain Equations The RF block voltage gain (GRF) is equal to the VCA gain + the mixer gain. G RF = V AGC × VCA Slope – VCA Offset ( in dB ) + 23 where the maximum value of G RF is 23 dB, regardless of voltage VGA1 voltage gain ( G VGA1 ) is equal to G VGA1 = V AGC × 26 + VGA1 Offset ( in dB ) VGA2 voltage gain ( G VGA2 ) is equal to G VGA2 = VGA2 Offset ( in dB ) The total baseband voltage gain ( GBaseband ) is equal to G Baseband = G VGA1 + G Filter + G VGA2 = G VGA1 + 3 + G VGA2 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 21 NXP Semiconductors CX24109 Chapter 1: Functional Description 1.7.2 Frequency Equations The VCO frequency is determined by F VCO = ( F Crystal ÷ R ) × ( N + ( A ÷ 32 ) ) × 32 × 2 = ( 10.111 ÷ R ) × ( N + ( A ÷ 32 ) ) × 32 × 2 NOTE: If A = 0, then N = N + 1 Remember, the incoming receive frequency is always lower than the VCO frequency, such that: F Receive = F VCO ÷ 2 or F VCO ÷ 4 1.7.3 Table 8. Recommended Default Values Recommended AGC Programming Values VCA and VGA Slope and Offset vs. Symbol Rate Symbol Rate 1 to 5 MSps Condition VGA2 Slope (dB/ V)(2) 0 VCA Slope (dB/V) 52 VCA Offset (dB)(1) 98.5 (102.75) 98.5 (107) 98.5 (111.25) VGA1 Slope (dB/V)(2) 26 VGA1 Offset (dB) –30 VGA2 Offset (dB) 29 FILTUNE Voltage (V) 0.41 5 to 15 MSps 57 26 –33 0 17 0.90 15 to 45 MSps 59.5 26 –36 0 14 2.70 FOOTNOTES: (1) There is an interaction between the offset and slope settings in the RF block, so the actual settings will be different from the theoretical setting. Theoretical settings are given in parentheses. (2) These values are for reference only. They are not programmable. Table 9. Recommended VCO Frequency vs. Charge Pump Current VCO Frequency Lower 50% VCO Frequency Range Upper 50% of VCO Frequency Range Charge Pump Current 2 mA 3 mA Table 10. Recommended Charge Pump Polarity and Reference Divider Values Feature Charge Pump Polarity Reference Divider Specification Negative ÷10 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 22 CX24109 Chapter 2: Applications Rev. 01 — 13 November 2008 Product data sheet 2.1 AGC Input To prevent excessive current draw, a 10 kΩ resistor on the AGC pin is recommended. See Figure 6. 2.2 VCO Power Pin Ripple Requirement Care must be taken to reduce the power supply ripple on pin 13 (VCO power supply) in order to reduce phase noise. The power supply conditioning circuitry given in Figure 6 is suitable for most circumstances. 2.3 Transmission Lines Though the CX24109’s RF layout is simple, there are two transmission lines that must be designed. The first transmission line is the LNB power line, which is located at the connector. The second transmission line is between the connector and the RF IN pin. The input transmission line must have a characteristic impedance of 75 Ω. The schematic gives recommended dimensions assuming a two-layer FR-4 board. 2.4 Example Schematic Figure 6 provides a simplified version of the CX24109/CX24121 reference design. For complete and current reference design information, contact your local Conexant sales office. CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 23 NXP Semiconductors CX24109 Chapter 2: Applications Figure 6. Simplified Application Schematic (Page 1 of 2) 5 V_RF LNB_POWER C104 C106 33 p C107 0.01 µF 47 p L103 BEAD C105 33 p C108 33 p C109 1n C110 1n W = 0.5 mm, L = 27 mm, H = 1.6 mm FR-4 47 44 42 40 38 37 AGC FILTUNE AGC1_VCC ATTEN_VCC1 ATTEN_VCC3 MIX_VCC RF_IN F Connector 3 J1 1 W = 1.4 mm L = 1.6 mm H < 10 mm FR-4 75 Ω C101 FILT_VCC AGC C103 33 p 1 4 FILTUNE I_OUTN I_OUTP Q_OUTN Q_OUTP 36 35 34 32 31 29 28 27 26 25 C111 0.047 µF I_OUT C112 0.047 µF C113 0.047 µF Q_OUT ATTEN_VCC2 RF_IN RF_GND 3.3 pF 2 22 pF C121 0.047 µF C120 0.047 µF R101 1.2 k 5 8 9 10 11 DC_IP DC_IN DC_QP DC_QP TUNERES SYNTH_VCC CKREF_OUT VCO_VCC OSC_VCC CX24109 AGC2_VCC CLK DATA EN LD CLK DATA LE LD GND (1) 13 17 20 22 16 18 24 C119 10 n LP_ILT XTA1 XTA2 CLKREF _OUT C114 1n 10.111 Series C118 100 u R105 8.2 L102 BEAD 5 V_RF C117 10 n C116 6.8 n Y1 R102 1.0 k C115 33 n FOOTNOTE: (1) Ground pins include: 2, 3, 5, 6, 7, 14, 15, 19, 21, 23, 30, 33, 39, 41, 43, 45, 46, and 48 102031_007 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 24 NXP Semiconductors CX24109 Chapter 2: Applications Figure 7. Simplified Application Schematic (Page 2 of 2) +3.3 V C602 0.047 uF C535 0.047 uF R515 30.9 KΩ 1% C536 0.01 uF C534 0.01 uF C532 0.01 uF C533 0.01 uF AGC FILTUNE 2 Vcm 1 PWR (2) Iref I_OUT Q_OUT AD_VAA AD_VAA AD_VDD 72 3 5 CX24121 CLK DATA LE LD R208 300 C205 100 p C206 100 p R203 300 C204 0.1 u R204 300 R205 300 R206 300 R207 10 K 68 LD 67 66 65 63 64 TUNER_EN TUNER_DATA TUNER_CLK AGCV FILTERV GPIO_1 (LNB_DC) LNB_22K 55 56 LNB Control CLKREF _OUT C209 0.1 u C207 100 p C208 0.1 u 41 TEST_MODE 11 79 77 XTAL_IN I_N Q_N (3) RS_DATA RS_CLK RSCntl1 Interrupt (RSSYNC) RSCntl2 32 37 47 38 To MPEG Processor 80 C861 0.01 µF 78 C863 0.01 µF I_P Q_P R306 33 SER_CLK SER_DATA R307 33 GND (1) SER_CLK SER_DATA 45 46 FOOTNOTE: (1) Ground Pins include: 4, 6, 8, 10, 15, 26, 30, 34, 50, 52, 62, 70, and 71. (2) Core (1.8 V) power pins include: 7, 9, 14, 29, 49, and 69. 3.3 V power pins include: 25, 33, 51, and 61. (3) RS_DATA includes RS_DATA0–RS_DATA7 pins 35, 31, 28, 27, 24, 23, 22, and 21. 102031_008 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 25 NXP Semiconductors CX24109 Chapter 2: Applications 2.5 Figure 8. Typical Performance Curves Reflection Coefficient at Input of CX24109 CX24109 S11 m1 Freq = 950 MHz plot_vs(S(1,1), freq) = –0.19 + j0.21 Impedance = 31.629 + j14.373 m2 Freq = 1.20 GHz plot_vs(S(1,1), freq) = 0.39/65.79 Impedance = 51.055 + j42.441 m3 Freq = 2.15 GHz plot_vs(S(1,1), freq) = 0.29/–2.11 Impedance = 89.855 – j2.055 S11 Frequency (950.0 MHz to 2.200 GHz) 102031_020 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 26 NXP Semiconductors CX24109 Chapter 2: Applications Figure 9. Baseband Filter Gain vs. Frequency and FILTUNE Voltage 10 FILTUNE = 0.5 V FILTUNE = 1.0 V 0 FILTUNE = 1.5 V FILTUNE = 2.0 V FILTUNE = 2.5 V FILTUNE = 3.0 V –10 –20 Gain (dB) –30 –40 –50 –60 –70 0 5 10 15 20 25 30 35 40 45 Frequency (MHz) Figure 10. Filter –3 dB Bandwidth vs. FILTUNE Voltage 30 25 –3dB Bandwodth of Filter (MHz) 20 15 10 5 0 0 0.5 1 1.5 FILTUNE Voltage (V) 2 2.5 3 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 27 NXP Semiconductors CX24109 Chapter 2: Applications Figure 11. Gain and IIP3 vs. AGC Voltage at 950 MHz 85 80 75 70 65 60 55 50 Gain and IIIP3 (dB) 45 40 35 30 25 20 15 10 5 0 –5 –10 1 1.5 2 AGC Voltage (V) 2.5 3 IIIP3 Gain Figure 12. Gain and IIP3 vs. AGC Voltage at 2150 MHz 85 80 75 70 65 60 55 Gain and IIIP3 (dB) 50 45 40 35 30 25 20 15 10 5 0 –5 –10 1.2 1.7 2.2 AGC Voltage (V) 2.7 3.2 IIIP3 Gain CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 28 NXP Semiconductors CX24109 Chapter 2: Applications Figure 13. Gain and NF vs. AGC Voltage at 950 MHz 85 80 75 70 65 60 55 Gain and NF (dB) 50 45 40 35 30 25 20 15 10 5 0 –5 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 AGC Voltage (V) Gain Noise Figure Figure 14. Gain and NF vs. AGC Voltage at 2150 MHz 85 80 75 70 65 60 55 Gain and NF (dB) 50 45 40 35 30 25 20 15 10 5 0 –5 –10 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 AGC Voltage (V) Gain Noise Figure CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 29 NXP Semiconductors CX24109 Chapter 2: Applications CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 30 CX24109 Chapter 3: Parametric Data and Specifications Rev. 01 — 13 November 2008 Product data sheet 3.1 Electrical Specifications Table 11. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Range Storage Temperature Junction Temperature Minimum –0.3 –0.3 –65 — Maximum 6 Vcc +0.3 +150 +150 Units V V °C °C 3.1.1 Standard Operating Conditions All specifications are valid under the operating conditions indicated in Tables 8, 9, 10, and 12. Table 12. Operating Conditions Parameter Ambient Operating Temperature Maximum Operating Junction Temperature Supply Voltage Reference Oscillator Frequency Reference Oscillator Frequency Stability Loop Filter Bandwidth Conditions — — — Series resonant, fundamental Including temperature drift — Min 0 — 4.75 — — — Typ +25 — 5.0 10.111 — 10 Max +70 125 5.25 — +100 — Units °C °C V MHz ppm kHz CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 31 NXP Semiconductors CX24109 Chapter 3: Parametric Data and Specifications Table 13. DC Electrical Characteristics Parameter Supply Current(1) Usable AGC Voltage Range, VAGC Impedance of AGC Input AGC Current, IAGC Usable Filtune Voltage Range, VFiltune Impedance of Filtune Input Thermal Resistance of Package Conditions — — at DC — — at DC θja(2) θjc Min — 1.3 — — 0 — — — Typ 244 — 1 — — 17 42 8.7 Max 262 2.80 — 0.4 3.0 — — — Units mA V MΩ mA V kΩ °C/W °C/W FOOTNOTES: Using 15–45 MSps programming values (see Table 8), Vcc = 5.0 V, VAGC = 1.45 V, VFiltune = 2.7 V. (2) Using a 2-layer CX24109/CX24121 reference design, where the package’s exposed paddle is connected to the printed circuit board ground plane using thermal vias. The ground plane on the reference design is approximately 2-7/8 inches x 1-1/4 inches. Better thermal performance can be obtained by increasing ground plane coverage or increasing the number of attached printed circuit board layers. (1) Table 14. AC Electrical Characteristics Parameter Programming Clock Frequency Bus Timing Data Setup, tSU Data Hold, tHD Enable Pulse Width, tEW Clock to Enable, tCE Programming Lines: Clock, Data, Enable VIH VIL IIH IIL LD and CLKREFOUT VOH VOL Conditions — See Figure 15. Min — — — 1 — Typ — 10 10 — 1 — — — — 2.65 0.9 Max 1 — — — — — 0.8 0.5 –0.5 — 1.125 Units MHz ns ns μs μs V V mA mA V V — — — — — — 2.1 — — — 2.3 — CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 32 NXP Semiconductors CX24109 Chapter 3: Parametric Data and Specifications Figure 15. Serial Programming Example Clock ... ... tHD tsu tce tew 102031_016 Data Enable Table 15. RF Electrical Characteristics (Sheet 1 of 3) Parameter Tuning Frequency Input Power, Single Tone(1) Aggregate Input Power(1)(2) Input Impedance, Balanced(1) Input VSWR(1) Iout and Qout Output Voltage Maximum Conversion (Voltage) Gain Minimum Conversion (Voltage) Gain Noise Figure (NF)(1) (3) RLoad = 1 kΩ Conditions — Depends on bandwidth of incoming signal and C/I — ZSOURCE = 75 Ω — Min 950 –81 — — — — 76 8 — Typ — — — 75 10 0.5 86 18 36 Max 2150 –23 –7 — — — 91 23 42 Units MHz dBm dBm Ω dB VP-P dB dB dB VAGC=2.4 V, 1 MSps gain coefficients(1) VAGC=1.45 V, 45 MSps gain coefficients(1) Pin = –43 dBm, 1–5 MSps gain coefficients(4) Pin = –81 dBm, 1–5 MSps gain coefficients(5) Pin = –34.5 dBm, 5–15 MSps gain coefficients(6) Pin = –72 dBm, 5–15 MSps gain coefficients(7) Pin = –30 dBm, 15–45 MSps gain coefficients(8) Pin = –70 dBm, 15–45 MSps gain coefficients(9) — 10.5 14 dB — 35 42 dB — 10.5 14 dB — 35 45 dB — 10.5 14 dB CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 33 NXP Semiconductors CX24109 Chapter 3: Parametric Data and Specifications Table 15. RF Electrical Characteristics (Sheet 2 of 3) Parameter IIP3 (Out-of-band)(1) (4) Conditions +(31 and 60) MHz, Pin = –42 dBm, 1–5 MSps gain coefficients(4) +(91 and 180) MHz, Pin = –42 dBm, 1–5 MSps gain coefficients(4) +(31 and 60) MHz, Pin = –81 dBm, 1–5 MSps gain coefficients +(91 and 180) MHz, Pin = –81 dBm, 1–5 MSps gain coefficients(5) +(31 and 60) MHz, Pin = –34.5 dBm, 5–15 MSps gain coefficients(6) +(91 and 180) MHz, Pin = –34.5 dBm, 5–15 MSps gain coefficients(6) +(31 and 60) MHz, Pin = –72 dBm, 5–15 MSps gain coefficients(7) +(91 and 180) MHz, Pin = –72 dBm, 5–15 MSps gain coefficients(7) +(31 and 60) MHz, Pin = –30 dBm, 15–45 MSps gain coefficients(8) +(91 and 180) MHz, Pin = –30 dBm, 15–45 MSps gain coefficients(8) +(31 and 60) MHz, Pin = –70 dBm, 15–45 MSps gain coefficients(9) +(91 and 180) MHz, Pin = –70 dBm, 15–45 MSps gain coefficients(9) Min –2 Typ 4.0 Max — Units dBm 5.5 9.4 — dBm –35 –25.0 — dBm –39 –7.2 — dBm 0 5.0 — dBm 5.5 9.8 — dBm –35 –25.5 — dBm –30 –2 –6.5 5.5 — — dBm dBm 5.7 10.5 — dBm –35 –24.5 — dBm –28 –6.5 — dBm IIP3I (Inband) 1 MSps coefficients and VAGC = 1. 5 V(1) 1 MSps coefficients and VAGC = 2.4 V(1) — — — — — –30 –30 –30 –65 3 1 –80 –45 –50 — — 13 3 –70 — — dBm dBm +deg +dB dBm dB dB I/Q Phase Difference I/Q Amplitude Ratio LO Leakage 2LO-RF Rejection 2RF-LO Rejection 950 to 2150 MHz(1) — — C/I = 10 dB VAGC = 1.5 V(1) C/I = 10 dB(1) CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 34 NXP Semiconductors CX24109 Chapter 3: Parametric Data and Specifications Table 15. RF Electrical Characteristics (Sheet 3 of 3) Parameter Conditions VCO and Synthesizer Min Typ Max Units Reference Oscillator Phase Noise Spurious Measured at 400 Hz At 1, 10.111, and 30 MHz offsets with 2 mA charge pump and 10 kHz loop BW — 10 kHz offset 100 kHz offset — –30 –130 –45 — — dBc/Hz dBc VCO Tuning Sensitivity LO Phase Noise at 950 MHz–1450 MHz 100 — — — — — — — –75 –97 –69 –94 — 1 330 — — — — –158 — MHz/V dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ms LO Phase Noise at 1450 MHz–2150 MHz 10 kHz offset 100 kHz offset LO Phase Noise at 950 MHz–2150 MHz Local Oscillator Settling Time 10 kHz offset +100 kHz offset All frequencies, VCOs and modes GENERAL NOTES: 1. Values in this table are valid under the operating conditions listed in Tables 8, 9, and 10, using a reference divider of 10, unless otherwise stated. FOOTNOTES: (1) This measurement is made at RFIN of CX24109. (2) Aggregate average power of 40 QPSK modulated carriers. (3) All NF and IIP3 measurements/specifications are made by setting a specific input level for the desired symbol rate and adjusting the AGC level to obtain the desired output level of 0.5 Vpp. (4) This level is derived assuming –23 dBm is the maximum level of all other transponders and that the operating symbol rate is 1 MSps. Assume C/I of 7 dB and a bandwidth scaling of 10 log (20 MHz / 1 MHz), thus, Pin = –23 dBm – 7 dB – 10 log (20 / 1) = –43 dBm. (5) This level is derived from Pin = P Transponder – LPath + GAntenna + GLNBmin – LCable. Where the operating symbol rate is 1 MSps and PTransponder is at a minimum. PTransponder = 10 log ((1E6 / 45E6) 10 (82 – 4) /10) = +61 dBm. Therefore, Pin = + 61 dBm – 205 dB + 38 dB + 45 dB – 20 dB = –81 dBm. (6) This level is derived assuming –23 dBm is the maximum level of all other transponders and that the operating symbol rate is 7 MSps. Assume C/I of 7 dB and a bandwidth scaling of 10 log (20 MHz / 7 MHz), thus, Pin = –23 dBm – 7 dB – 10 log 20 / 7 = –34.5 dBm. (7) This level is derived from Pin = PTransponder – LPath + GAntenna + GLNBmin – LCable. Where the operating symbol rate is 7 MSps and PTransponder = 10 log ((7E6 / 45E6) 10 (82–4)/10) = +70 dBm. Therefore, Pin = +70 dB – 205 dB + 38 dB + 45 dB – 20 dB = –72 dBm This level is derived assuming –23 dBm is the maximum level of all other transponders, an operating symbol rate of 20 MSps and a C/I of 7 dB. (9) Assume a symbol rate of 20 MSps. (8) CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 35 NXP Semiconductors CX24109 Chapter 3: Parametric Data and Specifications Table 16. Baseband Frequency Response Parameter Minimum Cutoff Frequency, F1 dB Minimum Cutoff Frequency, F1 dB Tuning Voltage Transfer Function Passband Ripple Stopband Attenuation Stopband Attenuation Conditions Measured at minimum VFiltune Measured at maximum VFiltune 0 V < VFiltune < 3.0 V 0 < Freq < F1 dB F > 2.6 × F1 dB 5 × F1 dB < F < 2 GHz Min 1.4 27 — — 35 45 Typ — — 10.5 — — — Max 2.6 — — 1.0 — — Units MHz MHz MHz/V dB dB dB 3.2 Figure 16. Mechanical Specifications 48-pin eTQFP Land Pattern LAND PATTERN - 48 ETQFP 0.965 REF. PWB Exposed Pad 5.070 REF. 3x3 Array of Thermal Vias 0.330 mm Dia. Spacing TBD 1.215 REF. 4.570 REF. Mask Opening Thermal Vias Should be Tinted Using 0.430 mm Dia. Solder Mask 4.570 REF. 0.250 5.070 REF. 0.250 0.965 REF. 0.500 1.215 REF. 1.000 8.400 REF. 11 EQ SP @ 0.50 = 5.50 TYP 9.400 REF. PWB METALIZATION PATTERN PWB SOLDER MASK PATTERN 102031_017 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 36 NXP Semiconductors CX24109 Chapter 3: Parametric Data and Specifications Figure 17. 48-pin eTQFP Package Diagram D Pin #1 Ref. Mark D1 D2 D D1 D1 D2 e b TOP VIEW BOTTOM VIEW Millimeters Dimension Min Max 1.20 MAX 0.05 0.95 9.00 BSC 7.00 BSC 4.50 REF 0.45 1.00 REF 0.50 BSC 0.17 0.09 0.08 MAX 0.27 0.20 0.007 0.004 0.75 0.018 0.15 1.05 0.002 0.037 Min Inches Max SIDE VIEW See Detail A A A1 A2 D D1 0.047 MAX 0.006 0.041 0.354 BSC 0.275 BSC 0.177 REF 0.030 0.039 REF 0.020 BSC 0.011 0.008 0.003 MAX A A2 c D2 L L1 e A1 DETAIL A L L1 b c Coplanarity 102031_018 CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 37 NXP Semiconductors CX24109 Chapter 3: Parametric Data and Specifications CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 38 NXP Semiconductors CX24109 Digital Satellite Tuner Legal information Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 39 NXP Semiconductors CX24109 Digital Satellite Tuner 40 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 November 2008 Document identifier: CX24109_N_1