NXP Semiconductors
Data Sheet: Technical Data
Document Number S32R274
Rev. 6, 06/2021
S32R274
S32R274/S32R264 Series
Data Sheet
Supports S32R274K, S32R274J,
S32R264K and S32R264J
Features
• On-chip modules available within the device include
the following features:
• Safety core: Power Architecture® e200Z4 32-bit CPU
with checker core
• Dual issue computation cores: Power Architecture®
e200Z7 32-bit CPU
• 2 MB on-chip code flash (FMC flash) with ECC
• 1.5 MB on-chip SRAM with ECC
• RADAR processing
– Signal Processing Toolbox (SPT) for RADAR signal
processing acceleration
– Cross Timing Engine (CTE) for precise timing
generation and triggering
– Waveform generation module (WGM) for chirp
ramp generation
– 4x 12-bit ΣΔ-ADC with 10 MSps
– One DAC with 10 MSps
– MIPICSI2 interface to connect external ADCs
• Memory Protection
– Each core memory protection unit provides 24
entries
– Data and instruction bus system memory protection
unit (SMPU) with 16 region descriptors each
– Register protection
• Clock Generation
– 40 MHz external crystal (XOSC)
– 16 MHz Internal oscillator (IRCOSC)
– Dual system PLL with one frequency modulated
phase-locked loop (FMPLL)
– Low-jitter PLL to ΣΔ-ADC and DAC clock
generation (not supported on SC66760x devices)
• Functional Safety
– Enables up to ASIL-D applications
– FCCU for fault collection and fault handling
– MEMU for memory error management
– Safe eDMA controller
– Self-Test Control Unit (STCU2)
– Error Injection Module (EIM)
– On-chip voltage monitoring
– Clock Monitor Unit (CMU)
• Security
– Cryptographic Security Engine (CSE2)
– Supports censorship and life-cycle management
• Timers
– Two Periodic Interval Timers (PIT) with 32-bit
counter resolution
– Three System Timer Module (STM)
– Three Software Watchdog Timers (SWT)
– Two eTimer modules with 6 channels each
– One FlexPWM module for 12 PWM signals
• Communication Interfaces
– Two Serial Peripheral interface (SPI) modules
– One LINFlexD module
– Two inter-IC communication interface (I2C)
modules
– One dual-channel FlexRay module with 128
message buffers
– Three FlexCAN modules with configurable buffers CAN FD optionally supported on 2 FlexCAN
modules
– One ENET MAC supporting MII/RMII/RGMII
interface
– ZipWire high-speed serial communication
• Debug Functionality
– 4-pin JTAG interface and Nexus/Aurora interface
for serial high-speed tracing
– e200Z7 core and e200Z4 core: Nexus development
interface (NDI) per IEEE-ISTO 5001-2012 Class 3+
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Two analog-to-digital converters (SAR ADC)
– Each ADC supports up to 16 input channels
– Cross Trigger Unit (CTU)
• On-chip voltage DC/DC regulator for core clock (VREG)
• Two Temperature Sensors (TSENS)
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
2
NXP Semiconductors
Table of Contents
1
2
Introduction........................................................................................ 4
8.4
Data retention vs program/erase cycles...................................39
1.1
Family comparison..................................................................4
8.5
Flash memory AC timing specifications.................................39
1.2
Feature list............................................................................... 5
8.6
Flash memory read wait-state and address-pipeline control
1.3
Block diagram......................................................................... 9
Ordering parts.....................................................................................9
2.1
3
4
5
6
8
9
Communication modules................................................................... 41
9.1
Ethernet switching specifications............................................41
Part identification............................................................................... 10
9.2
FlexRay timing parameters..................................................... 46
3.1
Description.............................................................................. 10
9.3
LVDS Fast Asynchronous Transmission (LFAST) electrical
3.2
Fields....................................................................................... 10
characteristics.......................................................................... 49
General............................................................................................... 11
9.4
Serial Peripheral Interface (SPI) timing specifications........... 53
4.1
Absolute maximum ratings..................................................... 11
9.5
LINFlexD timing specifications..............................................58
4.2
Operating conditions............................................................... 13
9.6
I2C timing .............................................................................. 58
4.3
Supply current characteristics................................................. 15
10 Debug modules...................................................................................59
4.4
Voltage regulator electrical characteristics............................. 16
10.1 JTAG/CJTAG interface timing .............................................. 59
4.5
Electromagnetic Compatibility (EMC) specifications............ 20
10.2 Nexus Aurora debug port timing.............................................62
4.6
Electrostatic discharge (ESD) characteristics......................... 20
11 WKUP/NMI timing specifications.....................................................63
I/O Parameters....................................................................................21
12 External interrupt timing (IRQ pin)................................................... 64
5.1
I/O pad DC electrical characteristics ......................................21
13 Temperature sensor electrical characteristics.....................................64
5.2
I/O pad AC specifications....................................................... 22
14 Radar module..................................................................................... 65
5.3
Aurora LVDS driver electrical characteristics........................ 23
14.1 MIPICSI2 D-PHY electrical and timing specifications.......... 65
5.4
Reset pad electrical characteristics..........................................24
14.2 MIPICSI2 Disclaimer..............................................................68
Peripheral operating requirements and behaviours............................ 26
15 Thermal Specifications.......................................................................70
6.1
7
Determining valid orderable parts...........................................9
settings.....................................................................................40
Clocks and PLL Specifications............................................... 26
15.1 Thermal characteristics........................................................... 70
Analog modules................................................................................. 29
16 Packaging........................................................................................... 72
7.1
ADC electrical characteristics.................................................29
17 Reset sequence................................................................................... 72
7.2
Sigma Delta ADC electrical characteristics............................ 33
17.1 Reset sequence duration.......................................................... 73
7.3
DAC electrical specifications..................................................36
17.2 Reset sequence description......................................................73
Memory modules............................................................................... 37
18 Power sequencing requirements.........................................................75
8.1
Flash memory program and erase specifications.................... 37
19 Pinouts................................................................................................76
8.2
Flash memory Array Integrity and Margin Read
specifications...........................................................................38
8.3
19.1 Package pinouts and signal descriptions................................. 76
20 Revision History.................................................................................76
Flash memory module life specifications................................38
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
3
Introduction
1 Introduction
1.1 Family comparison
The following table provides a comparison of the devices: S32R274, S32R264, and
MPC5775K . This information is intended to provide an understanding of the range of
functionality offered by this family. For full details of all of the family derivatives please
contact your marketing representative.
Table 1. S32R274 and S32R264 Family Comparison
Feature
S32R274K
S32R274J
CPUs
S32R264K
S32R264J
MPC5775K
266 MHz (z7
cores) / 133 MHz
(z4)
266 MHz (z7
cores) / 133 MHz
(z4)
e200z420 lock-step
2x e200z7260
SIMD
Maximum
Operating
Frequency
SPE2 + EFP2 (z7)
240 MHz (z7
cores) / 180 MHz
(z4)
266 MHz (z7
cores) / 133 MHz
(z4)
240 MHz (z7
cores) / 180 MHz
(z4)
Flash
2 MB with ECC
4 MB with ECC
EEPROM support
64 KB (emulation)
96 KB (emulation)
RAM
1.5 MB with ECC
ECC
end-to-end
MPU
Core MPU: 24 entries per core, System MPU: 2x16 entries
eDMA
safe eDMA with 32 channels, 64 triggers
Control ADC
SD-ADC
2x 12-bit SAR ADC, 1 MSps input mux for 16 external channels
4 channels, 10 MSps
–
SPT
1x
CTE
1x
WGM
1x
CTU
–
1x
4x 12-bit SAR
ADC, 1 MSps, input
mux for 37 external
channels
8 channels, 10
MSps
2x
SWT
3x
STM
3x
PIT
2x
CRC
2x
SEMA42
1x
LINFlexD
1x
4x
CAN
3x FlexCAN including 2x FlexCAN-FD
4x FlexCAN + 1x
MCAN-FD
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
4
NXP Semiconductors
Introduction
Table 1. S32R274 and S32R264 Family Comparison (continued)
Feature
S32R274K
S32R274J
S32R264K
S32R264J
MPC5775K
SPI
2x
4x
I2C
2x
3x
Zipwire
1x LFAST+SIPI, 320 MHz
FlexRay
1x dual channel
Ethernet
10/100 and >100 Mbps, RMII/MII/RGMII I/F, AVB support
10/100 Mbps,
RMII/MII I/F, AVB
support
FlexPWM
1x, 12 PWM channels
2x, 12 PWM
channels each
eTimer
2x, 6 channels each
3x, 6 channels
each
External ADC
interface
1x 4 lanes MIPICSI2 Rx, 1 Gbps/lane
1x PDI (16-bit data,
clock, sync)
IRCOSC
16 MHz
XOSC
40 MHz
FMPLL
dual system PLL, 1x FM modulated
DAC
–1
1x 12-bit 10 MSps
SIUL2
1x
BAM
1x
INTC
1x
SSCM
1x
FCCU/FOSU
1x
MEMU
1x
STCU2
1x
–1
1x 12-bit 2 MSps
CSE
1x
-
PASS/TDM
1x
-
MC_ME
1x
MC_CGM
1x
MC_RGM
1x
TSENS
2x
Debug
JTAGC, JTAGM, CJTAG, with class3+ Nexus, Aurora only
Safety level
ISO26262 SEooC ASIL-B to ASIL-D
Temp. range (Tj)
-40 to 150˚C
1. DAC is not supported in S32R264x devices. Hence, ignore its occurrences in this document for S32R264K and S32R264J.
1.2 Feature list
On-chip modules available within the device include the following features:
• Safety core: Power Architecture® e200Z4 32-bit CPU with checker core
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
5
Introduction
•
•
•
•
•
2 cycle delayed lockstep
Harvard architecture with 64-bit bus for data and instructions
Dual issue: up to two instructions per clock cycle
8 KB instruction cache and 4 KB data cache
64 KB data local memory
• with background load/store: backdoor access
• 0-wait state for all read and 32/64-bit write accesses
• Low number of wait states for backdoor accesses
• Support for decorated storage
• Variable Length Encoding (VLE) compliant for higher code density
• Single precision floating point operations
• Computation cores: Power Architecture® e200Z7 32-bit CPU
• Dual issue: up to two instructions per clock cycle
• Harvard architecture with 64-bit bus for data instructions
• 16 KB instruction cache and 16 KB data cache
• 64 KB data local memory
• with background load/store: backdoor access
• 0-wait state for all read and 32/64-bit write accesses
• Low number of wait states for backdoor accesses
• Support for decorated storage
• Using variable length encoding (VLE) for higher code density
• 4-way integer processing unit (SPE2)
• 2-way single-precision Floating Point Unit (EFPU2)
• 2 MB on-chip code flash (FMC flash) with ECC
• Three ports (one per CPU) shared between code and data flash with 4 × 256 bit
buffer for code and data flash including prefetch functions
• Data flash is part of the code flash module
• Including 64 KB EEPROM emulation
• 1.5 MB on-chip SRAM with ECC
• Decorated memory controller to support atomic read-modify-write operations
• Single- and double-bit error visibility is supported
• Up to four ports (one per CPU and SPT) and up to 8 banks allow simultaneous
accesses from different masters to different banks
• RADAR processing
• Signal Processing Toolbox (SPT) for RADAR signal processing acceleration
• Cross Timing Engine (CTE) for precise timing generation and triggering
• Waveform generation module (WGM) for chirp ramp generation
• 4x 12-bit ΣΔ-ADC with 10 MSps (not supported on S32R264 devices)
• One DAC with 10 MSps (not supported on S32R264 devices)
• MIPICSI2 interface to connect external ADCs
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
6
NXP Semiconductors
Introduction
•
•
•
•
•
•
• Four data lanes, with up to 1 Gbps per lane and in total
• One clock lane
Memory Protection
• Each core memory protection unit provides 24 entries
• Data and instruction bus system memory protection Unit (SMPU) with 16 region
descriptors each
• Register protection
Clock Generation
• 40 MHz external crystal (XOSC)
• 16 MHz Internal oscillator (IRCOSC)
• Dual system PLL with one frequency modulated phase-locked loop (FMPLL)
• Low-jitter PLL to ΣΔ-ADC and DAC clock generation
Functional Safety
• Enables up to ASIL-D applications
• End to end ECC ensuring full protection of all data accesses throughout the
system, from each of the systems masters through the crossbar and into the
memories and peripherals
• FCCU for fault collection and fault handling
• MEMU for memory error management
• Safe eDMA controller
• User selectable Memory BIST (MBIST) can be enabled to run out of various
reset conditions or during runtime
• Self-Test Control Unit (STCU2)
• Error Injection Module (EIM)
• On-chip voltage monitoring
• Clock Monitor Unit (CMU) to support monitoring of critical clocks
Security
• Cryptographic Security Engine (CSE2) enabling advanced security management
• Supports censorship and life-cycle management via Password and Device
Security (PASS) module
• Diary control for tamper detection (TDM)
Support Modules
• Global Interrupt controller (INTC) capable of routing interrupts to any CPU
• Semaphore unit to manage access to shared resources
• Two CRC computation units with four polynomials
• 32-channel eDMA controller with multiple transfer request sources using
DMAMUX
• Boot Assist Module (BAM) supports internal flash programming via a serial link
(LIN / CAN)
Timers
• Two Periodic Interval Timers (PIT) with 32-bit counter resolution
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
7
Introduction
•
•
•
•
•
• Three System Timer Module (STM)
• Three Software Watchdog Timers (SWT)
• Two eTimer modules with 6 channels each
• One FlexPWM module for 12 PWM signals
Communication Interfaces
• Two Serial Peripheral interface (SPI) module
• Two inter-IC communication interface (I2C) modules
• One LINFlexD module
• One dual-channel FlexRay module with 128 message buffers
• Three FlexCAN modules with configurable buffers
• CAN FD optionally supported on 2 FlexCAN modules
• One ENET MAC supporting MII/RMII/RGMII interface
• Supports 10/100 Mbps (MII/RMII/RGMII) and >100 Mbps (RGMII)
• Supports IEEE1588 timestamps and PTP
• Zipwire high-speed serial communication
• Supports LFAST and SIPI protocol
• Fast interprocessor communication with 320 Mbps gross data rate
• DMA based access to memory resources
Debug Functionality
• 4-pin JTAG interface and Nexus/Aurora interface for serial high-speed tracing
• e200Z7 core and e200Z4 core: Nexus development interface (NDI) per IEEEISTO 5001-2012 Class 3+
• All platform bus masters except CSE can be monitored via Nexus/Aurora
• Device/board boundary Scan testing supported with per Joint Test Action Group
(JTAG) (IEEE 1149.1) and 1149.7 (cJTAG)
• On-chip control for Nexus development interface by JTAGM module
Two analog-to-digital converters (SAR ADC)
• Each ADC supports up to 16 input channels
• Cross Trigger Unit to enable synchronization of ADC conversions with eTimer
On-chip voltage DC/DC regulator for core clock (VREG)
Two Temperature Sensors (TSENS)
S32R264 feature changes with respect to S32R274 are as follows:
• SD-ADC’s removed
• DAC removed
• SDPLL replaced with AFEPLL
• Improved radiated emissions in the GLONASS band. Full EMC reports are available
from NXP on request for both S32R264, and S32R274 to allow the customer to
select the most suitable part for their usecase.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
8
NXP Semiconductors
Ordering parts
1.3 Block diagram
FPU
64 KB
DTCM
4 KB
8 KB
ICache
DCache
Core MPU 24 Entries
BIU e2eECC
Core MPU 24 Entries
BIU e2eECC
IBus
IBus
IBus
CSE
SSCM
PIT_1
PIT_0
WKPU
BAM
DMAMUX_0
LFAST_0
SIPI
MC_CGM
MC_RGM
CSE
TDM
PASS
JTAGM
TDM
FlexCAN_1
VREG
STCU2
MEMU
CRC_0
FlexCAN_0
SPI_1
LINFlexD
FlexRAY
eTimer_1
ENET
ECC
Logic / Analogs
Debug
Memories
Peripherals already shown
explicitly in the block diagram
PASS
Triple Ported
Flash Controller
(PFLASH)
e2eECC
SIUL2
MC_ME
Core_1
Core_2
Core_0+
System memory Protection Unit SMPU_1
Core_2/
AHB
Bridge_0
CSE
up to 64 KB DFlash
eDMA
STM_0
STM_1
STM_2
SWT_1
SWT_2
INTC
SWT_0
PRAM
PFLASH
SEMA42
AXBS_1
SMPU_1
FPU
Delay/
RCCU
Instr. Crossbar Switch (AMBA 2.0 v6 AHB) 64- bit
Cal
1.5 MB SRAM
8 Banks
ECC
SMPU_0
VLE
Delay/
RCCU
TCM Backdoor e2eECC
e200z419
Checker Core0
VLE
all others
DBus
all others
Core_1
SPT
Core_0+
Quad Ported
SRAM Controller
(PRAM)
e2eECC
32-bit
DAC
XOSC
32-bit
SDADC[0:3]
SDPLL
SDVRegs
FlexCAN_2
I2C_1
NAP
DTS
Safety Lake
Nexus3+
2 MB Flash memory
SPI_2
I2C_2
MIPICSI2
eTimer_2
ADC_0
TCM_Core0/1/2
AIPS-Lite_0
e2eECC
e2eECC
FlexPWM_0
WGM_0
CMUs
CRC_1
AIPS-Lite_1
AXBS_0
VREG LVD
E200z420
Core0
NPC
NAL
e2eECC
Nexus Data
Trace
AIPS-Lite_0
TSENS_0/1
Dual
FMPLL
FCCU
BIU e2eECC
Data Crossbar Switch (AMBA 2.0 v6 AHB) 64 bit
XOSC
64 KB
DTCM
16 KB
DCache
Core MPU 24 Entries
System memory Protection Unit SMPU_0
IRCOSC
CRC_1
CRC_1
16 KB
ICache
SPE2
VFPU
AHB
Bridge_1
e2eECC
DBus
e2eECC
Nexus3+
e200z7260
Core1
VLE
PIT_0
SWT_0
STM_0
TCM Backdoor e2eECC
BIU e2eECC
Nexus Data
Trace
SDPLL
DMAMUX_1
64 KB
DTCM
16 KB
DCache
Core MPU 24 Entries
SD VREGs
CTU_0
SPE2
VFPU
16 KB
ICache
Safety Lake
Nexus Data
Trace
DAC
FlexRay
ENET
Delay/
RCCU
eDMA
e2eECC
eDMA
e2eECC
DMAMUX
Zipwire
Signal
Processing
Toolbox (SPT)
AIPS-Lite_1
Nexus3+
e200z7260
Core2
VLE
FastDMA
e2eECC
async
PIT_1
SWT_1
STM_1
SWT_2
STM_2
TCM Backdoor e2eECC
DMA
SRAM
(ECC)
Acquisition
FFT/
Processing
Sequencer
Local
SRAM
(ECC)
CJTAG
JTAGC
INTC
SPT
CTE_0
MIPICSI2
FR
ADC_1
4x
SDADC
MII/RMII/
RGMII
Zipwire
TCM Backdoor e2eECC
4x lanes
+ clock
DBus
4x analog
diff. input
Figure 1. S32R274 block diagram
NOTE
S32R264 devices support AFE PLL while S32R274 devices
support SDPLL.
2 Ordering parts
2.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to www.nxp.com and perform a part number search for the
device number.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
9
Part identification
3 Part identification
3.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
3.2 Fields
This section lists the possible values for each field in the part number (not all
combinations are valid):
Table 2. Configuration
257MAPBGA
Configuration
Performance
Temperature
FS32R274KSK2MMM
S
K
M
FS32R274KCK2MMM
C
K
M
FS32R274VBK2MMM
B
V
M
FS32R274VCK2MMM
C
V
M
FS32R274KSK2VMM
S
K
V
FS32R274KCK2VMM
C
K
V
FS32R274VBK2VMM
B
V
V
FS32R274VCK2VMM
C
V
V
FS32R274JSK2MMM
S
J
M
FS32R264KBK0MMM
B
K
M
FS32R264KCK0MMM
C
K
M
FS32R264JBK0MMM
B
J
M
FS32R264JCK0MMM
C
J
M
Table 3. Configuration
Configuration
2 MB Flash
1.5 MB RAM
CSE
B or S
Yes
Yes
Yes
C
Yes
Yes
No
Table 4. Performance
Perf (MHz)
Z7
Z7
Z4
Z4
K
240
240
120
120
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
10
NXP Semiconductors
General
Table 4. Performance (continued)
Perf (MHz)
Z7
Z7
Z4
Z4
V
200
200
100
100
J
266
266
133
133
Table 5. Temperature values
Temperature
TA
oC
to 125 oC
M
-40
V
-40 oC to 105 oC
4 General
4.1 Absolute maximum ratings
NOTE
Functional operating conditions appear in the DC electrical
characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maximum values is not
guaranteed.
Stress beyond the listed maximum values may affect device
reliability or cause permanent damage to the device.
Table 6. Absolute maximum ratings
Symbol
Parameter
Conditions
Min
Max
Unit
V
VDD_HV_PMU
3.3 V PMU supply voltage
—
–0.3
4.01, 2
VDD_HV_REG3V8
REG3V8 Supply Voltage
—
–0.3
5.5
V
VDD_HV_IO*
3.3 V Input/Output Supply Voltage, LFAST IO
Supply, RGMII IO Supply and PWM IO Supply
—
–0.3
3.631, 2
V
VSS_HV_IOx
Input/output ground voltage
—
–0.1
0.1
V
V
VDD_HV_FLA
3.3 V flash supply voltage
—
–0.3
3.631, 2
VDD_HV_RAW
AFE RAW supply voltage
—
–0.1
4
V
VDD_HV_DAC
AFE DAC supply voltage
—
–0.1
4
V
Aurora supply voltage
—
–0.3
1.5
V
VDD
1.25 V core supply voltage3, 4, 5
—
–0.3
1.5
V
VSS
ground3, 4, 5
—
–0.3
0.3
V
—
–0.1
0.1
V
VDD_LV_IO*
VSS_LV_OSC
1.25 V core supply
Oscillator amplifier ground
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
11
General
Table 6. Absolute maximum ratings (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
VDD_LV_PLL0
System PLL supply voltage
—
–0.3
1.5
V
VDD_LV_LFASTPLL
LFAST PLL supply voltage
—
–0.3
1.5
V
VDD_HV_ADCREF0/1
ADC_0 and ADC_1 high reference voltage
—
–0.3
5.5
V
VSS_HV_ADCREF0/1
ADC_0 and ADC_1 ground and low reference
voltage
—
–0.1
0.1
V
VDD_HV_ADC
3.3 V ADC supply voltage
—
–0.3
4.0 1, 2
V
VSS_HV_ADC
3.3 V ADC supply ground
—
–0.1
0.1
V
TVDD
VIN_XOSC
VINA
VINA_SD
Supply ramp
rate6
—
0.00005
0.1
V/μs
Voltage on XOSC pins with respect to ground
—
-0.3
1.47
V
Voltage on SAR ADC analog pin with respect to
ground (VSS_HV_ADCREFx)
—
–0.3
6.0
V
Powered up 8
-0.3
VDD_HV_RAW +
0.3
V
Powered down
-0.3
1.47
Relative to
VDD_HV_IOx
–0.3
VDD_HV_IOx + 0.3
V
Voltage on Sigma-Delta ADC analog pin with
respect to ground7
9
VIN
Voltage on any digital pin with respect to
ground (VSS_HV_IOx)
10
VDD_LV_DPHY
MIPICSI2 DPHY voltage supply3, 4, 5
—
–0.3
1.5
V
VSS_LV_DPHY
ground3, 4, 5
—
–0.3
0.3
V
mA
MIPICSI2 DPHY supply
IINJPAD
Injected input current on any pin during
overload condition11
—
–10
1012
IINJSUM
Absolute sum of all injected input currents
during overload condition
—
–50
50
mA
Storage temperature
—
–55
150
°C
TSTG
1. 5.3 V for 10 hours cumulative over lifetime of device; 3.3 V +10% for time remaining.
2. Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
3. 1.45 V to 1.5 V allowed for 60 seconds cumulative time at maximum TJ = 150°C; remaining time as defined in note 5 and
note 6.
4. 1.375 V to 1.45 V allowed for 10 hours cumulative time at maximum TJ = 150°C; remaining time as defined in note 6.
5. 1.32 V to 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at
maximum TJ=150°C.
6. TVDD is relevant for all external supplies.
7. ADC inputs include an overvoltage detect function that detects any voltage higher than 1.2 V with respect to ground on
either ADC input and open circuit (disconnect) the input in order to prevent damage to the ADC internal circuitry. The ADC
input remains disconnected until the inputs return to the normal operating range.
8. SDADC is powered up and overvoltage protection is ON.
9. SDADC is powered up and overvoltage protection is OFF.
10. Only when VDD_HV_IOx < 3.63 V.
11. No input current injection circuitry on AFE pins.
12. The maximum value of 10 mA applies to pulse injection only. DC current injection is limited to a maximum of 5 mA.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
12
NXP Semiconductors
General
4.2 Operating conditions
The following table describes the operating conditions for the device, and for which all
specifications in the datasheet are valid, except where explicitly noted. The device
operating conditions must not be exceeded, or the functionality of the device is not
guaranteed.
Table 7. Device operating conditions
Symbol
VDD_HV_PMU
VDD_HV_REG3V8
VDD
VDD_HV_IO*
VDD_LV_IO_*4
Conditions
Min
Typ
Max1
Unit
3.3V PMU Supply Voltage
—
3.132
3.3
3.6
V
REG3V8 Supply Voltage
—
3.13
3.8
5.5
V
—
1.192
1.25
1.313
V
Main GPIO 3V Supply
Voltage, LFAST IO Supply,
RGMII IO Supply, PWM IO
Supply Voltage
—
3.132
3.3
3.6
V
Aurora Supply Voltage
—
1.19
1.25
1.31
V
1.192
—
1.31
V
Parameter
Core Supply Voltage
VDD_LV_PLL0
System PLL Supply Voltage
—
VDD_LV_LFASTPLL
LFAST PLL Supply Voltage
—
1.19
—
1.31
V
VDD_HV_FLA5
Flash Supply Voltage
—
3.132
3.3
3.6
V
VDD_HV_ADC
SAR ADC Supply Voltage
(HVD supervised)
—
3.132
3.3
3.66
V
VDD_HV_RAW
3.3V AFE RAW Supply
Voltage
—
3.13
3.3
3.6
V
VDD_HV_DAC
3.3V AFE DAC Supply
Voltage
—
3.13
3.3
3.6
V
ADC_0 and ADC_1 high
reference voltage
—
3.13
3.3
3.6
V
Voltage on digital pin with
respect to ground (VSS_HV_IOx)
—
—
—
VDD_HV_IOx
+0.3
V
Differential
—
—
1.2
V
—
—
—
165
V/μs
±0.1%
40.16
40.2
40.25
kΩ
External Trim Resistor
Temperature Coefficient
—
—
—
25
ppm/°C
Voltage on SAR ADC analog
pin with respect to ground
(VSS_HV_ADCREFx)
—
—
—
VDD_HV_ADCRE
V
VDD_HV_ADCREF0/1
VIN
VINSDPP
VINSR
RTRIM_TOL
RTRIM_TEMPCO
VINA9
VDD_LV_DPHY
TA, 11
Sigma-Delta ADC Input
Voltage (peak-peak)7, 8
Sigma-Delta ADC Input Slew
Rate7
External Trim Resistor
tolerance
Fx
MIPICSI2 DPHY voltage
supply10
Ambient temperature at full
performance 12
—
1.19
1.25
1.31
V
–40
—
125
°C
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
13
General
Table 7. Device operating conditions (continued)
Symbol
TJ11
FXTAL
Conditions
Min
Typ
Max1
Unit
Junction temperature
—
–40
—
150
°C
XOSC Crystal Frequency13
—
—
40
—
MHz
Parameter
AFE Bypass Modes Only
Single-Ended External Clock14
EXTALclk
EXTAL external clock
frequency
40
MHz
EXTAL external clock Cycle to
Cycle Jitter (RMS)
—
—
—
2.515
ps
Vinxoscclkvil
EXTAL external clock input
low voltage
—
0
—
0.4
V
Vinxoscclkvih
EXTAL external clock input
high voltage
—
1
—
1.23
V
1
ns
53
%
Vinxoscjit
tr/tf
Rise/fall time of EXTAL
external clock input
tdc
Duty Cycle of EXTAL external
clock input
47
50
Differential LVDS External Clock
LVDSclk
LVDSVinxoscclk
LVDS external clock
frequency
40
LVDS external clock input
voltage
LVDSVinxoscclk(p-p) LVDS external clock input
voltage (peak-peak)
0
Voltage driven,
MHz
1.36
V
0.45
0.70
1.12
V
3.0
3.5
4.0
mA
2.5
ps
1.5
ns
53
%
AC coupled
Differential
LVDSIinxoscclk
LVDSVinxoscjit
tr /tf
tdcLVDS
LVDS external clock input
current
Current driven,
DC coupled.
LVDS external clock Jitter
(RMS) 15
Rise/fall time of LVDS
external clock input
Duty Cycle of LVDS external
clock input
20% - 80%
47
50
1.
2.
3.
4.
5.
6.
Full functionality cannot be guaranteed when voltages are out of the recommended operating conditions.
Min voltage takes into account the LVD variation.
Max voltage takes into account HVD variation.
Aurora supply must connect to core supply voltage at board level.
The ground connection for the VDD_HV_FLA is shared with VSS.
Supply range does not take into account HVD levels. Full range can be achieved after power-up, if HVD is disabled. See
Voltage regulator electrical characteristics section for details.
7. Around common mode voltage of 0.7 V. Input voltage cannot exceed 1.4 V prior to AFE start-up completion (VREF and
VREGs on and LVDs cleared).
8. SDADC input voltage full scale is 1.2 Vpp
9. On channels shared between ADC0 and 1, VDD_HV_ADCREFx is the lower of VDD_HV_ADCREF0/1.
10. VDD_LV_DPHY supply should be shorted to core supply voltage VDD on board. Refer to AN5251. Contact your NXP sales
representative for details.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
14
NXP Semiconductors
General
11. While determining if the operating temperature specifications are met, either the ambient temperature or junction
temperature specification can be used. It is critical that the junction temperature specification is not exceeded under any
condition.
12. Full performance means full frequency.
13. Recommended Crystal 40 MHz (ESR≤30 Ω), 8 pF load capacitance.
14. External mode can be used as differential input with EXTAL and XTAL
15. The number is 3.5 ps when SD-ADC and/or DAC is not used in the device.
4.3 Supply current characteristics
Current consumption data is given in the following table. These specifications are design
targets and are subject to change per device characterization.
Table 8. Current consumption characteristics
Symbol
IDD_CORE
Parameter
Core current in run mode
Conditions
All cores at max frequency. 1.31 V. Tj = 150°C (240
MHz)
Min Typ
-
-
Max
Unit
14801
mA
16421
All cores at max frequency. 1.31 V. Tj = 150°C (266
MHz)
IDD_HV_FLA
Flash operating current
Tj = 150°C. VDD_HV_FLA = 3.6 V
-
32
403
mA
IDD_LV_AURORA
Aurora operating current
Tj = 150°C. VDD_LV_AURORA = 1.31 V. 4 TX lanes
enabled.
-
-
60
mA
IDD_HV_ADC
ADC operating current
Tj = 150°C. VDD_HV_ADC = 3.6 V. 2 ADCs operating
at 80 MHz.
-
2
5
mA
IDD_HV_ADCREF
Reference current per
ADC4
Tj = 150°C. VDD_HV_ADCREFx = 3.6 V. ADC operating
at 80 MHz.
-
-
1.5
mA
-
-
0.75
Reference current per
temp sensor5
1.
2.
3.
4.
5.
6.
IDD_HV_RAW
AFE SD and regulator
operating current
Tj = 150°C. VDD_HV_RAW = 3.6 V. SD-PLL, AFE
regulators and 4 SD enabled.
-
706
75
mA
IDD_HV_DAC
AFE DAC operating
current
Tj = 150°C. VDD_HV_DAC = 3.6 V. DAC enabled.
-
10
15
mA
IDD_HV_PMU
PMU operating current
Tj = 150°C. VDD_HV_PMU = 3.6 V. Internal
regulation enabled.
-
2
10
mA
IDD_LV_DPHY
MIPICSI2 DPHY
operating current in HSRX mode
Tj = 150°C, VDD_LV_DPHY =1.31 V
-
14.9
23.2
mA
Strong dependence on use case, cache usage.
Measured during flash read.
Peak Flash current measured during read while write (RWW) operation.
ADC0 and 1 on ADCREF0/1.
Temp sensor current when PMC_CTL_TD[TSx_AOUT_EN] = 1. TS0 on ADCREF0/1.
Typical number is approximately 10 mA per each SD-ADC enabled, 12 mA for SD-PLL and 15 mA for the AFE regulators.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
15
General
4.4 Voltage regulator electrical characteristics
Table 9. Voltage regulator electrical specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
POR-R
1.25 V VDD core POR release
—
0.97
1.02
1.06
V
POR-E
1.25 V VDD core POR engage
—
0.93
0.98
1.02
V
LVD12R
Low-Voltage Detection 1.25 V release (Core
VDD supply, and PLL0/1 supply LVDs)
Untrimmed
1.122
1.157
1.192
V
Trimmed
1.142
1.157
1.172
V
Low-Voltage Detection 1.25 V engage (Core
VDD supply and PLL0/1 supply LVDs)
Untrimmed
1.102
1.137
1.172
V
Trimmed
1.122
1.137
1.152
V
HVD12R-trim
High-Voltage Detection 1.25 V release
(Core VDD)
Trimmed
1.33
1.35
1.37
V
HVD12E-trim
High-Voltage Detection 1.25 V engage
(Core VDD supply)
Trimmed
1.36
1.38
1.40
V
LVD_MIPI12R-trim
Low-Voltage Detection 1.25V release
(MIPICSI2 DPHY supply)
—
1.130
1.157
1.184
V
LVD_MIPI12E-trim
Low-Voltage Detection 1.25V engage
(MIPICSI2 DPHY supply)
—
1.111
1.137
1.163
V
POR-RVDD_HV_PMU
3.3 V PMU supply voltage POR release
threshold
—
2.54
2.645
2.735
V
POR-EVDD_HV_PMU
3.3 V PMU supply voltage POR engage
threshold
—
2.50
2.60
2.695
V
LVD33R
3.3V Low-Voltage Detection Release
Threshold (PMC, FLASH, IO, ADC)
Untrimmed
2.90
3.02
3.13
V
Trimmed
3.00
3.05
3.10
V
3.3V Low-Voltage Detection Engage
Threshold (PMC, FLASH, IO, ADC)
Untrimmed
2.86
2.98
3.09
V
Trimmed
2.96
3.01
3.06
V
3.3V High-Voltage Detection Release
Threshold (ADC)
Untrimmed
3.45
3.61
3.75
V
Trimmed
3.47
3.53
3.58
V
3.3V High-Voltage Detection Engage
Threshold (ADC)
Untrimmed
3.51
3.65
3.79
V
Trimmed
3.51
3.57
3.62
V
UVL30R
SMPS under-voltage lockout release
threshold
Untrimmed
2.75
2.90
3.05
V
UVL25E
SMPS under-voltage lockout engage
threshold
2.40
2.55
2.7
V
DGLITCHE
Voltage Detector Deglitcher Filter Time Engage
—
2.0
3.5
5
µs
DGLITCHR
Voltage Detector Deglitcher Filter Time Release
—
5
7
12
µs
RSTDGLTC
VREG_POR_B Input Deglitch Filter Time
—
200
320
500
ns
RSTPUP
VREG_POR_B Pin Pull-up Resistance
—
37
75
150
kΩ
REGENPUP
VREG_SEL Pin Pull-up Resistance
—
37
75
150
kΩ
Load Current from 10
mA to 1.8 A
1.19
1.255
1.35
V
LVD12R-trim
LVD12E
LVD12E-trim
LVD33R-trim
LVD33E
LVD33E-trim
HVD33R
HVD33R-trim
HVD33E
HVD33E-trim
VSMPS
Internal switched regulator output voltage
1
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
16
NXP Semiconductors
General
Table 9. Voltage regulator electrical specifications (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FSMPS
Internal switched regulator operating
frequency without modulation
Untrimmed
0.65
1.00
1.35
MHz
Trimmed
0.93
1.00
1.07
MHz
Internal switched regulator frequency
modulation
—
—
7.5
—
%
—
—
15
—
%
—
—
30
—
%
FSMPS-M7.5
FSMPS-M15
FSMPS-M30
VREGSWPUP
Internal switched regulator gate-driver pullup resistance2
—
—
—
—
—
VREF_BG_T
PMC bandgap reference voltage for
SARADC
Trimmed
1.20
1.22
1.237
V
Vih (VREG_POR_B)
VREG_POR_B pin High Voltage level
—
0.7 x
VDD_H
V_PMU
—
VDD_H
V_PMU
+ 0.3
V
Vil (VREG_POR_B)
VREG_POR_B pin Low Voltage level
—
-0.3
—
0.3 x
VDD_H
V_PMU
V
LVDAFER
Low Voltage Detection 3.3V Release (AFE
VDD_HV_DAC and VDD_HV_RAW
supplies)
2.75
2.80
2.90
V
LVDAFEE
Low Voltage Detection 3.3V Engage (AFE
VDD_HV_DAC and VDD_HV_RAW
supplies)
2.68
2.77
2.86
V
1. Min/Max includes transient load conditions. Steady state voltage is within the core supply operating specifications.
2. There is a strong pull up from VREG_SWP to VDD_HV_REG3V8 which is connected when SMPS is disabled. The pullup
has resistance less than 1 Kohm, therefore VREG_SWP should not be connected to ground if unused.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
17
General
Figure 2. SMPS External Components Configuration
Table 10. SMPS External Components
Ref
Description
M1
SI3443, 2SQ2315
L1
2.2 uH 3A < 100 mΩ series resistance (Ex. Bourns SRU8043-2R2Y)
D1
SS8P3L 8A Schottcky Diode
R1
24 kΩ
C1
10 μF Ceramic
C2
100 nF Ceramic
C3
100 nF Ceramic (place close to inductor)
C4
10 uF Ceramic (place close to inductor)
C5
1 nF Ceramic
C6
4 x 100 nF + 4 x 10nF Ceramic (place close to MCU supply pins)
C7
4 x 10 μF Ceramic (place close to MCU supply pins)
C8
100 nF Ceramic
C9
1 μF Ceramic (Unless C1 is really close to the pin)
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
18
NXP Semiconductors
General
Figure 3. Radar AFE External Components Configuration
Table 11. Radar AFE External Components
Component
Component
Value
Tolerance
Placement
Priority of
larger cap. 1
Placement Special notes
Priority of
smaller cap1
C1
0.47 μF
±35%
3
—
—
C2
0.1 μF
±35%
—
1
—
C3
1.0 μF
±35%
7
—
—
C4
1.0 μF
±35%
2
—
—
C5
0.1 μF
±35%
—
4
—
C6
1.0 μF
±35%
8
—
—
C7
0.1 μF
±35%
—
6
—
C8
1.0 μF
±35%
6
—
—
C9
0.1 μF
±35%
—
5
—
C10
1.0 μF
±35%
4
—
—
C11
0.1 μF
±35%
—
2
—
C12
1.0 μF
±35%
5
—
—
C13
0.1 μF
±35%
—
3
—
C14
1.0 μF
±35%
10
—
—
C15
0.1 μF
±35%
—
8
—
C16
1.0 μF
±35%
9
—
—
C17
0.1μF
±35%
—
7
—
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
19
General
Table 11. Radar AFE External Components (continued)
Component
Component
Value
Tolerance
Placement
Priority of
larger cap. 1
Placement Special notes
Priority of
smaller cap1
C18
10 μF
—
1
—
X7R type
C19
220 nF
—
—
—
Sigma Delta ADC input capacitor. See Figure
9
C20
220 nF
—
—
—
Sigma Delta ADC input capacitor. See Figure
9
R1
40.2 kΩ
±0.1%
—
—
tempco = 25ppm/C
R2
300 Ω
—
—
—
DAC Rl See Table 27
R3
300 Ω
—
—
—
DAC Rl See Table 27
Crystal
40MHz
—
—
—
Connected between XOSC_EXTAL/
XOSC_XTAL, ESR ≤ 30Ω
1. All Radar AFE external bypass capacitors should be placed as close as possible to the associated package pin. As shown
in Radar AFE External Components Configuration figure, most pins have two values of bypass capacitor. Greater than 0.1
μF is referred to as the larger cap. 0.1 μF is referred to as the smaller cap.
4.5 Electromagnetic Compatibility (EMC) specifications
EMC measurements to IC-level IEC standards are available from NXP on request.
4.6 Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
NOTE
A device will be defined as a failure if after exposure to ESD
pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing
shall be performed per applicable device specification at room
temperature followed by hot temperature, unless specified
otherwise in the device specification.
Table 12. ESD ratings
No.
Symbol
1
VESD(HBM)
Parameter
Electrostatic discharge
Conditions1
TA = 25 °C
Class
Max value2
Unit
H1C
2000
V
(Human Body Model)
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
20
NXP Semiconductors
I/O Parameters
Table 12. ESD ratings (continued)
No.
Symbol
Conditions1
Parameter
Class
Max value2
Unit
C3A
5003
V
conforming to AECQ100-002
2
VESD(CDM)
Electrostatic discharge
TA = 25 °C
(Charged Device Model)
conforming to AECQ100-011
750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. Data based on characterization results, not tested in production.
3. 500 V for non-AFE pins, 250 V for AFE pins.
5 I/O Parameters
5.1 I/O pad DC electrical characteristics
NMI, TCK, TMS, JCOMP are treated as GPIO.
Table 13. I/O pad DC electrical specifications
Symbol
Parameter
Value
Unit
Min
Max
Vih_hys
CMOS Input Buffer High Voltage (with hysteresis
enabled)
0.65*VDD_HV_IO
VDD_HV_IO + 0.3
V
Vil_hys
CMOS Input Buffer Low Voltage (with hysteresis
enabled)
-0.3
0.35*VDD_HV_IO
V
Vih
CMOS Input Buffer High Voltage (with hysteresis
disabled)
0.55 * VDD_HV_IO VDD_HV_IO + 0.3
V
Vil
CMOS Input Buffer Low Voltage (with hysteresis
disabled)
-0.3
0.40 * VDD_HV_IO
V
0.1 * VDD_HV_IO
—
V
Vhys
CMOS Input Buffer Hysteresis
VihTTL
TTL Input high level voltage (All SAR_ADC input pins)
2
VDD_HV_ADCREFx
+ 0.3
V
VilTTL
TTL Input low level voltage (All SAR_ADC input pins)
-0.3
0.56
V
TTL Input hysteresis voltage (All SAR_ADC input pins)
0.3
—
V
10
55
µA
10
55
µA
VhystTTL
Current1
Pull_Ioh
Weak Pullup
Pull_Iol
Weak Pulldown Current2
Iinact_d
Digital Pad Input Leakage Current (weak pull inactive)
Voh
Vol
Ioh_f
Iol_f
Ioh_h
Iol_h
-2.5
2.5
µA
Output High
Voltage3
0.8 * VDD_HV_IO
—
V
Output Low
Voltage4
—
0.2 * VDD_HV_IO
V
18
70
mA
21
120
mA
9
35
mA
10.5
60
mA
Full drive
Ioh5
Full drive
Iol5
Half drive
Ioh5
Half drive
Iol5
(ipp_sre[1:0] = 11)
(ipp_sre[1:0] = 11)
(ipp_sre[1:0] = 10)
(ipp_sre[1:0] = 10)
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
21
I/O Parameters
1.
2.
3.
4.
5.
Measured when pad = 0 V
Measured when pad = VDD_HV_IO
Measured when pad is sourcing 2 mA
Measured when pad is sinking 2 mA
Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test.
5.1.1 RGMII pad DC electrical characteristics
Table 14. RGMII pad DC electrical specifications
Symbol
1.
2.
3.
4.
5.
6.
Parameter
Value
Unit
Min
Max
Vih
CMOS Input Buffer High Voltage
0.65 x VDD_HV_IO
VDD_HV_IO + 0.3
Vil
CMOS Input Buffer Low Voltage
V
-0.3
0.35 x VDD_HV_IO
V
Pull_Ioh
Weak Pullup Current1
10
55
µA
Pull_Iol
Weak Pulldown Current2
10
55
µA
Iinact_d
Digital Pad Input Leakage Current (weak pull
inactive)
-2.5
2.5
µA
0.8 x VDD_HV_IO
—
V
—
0.2 * VDD_HV_IO
V
8
26
mA
8
24
mA
Voh
Output High Voltage3
Vol
Voltage4
Output Low
Ioh5
Ioh_f
Full drive
Iol_f
Full drive Iol6
Measured when pad = 0 V
Measured when pad = VDD_HV_IO
Measured when pad is sourcing 2 mA
Measured when pad is sinking 2 mA
Ioh_f value is measured with 0.8*VDDE applied to the pad.
Iol_f is measured when 0.2*VDDE is applied to the pad.
5.2 I/O pad AC specifications
AC Parameters are specified over the full operating junction temperature range of -40°C
to +150°C and for the full operating range of the VDD_HV_IO supply defined in Table 7.
Table 15. Functional Pad electrical characteristics
Symbol
Prop. Delay (ns)1
Rise/Fall Edge (ns)2
Drive Load (pF)
L>H/H>L
pad_sr_hv
(output)
Min
Max
Min
Max
2.5/2.5
8.25/7.5
0.7/0.6
3/3
50
6.4/5
19.5/19.5
2.5/2.0
12/12
200
2.2/2.5
8/8
0.4/0.3
3.5/3.5
25
2.9/3.5
12.5/11
1.0/0.8
6.5/6.5
50
11/8
35/31
6.5/3.0
25/21
200
SIUL2_MSCR[SRC
]
MSB,LSB
11
10
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
22
NXP Semiconductors
I/O Parameters
Table 15. Functional Pad electrical characteristics (continued)
Prop. Delay (ns)1
Symbol
Rise/Fall Edge (ns)2
Drive Load (pF)
SIUL2_MSCR[SRC
]
L>H/H>L
pad_sr_hv
Min
Max
Min
Max
8.3/9.6
45/45
4/3.5
25/25
50
13.5/15
65/65
6.3/6.2
30/30
200
13/13
75/75
6.8/6
40/40
50
21/22
100/100
11/11
51/51
200
0.5/0.5
0.5
2/2
MSB,LSB
013
003
NA
(input)4
1.
2.
3.
4.
As measured from 50% of core side input to Voh/Vol of the output
Measured from 20% - 80% of output voltage swing
Slew rate control modes
Input slope = 2ns
NOTE
Data based on characterization results, not tested in production.
Table 16. Functional Pad AC Specifications
Symbol
Parameter
pad_sr_hv(Cp)
Value
Parasitic Input Pin Capacitance
Unit
Min
Typ
Max
4.5
4.7
5.0
pF
5.3 Aurora LVDS driver electrical characteristics
NOTE
The Aurora interface is AC coupled, so there is no commonmode voltage specification.
Table 17. Aurora LVDS driver electrical characteristics
Parameter1
Symbol
FTXRX
Value
Data rate
Unit
Min
Typ
Max
—
—
1.15
Gbps
+/- 600
+/- 800
mV
Transmitter Specifications
Vdiffout
Differential output voltage swing (terminated)
+/- 400
Trise/Tfall
Rise/Fall time (10% - 90% of swing)
60
Vdiffin
Differential voltage
ps
Receiver Specifications
+/- 100
+/- 800
mV
Termination
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
23
I/O Parameters
Table 17. Aurora LVDS driver electrical characteristics (continued)
Parameter1
Symbol
Value
Unit
Min
Typ
Max
99
100
101
Ohms
RV_L
Terminating Resistance (external)
CP
Parasitic Capacitance (pad + bondwire + pin)
1
pF
LP
Parasitic Inductance
7
nH
STARTUP
TSTRT_BIAS
Bias startup time
TSTRT_TX
Transmitter startup
TSTRT_RX
—
—
5
µs
—
—
5
µs
time2
—
—
5
µs
Receiver o/p duty cycle
30
70
%
Receiver startup
LVDS_RXOUT3
time2
1. Conditions for these values are VDD_LV_IO_AURORA = 1.19V to 1.32V, TJ = –40 / 150 °C
2. Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.
3. Receiver o/p duty cycle is measured with 1.25 Gbps, 50% duty cycle, max 1 ns rise/fall time, 100 mV voltage swing signal
applied at the receiver input.
5.4 Reset pad electrical characteristics
The device implements a dedicated bidirectional RESET_B pin.
VDD_HV_IOx
VDDMIN
RESET_B
VIH
VIL
device reset forced by RESET_B
device start-up phase
Figure 4. Start-up reset requirements
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
24
NXP Semiconductors
I/O Parameters
VRESET_B
hw_rst
VDD_HV_IO
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
filtered by
lowpass filter
WFRST
unknown reset
state
device under hardware reset
WFRST
WNFRST
Figure 5. Noise filtering on reset signal
Table 18. RESET_B electrical characteristics
Symbol
Conditions1
Parameter
Value
Min
Typ
Max
Unit
VIH
Input high level TTL (Schmitt Trigger)
—
2.0
—
VDD_HV_IOx +
0.4
V
VIL
Input low level TTL (Schmitt Trigger)
—
–0.4
—
0.56
V
VHYS2
Input hysteresis TTL (Schmitt Trigger)
—
300
—
—
mV
IOL_R
Strong pull-down current
Device under power-on reset
0.2
—
—
mA
15
—
—
VDD_HV_IO = 1.2 V
VOL = 0.35 x VDD_HV_IO
Device under power-on reset
mA
VDD_HV_IO=3.0 V
VOL = 0.35 x VDD_HV_IO
WFRST
RESET_B input filtered pulse
—
—
—
500
ns
WNFRST
RESET_B input not filtered pulse
—
2400
—
—
ns
30
—
100
µA
|IWPD|
Weak pull-down current absolute value VIN = VDD_HV_IOx
1. VDD_HV_IOx = 3.3 V -5%,+10%, TJ = –40 / 150°C, unless otherwise specified.
2. Data based on characterization results, not tested in production.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
25
Peripheral operating requirements and behaviours
6 Peripheral operating requirements and behaviours
6.1 Clocks and PLL Specifications
6.1.1 40 MHz Oscillator (XOSC) electrical characteristics
The device provides an oscillator/resonator driver.
NOTE
XTAL/EXTAL must not be directly used to drive external
circuits.
Table 19. XOSC electrical characteristics
Symbol
Parameter
XOSCfout
Oscillator frequency
tstab
Oscillator start-up time
2
ms
Cycle to cycle jitter (peak –
peak)
2.51
ps
55
%
tjitcc
Conditions
Cin
Input Capacitance
Typ
Max
40
Output Duty Cycle
2
Min
45
50
Unit
MHz
Extal and Xtal each
3.0
4.0
5.0
pF
RinLVDS
LVDS bypass mode input
termination3
Between Extal and Xtal
75
100
125
ohm
VCMLVDS
LVDS Common Mode
Voltage
Vdda/2
0.60
0.70
0.80
V
1. The number is 3.5 ps when SD-ADC and/or DAC is not used in the device.
2. When using a 40 MHz crystal, the recommended load capacitance is 8 pF. Need quiet ground connection on the board
and external crystal/load capacitor placement as close to the Extal and Xtal pins as possible to allow good jitter
performance.
3. The termination resistance is only active when the AFE is powered (VDD_HV_RAW, VDD_HV_DAC and the AFE
regulators are powered up) and the XOSC is powered down (default case once device is out of reset) or the XOSC is
configured in differential bypass mode.
6.1.2 FMPLL electrical characteristics
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
26
NXP Semiconductors
Clocks and PLL Specifications
IRCOSC
PLL_0_PHI0
PLL_0
PLL_0_PHI1
XOSC
PLL_1_PHI0
PLL_1
Figure 6. PLL integration
Table 20. PLL0 electrical characteristics
Symbol
fPLL0IN
PLL0IN
Parameter
PLL0 input
clock2, 3
PLL0 input clock duty
cycle2
Conditions1
Min
Typ
Max
Unit
—
14
—
44
MHz
—
40
—
60
%
fPLL0VCO
PLL0 VCO frequency
—
600
—
1250
MHz
fPLL0PHI0
PLL0 output clock PHI0
—
4.76
—
6254
MHz
fPLL0PHI1
PLL0 output clock PHI1
—
20
—
156
MHz
tPLL0LOCK
PLL0 lock time
—
—
—
100
µs
PLL0LTJ
PLL0 long term jitter fPLL0IN = 8 MHz
(resonator)5
fPLL0PHI0 = 40 MHz, 1 μs
±1
ns
fPLL0PHI0 = 40 MHz, 13 μs
±1
ns
5
mA
IPLL0
PLL0 consumption
—
—
1. VDD_LV_PLL0 =1.25 V ± 5%, TJ = -40 / 150 °C unless otherwise specified.
2. PLL0IN clock retrieved directly from either IRCOSC or external XOSC clock.
3. fPLL0IN frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure the reference clock to the PLL analog
loop is in the range 8 MHz-20 MHz
4. The maximum clock outputs are limited by the design clock frequency requirements as per recommended operating
conditions.
5. VDD_LV_PLL0 noise due to application in the range VDD_LV_PLL0 = 1.25 V±5%, with frequency below PLL bandwidth (40 KHz)
will be filtered.
Table 21. FMPLL1 electrical characteristics
Symbol
Parameter
Conditions1
Min
Typ
Max
Unit
fPLL1IN
PLL1 input clock2
—
38
—
78
MHz
PLL1IN
PLL1 input clock duty cycle2
—
35
—
65
%
fPLL1VCO
PLL1 VCO frequency
—
600
—
1250
MHz
fPLL1PHI0
PLL1 output clock PHI0
—
4.76
—
625
MHz
tPLL1LOCK
PLL1 lock time
—
—
—
100
µs
fPLL1MOD
PLL1 modulation frequency
—
—
—
250
kHz
|δPLL1MOD|
PLL1 modulation depth (when
enabled)
Center spread
0.25
—
2
%
Down spread
0.5
—
4
%
IPLL1
PLL1 consumption
—
—
6
mA
1. VDD_LV_PLL0 = 1.25 V ± 5%, TJ = -40 / 150°C unless otherwise specified.
2. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
27
Clocks and PLL Specifications
6.1.3 16 MHz Internal RC Oscillator (IRCOSC) electrical specifications
Table 22. Internal RC Oscillator electrical specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FTarget
IRC target frequency
—
—
16
—
MHz
Funtrimmed
IRC frequency (untrimmed)
—
9.6
—
24
MHz
—
-8
—
8
%
—
—
5
µs
δFvar
IRC trimmed frequency variation
Tstartup
1
Startup time
1. The typical user trim step size (δfTRIM) is 0.3% of current frequency for application of positive trim and 0.26% of current
frequency for application of negative trim, based on characterization results.
6.1.4 320 MHz AFE PLL electrical characteristics
Table 23. 320 MHz AFE PLL parameters
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PLLfout
Output Frequency
—
—
320
—
MHz
PLLfin
Input Frequency
—
—
—
40
MHz
LW64 = 1
—
—
150
µs
tcal
Calibration Time
1
LW64 = 0
500
tlock
Lock Time
after calibration
—
—
75
µs
tjitcck
Cycle to cycle jitter (peak – peak)
—
—
—
10
ps
—
Output duty cycle
—
48
50
52
%
1. The LW64 bit sets the wait time before the PLL frequency is measured after each calibration step to allow for stabilization.
If LW64 is '0', wait time of 256 reference clock cycles is used. If LW64 is'1', wait time of 64 reference clock cycles is used.
6.1.5 LFAST PLL electrical characteristics
The specifications in the following table apply to the interprocessor bus LFAST interface.
Table 24. LFAST PLL electrical characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fRF_REF
PLL reference clock frequency
—
10
—
26
MHz
ERRREF
PLL reference clock frequency error
—
–1
—
1
%
PLL reference clock duty cycle
—
45
—
55
%
—
—
6401
—
MHz
—
—
—
40
μs
—
—
300
ps
DCREF
fVCO
tLOCK
ΔPERREF
PLL VCO frequency
PLL phase
lock2
Input reference clock jitter (peak to peak) Single period, fRF_REF =
10 MHz
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
28
NXP Semiconductors
Analog modules
Table 24. LFAST PLL electrical characteristics
(continued)
Symbol
Parameter
Condition
Min
Typ
Max
–500
—
500
Random Jitter (Rj)
—
84
101
ps
Deterministic Jitter (Dj)
—
80
96
ps
Total Jitter @BER 10-9
—
1.09
1.31
bits
per
second
Normal Mode
—
6
10
mA
Peak
—
7
11
mA
Power Down
—
0.5
27
μA
Long term, fRF_REF = 10
MHz
ΔPEREYE
IVDD_LV_LFASTPLL
Output Eye Jitter (peak to peak)3
VDD_LV_LFASTPLL Supply Current
Unit
1. The 640 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO
frequency is 624 MHz.
2. The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral
bridge clock that is connected to the PLL on the device.
3. Measured at the transmitter output across a 100 Ω termination resistor on a device evaluation board.
7 Analog modules
7.1 ADC electrical characteristics
The device provides a 12-bit Successive Approximation Register (SAR) Analog-toDigital Converter.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
29
Analog modules
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
( 2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
code out
7
( 1)
6
5
(5)
4
(4)
3
(3)
2
1
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
1 LSB (ideal)
0
1
2
3
Offset Error OSE
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Figure 7. ADC characteristics and error definitions
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
30
NXP Semiconductors
Analog modules
7.1.1 Input equivalent circuit
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
RF
Current Limiter
RL
CF
VA
Channel
Selection
Sampling
RSW1
RAD
CP1
CS
CP2
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL
Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 8. Input equivalent circuit
Table 25. ADC conversion characteristics
Symbol
fCK
fs
Conditions1
Parameter
Min
Typ
Max
Unit
ADC Clock frequency (depends on
ADC configuration) (The duty cycle
depends on AD_CK2 frequency.)
—
20
80
80
MHz
Sampling frequency
—
—
—
1.00
MHz
275
—
—
ns
tsample
Sample
time3
80 MHz@ 200 ohm source
impedance
tsampleC
SAR selftest C-algorithm sample time —
300
—
—
ns
TsampleS
SAR selftest S-algorithm sample time —
1
—
—
µs
TsampleBG
Bandgap sample time
—
1.87
—
—
µs
TsampleTS
Temperature sensor sample time
—
3.18
—
—
µs
80 MHz
650
—
—
ns
tconv
Conversion
time4
,5
CS
ADC input sampling capacitance
—
—
3
5
pF
5
ADC input pin capacitance 1
—
—
—
5
pF
5
ADC input pin capacitance 2
—
—
—
0.8
pF
RSW1
Internal resistance of analog source
VREF range = 3.0 to 3.6 V
—
—
875
Ω
RAD5
Internal resistance of analog source
—
—
—
825
Ω
Integral non-linearity
—
–2
—
2
LSB
—
–1
—
1
LSB
CP1
CP2
5
INL
non-linearity6
DNL
Differential
OFS
Offset error
—
–4
—
4
LSB
GNE
Gain error
—
–4
—
4
LSB
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
31
Analog modules
Table 25. ADC conversion characteristics (continued)
Symbol
TUEIS1WINJ
Conditions1
Parameter
Total unadjusted error for IS1WINJ
TUEIS1WWINJ Total unadjusted error for IS1WWINJ
Min
Typ
Max
Unit
–6
—
6
LSB
–6
—
6
LSB
—
250
nA
–3
—
38
mA
IS1WINJ (pad (single ADC channel)
going to one Max leakage
ADC)
Max positive/negative injection
150 °C
IS1WWINJ (double ADC channel)
(pad going to Max leakage
two ADCs)
Max positive/negative injection 7
150 °C
—
—
300
nA
|Vref_ad0 - Vref_ad1| < 150 mV
–3.6
—
3.6
mA
—
SNR
Signal-to-noise ratio
3.3 V reference voltage
67
—
—
dB
THD
Total harmonic distortion
@ 50 KHz
65
—
—
dB
SINAD
Signal-to-noise and distortion
Fin < 50 KHz
6.02 x ENOB + 1.76
dB
ENOB
Effective number of bits
Fin < 50 KHz
10.5
bits
—
—
1. VDD_HV_ADC = 3.3 V -5%,+10%, TJ = –40 to +150°C, unless otherwise specified and analog input voltage from VAGND to
VDD_HV_ADCREFx.
2. AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
3. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the
sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tsample depend on programming.
4. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to
load the result register with the conversion result.
5. SeeInput equivalent circuit figure.
6. No missing codes.
7. ADC specifications are met only if injection is within these specified limits
8. Max injection current for all ADC IOs is ± 10 mA
NOTE
The ADC performance specifications are not guaranteed if two
ADCs simultaneously sample the same shared channel. Aurora
interface along with SAR-ADC would degrade SAR-ADC
performance. General Purpose Input (GPI) functionality should
not be used on any of the SAR-ADC channels when SARADC
is functional.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
32
NXP Semiconductors
Analog modules
7.2 Sigma Delta ADC electrical characteristics
Figure 9. ADC input equivalent circuit
Table 26. Sigma Delta ADC Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
SPSSDA
Sample Rate
After Decimation Filtering
—
10
10
MS/S
Latency
@ 10 MS/s, full step input to 50% output.
Decimation filter delay not included
—
—
0.1
µs
Recovery Time
After overload condition
—
—
0.5
µs
63
67
—
dBFS
LSDA
RTSDA
SNRSDA_MM_ON, 1
Signal-to-Noise Ratio Input Frequency Range and integration
Mismatch Shaper on bandwidth are from 20 KHz to 5 MHz (using
full-bandwidth decimation filter coefficients).
Production test frequencies 449 KHz and 4
MHz. Production test amplitude is -6 dBFS =
0.6 Vpp.
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
33
Analog modules
Table 26. Sigma Delta ADC Parameters (continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
62
64
—
dBFS
Characterized under the following conditions:
• 0.6 Vpp (i.e. -6 dBFS) input signals
applied at the following frequencies one
at a time: 20.77 KHz, 317.7 KHz, 857.7
KHz, 1.411 MHz, 2.95 MHz, 3.897
MHz, and 4.997 MHz and the SNR in
dBFS is then calculated.
• SNR at 5 MHz will be reduced by 5 dB
due to decimation filter roll off.
• The SNR is specified to be 67 dBFS
typical for input frequencies between 20
KHz and 4 MHz. Mismatch shaper on.
SNDRSDA_MM_ON1
Signal-to-Noise-and- Input Frequency Range and integration
Distortion Ratio
bandwidth are from 20 KHz to 5 MHz. (using
Mismatch Shaper on full-bandwidth decimation filter coefficients).
Production test frequencies 449 KHz and 4
MHz. Production test amplitude is -6 dBFS =
0.6 Vpp.
Characterized under the following conditions:
• 0.6 Vpp (i.e. -6 dBFS) input signals
applied at the following frequencies one
at a time: 20.77 KHz, 317.7 KHz, 857.7
KHz, 1.411 MHz, 2.95 MHz, 3.897
MHz, and 4.997 MHz and the SNDR in
dBFS is then calculated.
• SNR at 5 MHz will be reduced by 5 dB
due to decimation filter roll off.
• The SNR is specified to be 64 dBFS
typical for input frequencies between 20
KHz and 4 MHz. Mismatch shaper on.
IFDRSDA
IMDSDA_MM_ON
Interference Free
Dynamic Range
20 ms integration, ADC inputs tied together at
the package pin. One side of the AC coupling
capacitors associated with each input should
remain connected to the ADC input and the
other side of the capacitor should connected
to ground.
90
—
—
dBFS
Intermodulation
Distortion Mismatch
Shaper on
Input Frequency Range and integration
bandwidth are from 20 KHz to 5 MHz (using
full-bandwidth decimation filter coefficients).
62
—
—
dBc
Characterized under the following conditions:
• Two distinct sets of signal pairs at the
specified frequencies and at an
amplitude of -8 dBFs (i.e. 0.23886
Vpeak = 0.47772 Vpp differential) are
applied one signal pair at a time.
• Signal pair #1 is f1 = 1 MHz and f2 =
1.1 MHz and signal pair #2 is f1 =
390.625 KHz and f2 = 546.875 KHz.
• All inter modulation products are
checked. Mismatch Shaper on.
GM
Gain Mismatching
(ADCx to ADCy)
-3.5
—
3.5
%
OE
Input Offset Error
—
-25
—
25
mV
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
34
NXP Semiconductors
Analog modules
Table 26. Sigma Delta ADC Parameters (continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
OEV
Offset Variation
t = 50 ms, T = constant, data averaged in 1
ms increments
-0.07
—
0.07
mV
Vcm
Common Mode
Voltage2
SDADC switched on
—
vdda/2 –
30 mV
—
V
xtalk
Crosstalk (from any
ADC to the other
ADCs)
Processing a full scale signal.
—
—
-40
dB
Zin
Input Impedance
Maximum input impedance occurs for input
signals at 20 KHz and minimum input
impedance occurs at input frequencies
greater than 1 MHz3
7.3
—
33.5
kΩ
Rcm
Resistance from
each SDADC input to
Vcm (see Figure 9)
27.3
32.2
37.0
kΩ
R_SDADC
Resistance from
each SDADC input
pin to differential
amplifier input (see
Figure 9)
-
9.0
10.75
12.5
kΩ
C_SDADC
SDADC integrator
capacitors (see
Figure 9)
-
0.636
0.684
0.732
pF
Cin parasitic
parasitic input
capacitance from
ADC input to ground
2.0
3.9
4.9
pF
—
1
ns
DT
Analog Delay
Variation
(ADCx to ADCy)
AA
Alias Suppression
ADC input frequency between 315 and 325
MHz
50
—
—
dB
STFoob
ADC out of band
Signal Transfer
Function peaking
Out of band Signal Transfer function peaking
from 20 MHz to 40 MHz
0
2
3
dB
PR
passband ripple
From 20 KHz to 4 MHz (default decimation
filter coefficients must be used)
-0.5
0.0
0.5
dB
Out Of Band
Attenuation
Default decimation filter coefficients must be
used
—
—
dB
OOBA4
5 MHz
6 MHz
7 MHz
10 MHz
-4.5
-10
-20
-40
-60
15 MHz
1. Derate specification by 2 dBFS for Tj less than 0°C.
2. vdda is an internally regulated and trimmed 1.45V ± 10mV voltage.
3. The input structure of the ADC is an active RC integrator which has a frequency dependent input impedance as indicated
in ADC input equivalent circuit.
4. All attenuation values are relative to 0 dB in the ADC passband.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
35
Analog modules
7.3 DAC electrical specifications
NOTE
• All data is measured in single ended mode. Differential
mode is guaranteed by design.
• Specifications guaranteed only if factory trims are not
overridden.
Table 27. DAC parameters
Symbol
NBIT
Parameter
Bits
Condition
Base bits
Min
Typ
Max
Unit
—
12
—
Bits
PWM bits
4
(extra
lsb's)
SPSDAC
Sample rate
—
—
10
—
MSam
ples/s
DNL
Linearity1
—
-24
—
4
LSB
Single-Ended, Rl = 300 Ω
1.2
—
1.35
V
4.0
—
4.5
mA
—
20
30
65
170
nV/
sqrt(Hz
)
mV
Voltage1, 2, 3
Vout
Output
Iout
Full-Scale Output Current
DAC full-scale adjust bits set to
01 or 10
NDAC
DAC output noise 1, 4
@250 kHz
@100 kHz
@10 kHz
@1 kHz
SOE
Static Offset Error1, 2
Single-Ended
60
75
100
Differential with the full-scale
adjust bits set to either 01 or 10
-30
0
30
TOE
Transient Offset Error1, 2, 5
After low-pass filter and
averaging
—
—
0.05
LSB
tDV
Transient Time Delay Variation 1, 2, 6
LSB step
—
—
1
ns
MSB step
10
Oc
Output compliance
single-ended, only the DNL
specification is guaranteed. The
TOE and Tdv may be degraded.
0
—
1.35
V
tempco
Temperature coefficient
—
–1
—
1.0
LSB/K
PSRR
Power Supply Rejection Ratio7
Freq < 250 KHz
30
—
—
dB
2
1. DAC linearity, output swing, noise, TOE, and Tdv specifications are all based upon a 300 Ω DAC output load resistor and
assume that the full-scale adjust bits are set to either 01 or 10. These specifications will NOT be met for other DAC output
load resistor values.
2. Once all of the LVDs have cleared and the DAC is powered on, a one-time wait time of 300 ms is required before the DAC
output signal is valid.
3. The full-scale DAC output is trimmed to 1.30 V ±10 mV with all DAC inputs set to 1 including both full-scale adjust bits.
4. Rl = 300 Ω, 10uF capacitor between Vdd_HV_DAC and DAC_C, ideal supply
5. Difference between ideal and real (Va+Vb/2), for all base and PWM LSBs
6. Falling edge to falling edge or rising edge to rising edge. Any transition DACn -> DACn + 1
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
36
NXP Semiconductors
Memory modules
7. DAC PSRR is 30 dB minimum for DAC output levels of 1/3 of full-scale or less. DAC PSRR is 24 dB minimum with the
DAC output at full-scale.
8 Memory modules
8.1 Flash memory program and erase specifications
NOTE
All timing, voltage, and current numbers specified in this
section are defined for a single embedded flash memory within
an SoC, and represent average currents for given supplies and
operations.
Table 28 shows the estimated Program/Erase times.
Table 28. Flash memory program and erase specifications
Characteristic1
Symbol
Typ2
Factory
Programming3, 4
Field Update
Initial
Max
Initial
Max, Full
Temp
Typical
End of
Life5
20°C ≤TA
≤30°C
-40°C ≤TJ
≤150°C
-40°C ≤TJ
≤150°C
Unit
Lifetime Max6
≤ 1,000
cycles
≤ 250,000
cycles
tdwpgm
Doubleword (64 bits) program time 43
100
150
55
500
μs
tppgm
Page (256 bits) program time
73
200
300
108
500
μs
tqppgm
Quad-page (1024 bits) program
time
268
800
1,200
396
2,000
μs
t16kers
16 KB Block erase time
168
290
320
250
1,000
ms
t16kpgm
16 KB Block program time
34
45
50
40
1,000
ms
t32kers
32 KB Block erase time
217
360
390
310
1,200
ms
t32kpgm
32 KB Block program time
69
100
110
90
1,200
ms
t64kers
64 KB Block erase time
315
490
590
420
1,600
ms
t64kpgm
64 KB Block program time
138
180
210
170
1,600
ms
t256kers
256 KB Block erase time
884
1,520
2,030
1,080
4,000
—
ms
t256kpgm
256 KB Block program time
552
720
880
650
4,000
—
ms
1. Program times are actual hardware programming times and do not include software overhead. Block program times
assume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
3. Conditions: ≤ 150 cycles, nominal voltage.
4. Plant Programing times provide guidance for timeout limits used in the factory.
5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
6. Conditions: -40°C ≤ TJ ≤ 150°C, full spec voltage.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
37
Memory modules
8.2 Flash memory Array Integrity and Margin Read specifications
Table 29. Flash memory Array Integrity and Margin Read specifications
Symbol
Characteristic
Min
Typical
Max1
Units
tai16kseq
Array Integrity time for sequential sequence on 16 KB block.
—
—
512 x
Tperiod x
Nread
—
tai32kseq
Array Integrity time for sequential sequence on 32 KB block.
—
—
1024 x
Tperiod x
Nread
—
tai64kseq
Array Integrity time for sequential sequence on 64 KB block.
—
—
2048 x
Tperiod x
Nread
—
tai256kseq
Array Integrity time for sequential sequence on 256 KB block.
—
—
8192 x
Tperiod x
Nread
—
tmr16kseq
Margin Read time for sequential sequence on 16 KB block.
73.81
—
110.7
μs
tmr32kseq
Margin Read time for sequential sequence on 32 KB block.
128.43
—
192.6
μs
tmr64kseq
Margin Read time for sequential sequence on 64 KB block.
237.65
—
356.5
μs
tmr256kseq
Margin Read time for sequential sequence on 256 KB block.
893.01
—
1,339.5
μs
2
1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires
6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the
address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
8.3 Flash memory module life specifications
Table 30. Flash memory module life specifications
Symbol
Array P/E
cycles
Data
retention
Characteristic
Conditions
Min
Typical
Units
Number of program/erase cycles per block
for 16 KB, 32 KB and 64 KB blocks.1
—
250,000
—
P/E
cycles
Number of program/erase cycles per block
for 256 KB blocks.2
—
1,000
250,000
P/E
cycles
Minimum data retention.
Blocks with 0 - 1,000 P/E
cycles.
50
—
Years
Blocks with 100,000 P/E
cycles.
20
—
Years
Blocks with 250,000 P/E
cycles.
10
—
Years
1. Program and erase supported across standard temperature specs.
2. Program and erase supported across standard temperature specs.
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
38
NXP Semiconductors
Memory modules
8.4 Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by the
following figure. The spec window represents qualified limits. The extrapolated dotted
line demonstrates technology capability, however is beyond the qualification limits.
8.5 Flash memory AC timing specifications
Table 31. Flash memory AC timing specifications
Symbol
tpsus
tesus
Characteristic
Min
Typical
Max
Units
Time from setting the MCR-PSUS bit until MCR-DONE bit is set
to a 1.
—
9.4
11.5
μs
plus four
system
clock
periods
plus four
system
clock
periods
Time from setting the MCR-ESUS bit until MCR-DONE bit is set
to a 1.
—
16
20.8
plus four
system
clock
periods
plus four
system
clock
periods
μs
Table continues on the next page...
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
39
Memory modules
Table 31. Flash memory AC timing specifications (continued)
Symbol
Characteristic
Min
Typical
Max
Units
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low.
—
—
100
ns
tdone
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared.
—
—
5
ns
tdones
Time from 1 to 0 transition on the MCR-EHV bit aborting a
program/erase until the MCR-DONE bit is set to a 1.
—
16
20.8
μs
plus four
system
clock
periods
plus four
system
clock
periods
Time to recover once exiting low power mode.
16
—
45
tres
tdrcv
plus seven
system
clock
periods.
μs
plus seven
system
clock
periods
taistart
Time from 0 to 1 transition of UT0-AIE initiating a Margin Read
or Array Integrity until the UT0-AID bit is cleared. This time also
applies to the resuming from a suspend or breakpoint by
clearing AISUS or clearing NAIBP
—
—
5
ns
taistop
Time from 1 to 0 transition of UT0-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also applies
to the UT0-AISUS to UT0-AID setting in the event of a Array
Integrity suspend request.
—
—
80
ns
Time from 1 to 0 transition of UT0-AIE initiating a Margin Read
abort until the UT0-AID bit is set. This time also applies to the
UT0-AISUS to UT0-AID setting in the event of a Margin Read
suspend request.
10.36
tmrstop
plus fifteen
system
clock
periods
—
plus four
system
clock
periods
20.42
μs
plus four
system
clock
periods
8.6 Flash memory read wait-state and address-pipeline control
settings
The following table describes the recommended settings of the Flash Memory
Controller's PFCR1,2,3[RWSC] and PCRC1,2,3[APC] fields at various operating
frequencies, based on specified intrinsic flash memory access timed of the Flash memory.
Table 32. Flash read wait state and address pipeline control guidelines
Operating Frequency (fsys = SYS_CLK)
RWSC
APC
Flash read latency on
min-cache miss (# of
fcpu clock periods)
Flash read latency
on mini-cache hit (#
of fcpu clock
periods)
0 MHz < fsys
工商网监
湘ICP备2023018690号
