HEF4021B

HEF4021B 8-bit static shift register Rev. 04 — 10 November 2008 Product data sheet 1. General description The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over both the industrial (−40 °C to +85 °C) and automotive (−40 °C to +125 °C) temperature ranges. 2. Features I I I I I I I Tolerant of slower rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the automotive temperature range −40 °C to +125 °C Complies with JEDEC standard JESD 13-B ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 3. Applications I Industrial and automotive NXP Semiconductors HEF4021B 8-bit static shift register 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +125 °C. Type number HEF4021BP HEF4021BT Package Name DIP16 SO16 Description plastic dual in-line package; 16-leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm SOT38-4 SOT109-1 Version HEF4021B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 2 of 14 NXP Semiconductors HEF4021B 8-bit static shift register 5. Functional diagram 7 D0 9 PL 6 D1 5 D2 4 D3 13 D4 14 D5 15 D6 1 D7 11 DS 10 CP SD/CD D CP SHIFT REGISTER 8-BITS Q5 Q6 Q7 2 12 3 001aae608 Fig 1. Functional diagram D0 D5 D6 D7 SD DS D CP FF 1 CD O D SD O D SD O D SD O CP FF 6 CD CP FF 7 CD CP FF 8 CD PL CP Q5 Q6 Q7 001aae610 Fig 2. Logic diagram HEF4021B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 3 of 14 NXP Semiconductors HEF4021B 8-bit static shift register 6. Pinning information 6.1 Pinning HEF4021B D7 Q5 Q7 D3 D2 D1 D0 VSS 1 2 3 4 5 6 7 8 001aae609 16 VDD 15 D6 14 D5 13 D4 12 Q6 11 DS 10 CP 9 PL Fig 3. Pin configuration 6.2 Pin description Table 2. Symbol Q5 to Q7 D0 to D7 VSS PL CP DS VDD Pin description Pin 2, 12, 3 7, 6, 5, 4, 13, 14,15, 1 8 9 10 11 16 Description buffered parallel output from the last three stages parallel data input ground supply voltage parallel load input clock input (LOW-to-HIGH edge-triggered) serial data input supply voltage 7. Functional description Table 3. Function table[1] Outputs DS data 1 data 2 data 3 X X PL L L L L L Q5 X X X data 1 data 2 Q6 X X X X data 1 Q7 X X X X X Number of clock Inputs transitions CP Serial operation 1 2 3 6 7 ↑ ↑ ↑ ↑ ↑ HEF4021B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 4 of 14 NXP Semiconductors HEF4021B 8-bit static shift register Table 3. Function table[1] …continued Outputs DS X X X PL L L H Q5 data 3 no change D5 Q6 data 2 no change D6 Q7 data 1 no change D7 Number of clock Inputs transitions CP 8 Parallel operation X [1] ↑ ↓ H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW to HIGH clock transition; ↓ = HIGH to LOW clock transition; data n = data (HIGH or LOW) on the DS input at the nth ↑ CP transition. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IIK VI IOK II/O IDD Tstg Tamb Ptot Parameter supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation Tamb −40 °C to +125 °C DIP16 package SO16 package P [1] [2] [1] [2] Conditions VI < 0.5 V or VI > VDD + 0.5 V VO < 0.5 V or VO > VDD + 0.5 V Min −0.5 −0.5 −65 −40 - Max +18 ±10 VDD + 0.5 ±10 ±10 50 +150 +125 750 500 100 Unit V mA V mA mA mA °C °C mW mW mW power dissipation per output For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. 9. Recommended operating conditions Table 5. Symbol VDD VI Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 −40 Typ Max 15 VDD +125 3.75 0.5 0.08 Unit V V °C ns/V ns/V ns/V HEF4021B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 5 of 14 NXP Semiconductors HEF4021B 8-bit static shift register 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 µA VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 µA 5V 10 V 15 V VOH HIGH-level output voltage LOW-level output voltage |IO| < 1 µA 5V 10 V 15 V |IO| < 1 µA 5V 10 V 15 V 5V 5V 10 V 15 V 5V 10 V 15 V 15 V 5V 10 V 15 V CI input capacitance Tamb = −40 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.7 −0.64 −1.6 −4.2 0.64 1.6 4.2 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.1 5 10 20 Tamb = 25 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.4 −0.5 −1.3 −3.4 0.5 1.3 3.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.1 5 10 20 7.5 Tamb = 85 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±1.0 150 300 600 Tamb = 125 °C Unit Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±1.0 150 300 600 V V V V V V V V V V V V mA mA mA mA mA mA mA µA µA µA µA pF VOL IOH HIGH-level VO = 2.5 V output current V = 4.6 V O VO = 9.5 V VO = 13.5 V IOL LOW-level VO = 0.4 V output current V = 0.5 V O VO = 1.5 V input leakage VDD = 15 V current supply current IO = 0 A II IDD 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol tPHL Parameter HIGH to LOW propagation delay Conditions CP to Qn see Figure 4 VDD 5V 10 V 15 V PL to Qn see Figure 4 5V 10 V 15 V HEF4021B_4 Extrapolation formula [1] Min - Typ 125 55 40 120 55 40 Max 250 110 80 240 110 80 Unit ns ns ns ns ns ns 98 ns + (0.55 ns/pF) CL 44 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 93 ns + (0.55 ns/pF) CL 44 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 6 of 14 NXP Semiconductors HEF4021B 8-bit static shift register Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol tPLH Parameter LOW to HIGH propagation delay Conditions CP to Qn see Figure 4 VDD 5V 10 V 15 V PL to Qn see Figure 4 5V 10 V 15 V tt transition time Qn; see Figure 4 5V 10 V 15 V tsu set-up time DS to CP; see Figure 5 5V 10 V 15 V Dn to PL; see Figure 6 5V 10 V 15 V th hold time DS to CP; see Figure 5 5V 10 V 15 V Dn to PL; see Figure 6 5V 10 V 15 V tW pulse width CP = LOW; minimum width; see Figure 5 PL = HIGH; minimum width; see Figure 6 trec recovery time PL input; see Figure 6 5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V fclk(max) maximum clock frequency CP input; see Figure 5 5V 10 V 15 V [1] [1] [1] Extrapolation formula 88 ns + (0.55 ns/pF) CL 39 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 78 ns + (0.55 ns/pF) CL 39 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 10 ns + (1.00 ns/pF) CL 9 ns + (0.42 ns/pF) CL 6 ns + (0.28 ns/pF) CL Min +25 +25 +15 50 30 20 40 20 15 +15 15 15 70 30 24 70 30 24 50 40 35 6 15 20 Typ 115 50 40 105 50 40 60 30 20 −15 −10 −5 25 10 5 20 10 8 −10 0 0 35 15 12 35 15 12 10 5 5 13 30 40 Max 230 100 80 210 100 80 120 60 40 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). HEF4021B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 7 of 14 NXP Semiconductors HEF4021B 8-bit static shift register Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (µW) PD = 900 × fi + Σ(fo × CL) × VDD 2 where: fi = input frequency in MHz, fo = output frequency in MHz, 2 PD = 4300 × fi + Σ(fo × CL) × VDD2 PD = 12000 × fi + Σ(fo × CL) × VDD CL = output load capacitance in pF, VDD = supply voltage in V, Σ(CL × fo) = sum of the outputs. 12. Waveforms VDD CP or PL INPUT VSS VOH Qn OUTPUT VOL VM tPHL VY VM VX tt tPLH tt 001aaj060 Fig 4. Waveforms showing propagation delays for CP and PL inputs to Qn output and Qn transition times 1 / fclk(max) VDD CP INPUT VSS tsu VDD DS INPUT VSS 001aae611 VM th tW VM Fig 5. Waveforms showing minimum clock pulse width, set-up time, and hold time for CP and DS. HEF4021B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 8 of 14 NXP Semiconductors HEF4021B 8-bit static shift register VDD CP INPUT VSS tW VDD PL INPUT VSS tsu VDD Dn INPUT VSS 90 % VM 10 % tf tr 001aae612 VM trec VM th Set-up times and hold times are shown as positive values but may be specified as negative values; Measurement points are given in Table 9. Fig 6. Table 9. VDD Waveforms showing minimum pulse width and recovery time for PL; set-up and hold times for Dn to PL. Measurement points Input VM 0.5VDD Output VM 0.5VDD VX 0.1VDD VY 0.9VDD Supply voltage 5 V to 15 V VDD VI G RT VO DUT CL 001aag182 Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 7. Table 10. VDD Test circuit Test data Input VI VSS or VDD tr, tf ≤ 20 ns Load CL 50 pF Supply voltage 5 V to 15 V HEF4021B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 9 of 14 NXP Semiconductors HEF4021B 8-bit static shift register 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 8. HEF4021B_4 Package outline SOT38-4 (DIP16) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 10 of 14 NXP Semiconductors HEF4021B 8-bit static shift register SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. HEF4021B_4 Package outline SOT109-1 (SO16) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 11 of 14 NXP Semiconductors HEF4021B 8-bit static shift register 14. Abbreviations Table 11. Acronym DUT ESD HBM MM Abbreviations Description Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 12. Revision history Release date 20081110 Data sheet status Product data sheet Change notice Supersedes HEF4021B_CNV_3 Document ID HEF4021B_4 Modifications: • • • • • • • • • • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Pins renamed throughout, see Figure 3 “Pin configuration” and Table 2 “Pin description”. Maximum temperature increased throughout and 125 °C data added to Table 6 “Static characteristics”. Section 2 “Features” added. Package version SOT38-1 changed to SOT38-4 in Section 4, and Figure 8. Package SOT74 removed from Section 4. Table 1 “Ordering information” restructured. Section 8 “Limiting values” and Section 10 “Static characteristics” added, taken from the HE4000B Family Specifications data sheet. IDD, IOL, IOH and II values updated in Section 10 “Static characteristics”. Section 9 “Recommended operating conditions” added. Figure references added to table Table 7 “Dynamic characteristics”. thold, tWCPL, tWPLH and tRPL changed to th, tW and trec for Table 7, Figure 5 and Figure 6. 50 % changed to VM for Figure 5 and 6. Table 9 “Measurement points”, Figure 7 “Test circuit” and Table 10 “Test data” added. Product specification Product specification HEF4021B_CNV_2 - HEF4021B_CNV_3 HEF4021B_CNV_2 19950101 19950101 HEF4021B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 12 of 14 NXP Semiconductors HEF4021B 8-bit static shift register 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4021B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 10 November 2008 13 of 14 NXP Semiconductors HEF4021B 8-bit static shift register 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 November 2008 Document identifier: HEF4021B_4