HEF4043B

HEF4043B Quad R/S latch with 3-state outputs Rev. 06 — 11 November 2008 Product data sheet 1. General description The HEF4043B is a quad R/S latch with 3-state outputs with a common output enable input (OE). Each latch has an active HIGH set input (1S to 4S), an active HIGH reset input (1R to 4R) and an active HIGH 3-state output (1Q to 4Q). When OE is HIGH, the latch output (nQ) is determined by the nR and nS inputs as shown in Table 3. When OE is LOW, the latch outputs are in the high impedance OFF-state. OE does not affect the state of the latch. The high impedance off-state feature allows common bussing of the outputs. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the industrial (−40 °C to +85 °C) temperature range. 2. Features I I I I I I Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range −40 °C to +85 °C Complies with JEDEC standard JESD 13-B ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 3. Applications I Four-bit storage with output enable 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +85 °C. Type number HEF4043BP HEF4043BT Package Name DIP16 SO16 Description plastic dual in-line package; 16-leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm Version SOT38-4 SOT109-1 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs 5. Functional diagram 4 1S 1Q 2 3 1R 6 2S 2Q 9 7 2R 3-STATE OUTPUTS 3Q 10 11 3R nS nQ 12 3S 14 4S 4Q 1 15 4R nR nOE 5 OE to other latches 001aae616 001aae618 Fig 1. Functional diagram Fig 2. Logic diagram for one latch 6. Pinning information 6.1 Pinning HEF4043B 4Q 1Q 1R 1S OE 2S 2R VSS 1 2 3 4 5 6 7 8 001aae617 16 VDD 15 4R 14 4S 13 n.c. 12 3S 11 3R 10 3Q 9 2Q Fig 3. Pin configuration HEF4043B_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 11 November 2008 2 of 13 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs 6.2 Pin description Table 2. Symbol 1Q to 4Q 1R to 4R 1S to 4S OE VSS n.c. VDD Pin description Pin 2, 9, 10, 1 3, 7, 11, 15 4, 6, 12, 14 5 8 13 16 Description 3-state buffered latch output reset input (active HIGH) set input (active HIGH) common output enable input ground supply voltage not connected supply voltage 7. Functional description Table 3. Inputs OE L H H H [1] Function table[1] Output nS X L H L nR X H X L nQ Z L H latched H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI IIK IOK II/O Tstg Tamb Ptot Parameter supply voltage input voltage input clamping current output clamping current input/output current storage temperature ambient temperature total power dissipation Tamb −40 °C to +85 °C DIP16 package SO16 package P [1] [2] [1] [2] Conditions Min −0.5 −0.5 Max +18 VDD + 0.5 ±10 ±10 ±10 +150 +85 750 500 100 Unit V V mA mA mA °C °C mW mW mW VI < 0.5 V or VI > VDD + 0.5 V VO < 0.5 V or VO > VDD + 0.5 V −65 −40 - power dissipation per output For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. HEF4043B_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 11 November 2008 3 of 13 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs 9. Recommended operating conditions Table 5. Symbol VDD VI Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 −40 Typ Max 15 VDD +85 3.75 0.5 0.08 Unit V V °C ns/V ns/V ns/V 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 µA VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 µA 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 µA 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 µA 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V VO = 13.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IOZ input leakage current OFF-state output current nQ output HIGH; returned to VDD nQ output LOW; returned to VSS 5V 5V 10 V 15 V 5V 10 V 15 V 15 V 15 V 15 V Tamb = −40 °C Tamb = 25 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.7 −0.52 −1.3 −3.6 0.52 1.3 3.6 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.3 1.6 1.6 Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.4 −0.44 −1.1 −3.0 0.44 1.1 3.0 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.3 1.6 1.6 Tamb = 85 °C Unit Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±1.0 12.0 12.0 V V V V V V V V V V V V mA mA mA mA mA mA mA µA µA µA HEF4043B_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 11 November 2008 4 of 13 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs Table 6. Static characteristics …continued VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter IDD supply current Conditions IO = 0 A VDD 5V 10 V 15 V CI input capacitance Tamb = −40 °C Tamb = 25 °C Min Max 20 40 80 Min Max 20 40 80 7.5 Tamb = 85 °C Unit Min Max 150 300 600 µA µA µA pF 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; For waveforms and test circuit see Section 12; unless otherwise specified. Symbol tPHL Parameter HIGH to LOW propagation delay Conditions nR → nQ; see Figure 4 VDD 5V 10 V 15 V tPLH LOW to HIGH propagation delay nS → nQ; see Figure 4 5V 10 V 15 V tt transition time nQ output; see Figure 4 5V 10 V 15 V tPHZ HIGH to OFF-state propagation delay OE → nQ; see Figure 5 5V 10 V 15 V tPLZ LOW to OFF-state propagation delay OE → nQ; see Figure 5 5V 10 V 15 V tPZH OFF-state to HIGH propagation delay OE → nQ; see Figure 5 5V 10 V 15 V tPZL OFF-state to LOW propagation delay OE → nQ; see Figure 5 5V 10 V 15 V tW pulse width nS input HIGH; 5V minimum width; 10 V see Figure 4 15 V nR input HIGH; 5 V minimum width; 10 V see Figure 4 15 V [1] [2] [1] [2] [1] [1] Extrapolation formula 63 ns + (0.55 ns/pF)CL 24 ns + (0.23 ns/pF)CL 17 ns + (0.16 ns/pF)CL 38 ns + (0.55 ns/pF)CL 14 ns + (0.23 ns/pF)CL 7 ns + (0.16 ns/pF)CL 10 ns + (1.00 ns/pF)CL 9 ns + (0.42 ns/pF)CL 6 ns + (0.28 ns/pF)CL Min 30 20 16 30 20 16 Typ 90 35 25 65 25 15 60 30 20 45 20 10 50 20 10 25 15 10 40 20 15 15 10 8 15 10 8 Max 180 70 50 135 50 35 120 60 40 90 35 25 100 40 25 50 30 25 80 45 35 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). tt is the same as tTHL and tTLH. © NXP B.V. 2008. All rights reserved. HEF4043B_6 Product data sheet Rev. 06 — 11 November 2008 5 of 13 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (µW) PD = 1100 × fi + Σ(fo × CL) × VDD2 2 where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; Σ(CL × fo) = sum of the outputs. PD = 4400 × fi + Σ(fo × CL) × VDD2 PD = 11400 × fi + Σ(fo × CL) × VDD 12. Waveforms tr VI input nS 0V tf 90 % VM 10 % tW VI input nR 0V tW tPLH VOH output nQ VOL tPHL VM 90 % VM 10 % tTLH tTHL 001aai286 tr and tf are the input rise and fall times Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Transition times: transition time (tt) = HIGH LOW (tTHL) or LOW HIGH (tTLH) transition times. Measurement points are given in Table 9 and test data is given in Table 10. Fig 4. Input minimum set (nS) and reset (nR) pulse widths, inputs nS or nR to latch output (nQ) propagation delay and nQ transition time HEF4043B_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 11 November 2008 6 of 13 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs VDD OE input VSS tPLZ output LOW-to-OFF OFF-to-LOW VDD tPZL VY VM VSS tPHZ VDD VX tPZH VY VX outputs on outputs off outputs on 001aag355 output HIGH-to-OFF OFF-to-HIGH VSS Measurement points are given in Table 9. Fig 5. Table 9. VDD Output enable (OE) to latch output (nQ) enable time (tPZL and tPZH) and disable time (tPLZ and tPHZ) Measurement points Input VI VDD or 0 V VM 0.5VDD Output VM 0.5VDD VX 0.1VDD VY 0.9VDD Supply voltage 5 V to 15 V HEF4043B_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 11 November 2008 7 of 13 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VDD VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aai546 Test and measurement data is given in Table 10. Definitions test circuit: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 6. Table 10. Test circuit for measuring switching times Test data Input VI tr, tf ≤ 20 ns VDD Load CL 50 pF RL 1 kΩ VEXT tPLH, tPHL open tPLZ, tPZL 2VDD tPHZ, tPZH GND Supply voltage 5 V to 15 V HEF4043B_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 11 November 2008 8 of 13 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 7. HEF4043B_6 Package outline SOT38-4 (DIP16) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 11 November 2008 9 of 13 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 8. HEF4043B_6 Package outline SOT109-1 (SO16) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 11 November 2008 10 of 13 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs 14. Abbreviations Table 11. Acronym DUT ESD HBM MM Abbreviations Description Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 12. Revision history Release date 20081111 Data sheet status Product data sheet Change notice Supersedes HEF4043B_5 Document ID HEF4043B_6 Modifications: • • • Maximum Tamb changed to 85 °C and Tamb = 125 °C parameter data removed throughout. Section 1 “General description” temperature range statement modified. Table 6 “Static characteristics” IOH, IOL, IOZ and IDD values updated. Product data sheet Product data sheet Product specification Product specification HEF4043B_4 HEF4043B_CNV_3 HEF4043B_CNV_2 - HEF4043B_5 HEF4043B_4 HEF4043B_CNV_3 HEF4043B_CNV_2 20080729 20080710 19950101 19950101 HEF4043B_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 11 November 2008 11 of 13 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4043B_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 11 November 2008 12 of 13 NXP Semiconductors HEF4043B Quad R/S latch with 3-state outputs 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 November 2008 Document identifier: HEF4043B_6