HEF4071BP

HEF4071B Quad 2-input OR gate Rev. 06 — 1 December 2009 Product data sheet 1. General description The HEF4071B is a quad 2-input OR gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over both the industrial (−40 °C to +85 °C) and automotive (−40 °C to +125 °C) temperature ranges. 2. Features Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Inputs and outputs are protected against electrostatic effects Operates across the automotive temperature range from −40 °C to +125 °C Complies with JEDEC standard JESD 13-B 3. Applications Automotive and industrial 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +125 °C. Type number HEF4071BP HEF4071BT Package Name DIP14 SO14 Description plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm Version SOT27-1 SOT108-1 NXP Semiconductors HEF4071B Quad 2-input OR gate 5. Functional diagram 1 2 5 6 8 9 12 13 1A 1B 2A 2B 3A 3B 4A 4B 1Y 3 2Y 4 3Y 10 4Y 11 nA nB nY 001aaj108 001aaj110 Fig 1. Functional diagram Fig 2. Logic diagram (one gate) 6. Pinning information 6.1 Pinning HEF4071B 1A 1B 1Y 2Y 2A 2B VSS 1 2 3 4 5 6 7 001aaj107 14 VDD 13 4B 12 4A 11 4Y 10 3Y 9 8 3B 3A Fig 3. Pin configuration 6.2 Pin description Table 2. Symbol 1A to 4A 1B to 4B 1Y to 4Y VSS VDD Pin description Pin 1, 5, 8, 12 2, 6, 9, 13 3, 4, 10, 11 7 14 Description input input output ground (0 V) supply voltage HEF4071B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 1 December 2009 2 of 11 NXP Semiconductors HEF4071B Quad 2-input OR gate 7. Functional description Table 3. Input nA L L H H [1] Function table[1] Output nB L H L H nY L H H H H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol VDD IIK VI IOK II/O IDD Tstg Tamb Ptot Parameter supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation Tamb = −40 °C to + 125 °C DIP14 SO14 P [1] [2] [1] [2] Conditions VI < −0.5 V or VI > VDD + 0.5 V VO < −0.5 V or VO > VDD + 0.5 V Min −0.5 −0.5 −65 −40 - Max +18 ±10 VDD + 0.5 ±10 ±10 50 +150 +125 750 500 100 Unit V mA V mA mA mA °C °C mW mW mW power dissipation per output For DIP14 packages: above Tamb = 70 °C, Ptot derates linearly with 12 mW/K. For SO14 packages: above Tamb = 70 °C, Ptot derates linearly with 8 mW/K. 9. Recommended operating conditions Table 5. Symbol VDD VI Tamb Δt/ΔV Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 −40 Max 15 VDD +125 3.75 0.5 0.08 Unit V V °C μs/V μs/V μs/V HEF4071B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 1 December 2009 3 of 11 NXP Semiconductors HEF4071B Quad 2-input OR gate 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 μA VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 μA 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 μA 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 μA 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V VO = 13.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current 5V 5V 10 V 15 V 5V 10 V 15 V 15 V 5V all valid input combinations; 10 V IO = 0 A 15 V Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.7 −0.64 −1.6 −4.2 0.64 1.6 4.2 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.1 0.25 0.5 1.0 Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.4 −0.5 −1.3 −3.4 0.5 1.3 3.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.1 0.25 0.5 1.0 7.5 Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±1.0 7.5 15.0 30.0 Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±1.0 7.5 15.0 30.0 V V V V V V V V V V V V mA mA mA mA mA mA mA μA μA μA μA pF CI input capacitance HEF4071B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 1 December 2009 4 of 11 NXP Semiconductors HEF4071B Quad 2-input OR gate 11. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 °C; waveforms see Figure 4; test circuit see Figure 5; unless otherwise specified. [1] Symbol Parameter tPHL HIGH to LOW propagation delay Conditions nA or nB to nY VDD 5V 10 V 15 V tPLH LOW to HIGH propagation delay nA or nB to nY 5V 10 V 15 V tt transition time 5V 10 V 15 V [1] [2] [2] Extrapolation formula 28 ns + (0.55 ns/pF)CL 15 ns + (0.23 ns/pF)CL 12 ns + (0.16 ns/pF)CL 18 ns + (0.55 ns/pF)CL 9 ns + (0.23 ns/pF)CL 7 ns + (0.16 ns/pF)CL 10 ns + (1.00 ns/pF)CL 9 ns + (0.42 ns/pF)CL 6 ns + (0.28 ns/pF)CL Min - Typ 55 25 20 45 20 15 60 30 20 Max 115 50 35 90 45 30 120 60 40 Unit ns ns ns ns ns ns ns ns ns The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF). tt is the same as tTHL and tTLH. Table 8. Dynamic power dissipation VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter PD dynamic power dissipation VDD Typical formula 2 where: fi = input frequency in MHz; 5 V PD = 1150 × fi + Σ(fo × CL) × VDD (μW) 10 V PD = 4800 × fi + Σ(fo × CL) × VDD2 (μW) fo = output frequency in MHz; 15 V PD = 19700 × fi + Σ(fo × CL) × VDD2 (μW) CL = output load capacitance in pF; Σ(fo × CL) = sum of the outputs; VDD = supply voltage in V. 12. Waveforms tr VI nA, nB input 0V tf 90 % VM 10 % tPLH tPHL VOH nY output VOL 90 % VM 10 % tTLH tTHL 001aai140 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. Input to output propagation delay and output transition times HEF4071B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 1 December 2009 5 of 11 NXP Semiconductors HEF4071B Quad 2-input OR gate Table 9. VDD 5 V to 15 V Measurement points Input VM 0.5VDD Output VM 0.5VDD Supply voltage VDD VI G RT VO DUT CL 001aag182 Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 5. Table 10. VDD Test circuit Test data Input VI VSS or VDD tr, tf ≤ 20 ns Load CL 50 pF Supply voltage 5 V to 15 V HEF4071B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 1 December 2009 6 of 11 NXP Semiconductors HEF4071B Quad 2-input OR gate 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D seating plane ME A2 A L A1 c Z e b1 b 14 8 MH wM (e 1) pin 1 index E 1 7 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 6. HEF4071B_6 Package outline SOT27-1 (DIP14) © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 1 December 2009 7 of 11 NXP Semiconductors HEF4071B Quad 2-input OR gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 (A 3) θ Lp L A 1 7 e bp wM detail X 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ o 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 7. HEF4071B_6 Package outline SOT108-1 (SO14) © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 1 December 2009 8 of 11 NXP Semiconductors HEF4071B Quad 2-input OR gate 14. Revision history Table 11. Revision history Release date 20091201 Data sheet status Product data sheet Product data sheet Product data sheet Product specification Product specification Change notice Supersedes HEF4071B_5 HEF4071B_4 HEF4071B_CNV_3 HEF4071B_CNV_2 Document ID HEF4071B_6 Modifications: HEF4071B_5 HEF4071B_4 HEF4071B_CNV_3 HEF4071B_CNV_2 • Section 9 “Recommended operating conditions” Δt/ΔV values updated. 20090728 20081128 19950101 19950101 HEF4071B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 1 December 2009 9 of 11 NXP Semiconductors HEF4071B Quad 2-input OR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 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Export might require a prior authorization from national authorities. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4071B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 1 December 2009 10 of 11 NXP Semiconductors HEF4071B Quad 2-input OR gate 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contact information. . . . . . . . . . . . . . . . . . . . . 10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 December 2009 Document identifier: HEF4071B_6