HEF4511BP

HEF4511B BCD to 7-segment latch/decoder/driver Rev. 06 — 7 December 2009 Product data sheet 1. General description The HEF4511B is a BCD to 7-segment latch/decoder/driver with four address inputs (D0 to D3), an active HIGH latch enable input (LE), an active LOW ripple blanking input (BL), an active LOW lamp test input (LT), and seven active HIGH NPN bipolar transistor segment outputs (Qa to Qg). When LE is LOW and BL is HIGH, the state of the segment outputs (Qa to Qg) is determined by the data on D0 to D3. When LE goes HIGH, the last data present on D0 to D3 is stored in the latches and the segment outputs remain unchanged. When LT is LOW, all of the segment outputs are HIGH independent of all other input conditions. With LT HIGH, a LOW on BL forces all segment outputs LOW. The inputs LT and BL do not affect the latch circuit. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the industrial (−40 °C to +85 °C) and automotive (−40 °C to +125 °C) temperature ranges. 2. Features Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the automotive temperature range −40 °C to +125 °C Complies with JEDEC standard JESD 13-B 3. Applications Automotive and industrial 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +125 °C. Type number HEF4511BP HEF4511BT Package Name DIP16 SO16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm Version SOT38-4 SOT109-1 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver 5. Functional diagram 7 D0 5 LE 1 D1 LATCHES 2 D2 6 D3 4 BL DECODER 3 LT DRIVERS Qg 14 Qf 15 Qe 9 Qd 10 Qc 11 Qb 12 Qa 13 001aae675 Fig 1. Functional diagram VDD driver logic IOH + VOH − VSS 001aae677 Fig 2. Schematic diagram of output stage HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 2 of 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 06 — 7 December 2009 3 of 19 HEF4511B_6 NXP Semiconductors D0 D1 D2 D3 BL D latch CP 1 Q D latch CP 2 Q D latch CP 3 Q D latch CP 4 Q Q LE Q Q Q BCD to 7-segment latch/decoder/driver LT HEF4511B Qg © NXP B.V. 2009. All rights reserved. Qf Qe Qd Qc Qb Qa 001aae679 Fig 3. Logic diagram NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver 6. Pinning information 6.1 Pinning HEF4511B D1 D2 LT BL LE D3 D0 VSS 1 2 3 4 5 6 7 8 001aae676 16 VDD 15 Qf 14 Qg 13 Qa 12 Qb 11 Qc 10 Qd 9 Qe Fig 4. Pin configuration DIP16 and SO16 6.2 Pin description Table 2. Symbol LT BL LE D0 to D3 VSS Qa to Qg VDD Pin description Pin 3 4 5 7, 1, 2, 6 8 13, 12, 11, 10, 9, 15, 14 16 Description lamp test input (active LOW) ripple blanking input (active LOW) latch enable input (active HIGH) address (data) input ground supply voltage segment output supply voltage HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 4 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver 7. Functional description Table 3. Inputs LE X X L L L L L L L L L L L L H [1] Function table[1] Outputs BL X L H H H H H H H H H H H H H LT L H H H H H H H H H H H H H H D3 X X L L L L L L L L H H H H X D2 X X L L L L H H H H L L L H X D1 X X L L H H L L H H L L H X X D0 X X L H L H L H L H L H X X X Qa H L H L H H L H L H H H L L N.C. Qb H L H H H H H L L H H H L L N.C. Qc H L H H L H H H H H H H L L N.C. Qd H L H L H H L H H L H L L L N.C. Qe H L H L H L L L H L H L L L N.C. Qf H L H L L L H H H L H H L L N.C. Qg H L L L H H H H H L H H L L N.C. 8 blank 0 1 2 3 4 5 6 7 8 9 blank blank N.C. Display H = HIGH voltage level; L = LOW voltage level; X = don’t care; N.C. = no change. a f e g d b c 001aaj494 Fig 5. Seven segment digital display with segment designation HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 5 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IIK VI IOK II/O IOH IDD Tstg Tamb Ptot Parameter supply voltage input clamping current input voltage output clamping current input/output current HIGH-level output current supply current storage temperature ambient temperature total power dissipation Tamb = 125 °C DIP16 package SO16 package P [1] [2] [3] [2] [3] [1] Conditions VI < −0.5 V or VI > VDD + 0.5 V VO < −0.5 V or VO > VDD + 0.5 V Min −0.5 −0.5 −25 −65 −40 - Max +18 ±10 VDD + 0.5 ±10 ±10 50 +150 +125 750 500 100 Unit V mA V mA mA mA mA °C °C mW mW mW power dissipation per output A destructive high current mode may occur if VI and VO are not constrained to the range VSS ≤ VI or VO ≤ VDD. For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. 9. Recommended operating conditions Table 5. Symbol VDD VI Tamb Δt/ΔV Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 −40 Typ Max 15 VDD +125 3.75 0.5 0.08 Unit V V °C μs/V μs/V μs/V HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 6 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 μA VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 μA 5V 10 V 15 V VOH VOL HIGH-level output voltage LOW-level output voltage see Table 7 |IO| < 1 μA 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current IO = 0 A 5V 5V 10 V 5V 10 V 15 V 15 V 5V 10 V 15 V CI input capacitance Tamb = −40 °C Tamb = +25 °C Min 3.5 7.0 11.0 −1.7 −0.64 −1.6 −4.2 0.64 1.6 4.2 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.1 5 10 20 Min 3.5 7.0 11.0 −1.4 −0.5 −1.3 −3.4 0.5 1.3 3.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.1 5 10 20 7.5 Tamb = +85 °C Min 3.5 7.0 11.0 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±1.0 150 300 600 Tamb = +125 °C Unit Min 3.5 7.0 11.0 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±1.0 150 300 600 V V V V V V V V V mA mA mA mA mA mA mA μA μA μA μA pF VO = 13.5 V 15 V HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 7 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver Table 7. Static characteristics for VOH VSS = 0 V. Symbol VOH Parameter HIGH-level output voltage IOH mA 0 VDD V 5V 10 V 15 V 5 5V 10 V 15 V 10 5V 10 V 15 V 15 5V 10 V 15 V 20 5V 10 V 15 V 25 5V 10 V 15 V Tamb = −40 °C Min 4.10 9.10 14.10 3.60 8.75 13.75 2.80 8.10 13.10 Tamb = +25 °C Min 4.10 9.10 14.10 3.60 8.75 13.75 2.80 8.10 13.10 Typ 4.40 9.90 14.40 4.30 9.30 14.30 4.25 9.25 14.30 4.20 9.20 14.20 4.20 9.20 14.20 4.15 9.20 14.20 Tamb = +85 °C Min 4.10 9.10 14.10 3.30 8.45 13.45 2.50 7.80 12.80 Tamb = +125 °C Min 4.10 9.10 14.10 3.20 8.35 13.35 2.30 7.60 12.60 V V V V V V V V V V V V V V V V V V Unit 11. Dynamic characteristics Table 8. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8. Symbol tPHL Parameter HIGH to LOW propagation delay Conditions Dn → Qn; see Figure 6 VDD 5V 10 V 15 V LE → Qn; see Figure 6 5V 10 V 15 V BL → Qn; see Figure 6 5V 10 V 15 V LT → Qn; see Figure 6 5V 10 V 15 V Extrapolation formula[1] 128 ns + (0.55 ns/pF)CL 49 ns + (0.23 ns/pF)CL 32 ns + (0.16 ns/pF)CL 133 ns + (0.55 ns/pF)CL 49 ns + (0.23 ns/pF)CL 37 ns + (0.16 ns/pF)CL 93 ns + (0.55 ns/pF)CL 39 ns + (0.23 ns/pF)CL 27 ns + (0.16 ns/pF)CL 52 ns + (0.55 ns/pF)CL 19 ns + (0.23 ns/pF)CL 12 ns + (0.16 ns/pF)CL Min Typ 155 60 40 160 60 45 120 50 35 80 30 20 Max 310 120 80 320 120 90 240 100 70 160 60 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 8 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver Table 8. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8. Symbol tPLH Parameter LOW to HIGH propagation delay Conditions Dn → Qn; see Figure 6 VDD 5V 10 V 15 V LE → Qn; see Figure 6 5V 10 V 15 V BL → Qn; see Figure 6 5V 10 V 15 V LT → Qn; see Figure 6 5V 10 V 15 V tTHL HIGH to LOW output see Figure 6 transition time 5V 10 V 15 V tTLH LOW to HIGH output see Figure 6 transition time 5V 10 V 15 V tsu set-up time Dn → LE; see Figure 7 5V 10 V 15 V th hold time Dn → LE; see Figure 7 5V 10 V 15 V tW pulse width LE input LOW; minimum width; see Figure 7 5V 10 V 15 V Extrapolation formula[1] 108 ns + (0.55 ns/pF)CL 44 ns + (0.23 ns/pF)CL 32 ns + (0.16 ns/pF)CL 133 ns + (0.55 ns/pF)CL 59 ns + (0.23 ns/pF)CL 42 ns + (0.16 ns/pF)CL 78 ns + (0.55 ns/pF)CL 29 ns + (0.23 ns/pF)CL 22 ns + (0.16 ns/pF)CL 33 ns + (0.55 ns/pF)CL 19 ns + (0.23 ns/pF)CL 17 ns + (0.16 ns/pF)CL 10 ns + (1.00 ns/pF)CL 9 ns + (0.42 ns/pF)CL 6 ns + (0.28 ns/pF)CL 20 ns + (1.00 ns/pF)CL 13 ns + (0.06 ns/pF)CL 10 ns + (0.06 ns/pF)CL Min 50 25 20 60 30 25 80 40 35 Typ 135 55 40 160 70 50 105 40 30 60 30 25 60 30 20 25 16 13 25 12 9 30 15 12 40 20 17 Max 270 110 80 320 140 100 210 80 60 120 60 50 120 60 40 50 32 26 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). Table 9. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (μW) PD = 1000 × fi + Σ(fo × CL) × VDD PD = 4000 × fi + Σ(fo × CL) × VDD 2 2 where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; Σ(fo × CL) = sum of the outputs. PD = 10000 × fi + Σ(fo × CL) × VDD2 HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 9 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver 12. Waveforms VI LE VSS VI D2 VSS VI LT VSS tPHL VI BL VSS tPLH tPHL VOH Qg VOL tTHL 90 % VM 10 % tTLH 001aaj495 VM VM VM VM tPLH tPHL tPHL tPLH tPLH Conditions: D3 = LOW and D0 = D1 = HIGH. Measurement points are given in Table 10. Fig 6. Propagation delays and output transition times HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 10 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver VI LE input VSS tW VI D2 input VSS tsu th VOH Qg output VOL 001aae682 VM VM The shaded area indicates where the input is permitted to change for predictable output performance. Conditions: D3 = LOW and D0 = D1 = BL = LT = HIGH. Measurement points are given in Table 10. Fig 7. Waveforms showing minimum LE pulse width, set-up, and hold time for Dn to LE HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 11 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW 001aaj781 VM VI positive pulse 0V VM a. Input waveforms VDD VI G RT VO DUT CL 001aag182 b. Test circuit Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 8. Table 10. Test circuit for measuring switching times Measurement points and test data Input VI VM 0.5VI tr, tf ≤ 20 ns VDD Load CL 50 pF Supply voltage 5 V to 15 V HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 12 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver 13. Application information • • • • • VDD VDD Driving LED displays Driving incandescent displays Driving fluorescent displays Driving LCD displays Driving gas discharge displays common anode LED ≈ 1.7 V common cathode LED ≈ 1.7 V VSS 001aae683 VSS 001aae684 Fig 9. Connection to common cathode LED display readout Fig 10. Connection to common anode LED display readout VDD VDD VDD direct (low brightness) (1) VSS VSS 001aae685 to filament supply VSS 001aae686 (1) A filament pre-warm resistor is recommended to reduce filament thermal shock and increase the effective cold resistance of the filament. Fig 11. Connection to incandescent display readout Fig 12. Connection to fluorescent display readout HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 13 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver VDD appropriate voltage VDD exitation (square wave; VSS to VDD) 1/4 HEF4070B VSS 001aae687 VSS 001aae688 Direct DC drive of LCDs not recommended for life of LCD readouts. Fig 13. Connection to gas discharge display readout Fig 14. Connection to LCD readout HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 14 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver 14. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 15. Package outline SOT38-4 (DIP16) HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 15 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 8 A1 (A 3) A L wM detail X e bp 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ o 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT109-1 (SO16) HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 16 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver 15. Revision history Table 11. Revision history Release date 20091207 Data sheet status Product data sheet Product data sheet Product data sheet Product specification Product specification Change notice Supersedes HEF4511B_5 HEF4511B_4 HEF4511B_CNV_3 HEF4511B_CNV_2 Document ID HEF4511B_6 Modifications: HEF4511B_5 HEF4511B_4 HEF4511B_CNV_3 HEF4511B_CNV_2 • Section 9 “Recommended operating conditions”: Δt/ΔV values updated. 20090813 20090305 19950101 19950101 HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 17 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4511B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 7 December 2009 18 of 19 NXP Semiconductors HEF4511B BCD to 7-segment latch/decoder/driver 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application information. . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 December 2009 Document identifier: HEF4511B_6