LPC11Axx
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash, 8 kB
SRAM, 4 kB EEPROM; configurable analog/mixed-signal
Rev. 4 — 30 October 2012
Product data sheet
1. General description
The LPC11Axx are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11Axx operate at CPU frequencies of up to 50 MHz.
Analog/mixed-signal subsystems can be configured by software from interconnected
digital and analog peripherals.
The digital peripherals on the LPC11Axx include up to 32 kB of flash memory, up to 4 kB
of EEPROM data memory, up to 8 kB of SRAM data memory, a Fast-mode Plus I2C-bus
interface, a RS-485/EIA-485 USART, two SSP controllers, four general purpose
counter/timers, and up to 42 general purpose I/O pins.
Analog peripherals include a 10-bit ADC, a 10-bit DAC, an analog comparator, a
temperature sensor, an internal voltage reference, and UnderVoltage LockOut (UVLO)
protection.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug (SWD)
JTAG boundary scan.
System tick timer.
Memory:
Up to 32 kB on-chip flash program memory.
Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.
Up to 8 kB SRAM data memory.
16 kB boot ROM.
In-System Programming (ISP) for flash and In-Application Programming (IAP) for
flash and EEPROM via on-chip bootloader software.
Includes ROM-based 32-bit integer division and I2C-bus driver routines.
Digital peripherals:
Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, and open-drain mode.
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
LPC11AXX
Product data sheet
Up to 16 pins are configurable with a digital input glitch filter for removing glitches
with widths of 10 ns or less and two pins are configurable for 50 ns glitch filters.
GPIO pins can be used as edge and level sensitive interrupt sources.
High-current source output driver (20 mA) on one pin (PIO0_21).
High-current sink driver (20 mA) on true open-drain pins (PIO0_2 and PIO0_3).
Four general purpose counter/timers with a total of up to 16 capture inputs and 14
match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDOsc).
Analog peripherals:
10-bit ADC with input multiplexing among 8 pins.
10-bit DAC with flexible conversion triggering.
Highly flexible analog comparator with a programmable voltage reference.
Integrated temperature sensor.
Internal voltage reference.
UnderVoltage Lockout (UVLO) protection against power-supply droop below 2.4 V.
Serial interfaces:
USART with fractional baud rate generation, internal FIFO, support for
RS-485/9-bit mode and synchronous mode.
Two SSP controllers with FIFO and multi-protocol capabilities. Support data rates
of up to 25 Mbit/s.
I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with
a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
Clock generation:
Crystal Oscillator (SysOsc) with an operating range of 1 MHz to 25 MHz.
12 MHz internal RC Oscillator (IRC) trimmed to 1% accuracy that can optionally be
used as a system clock.
Internal low-power, Low-Frequency Oscillator (LFOsc) with programmable
frequency output.
Clock input for external system clock (25 MHz typical).
PLL allows CPU operation up to the maximum CPU rate with the IRC, the external
clock, or the SysOsc as clock sources.
Clock output function with divider that can reflect the SysOsc, the IRC, the main
clock, or the LFOsc.
Power control:
Supports one reduced power mode: The ARM Sleep mode.
Power profiles residing in boot ROM allowing to optimize performance and
minimize power consumption for any given application through one simple function
call.
Processor wake-up from reduced power mode using any interrupt.
Power-On Reset (POR).
Brown-Out Detect (BOD) with two programmable thresholds for interrupt and one
hardware controlled reset trip point.
POR and BOD are always enabled for rapid UVLO protection against power supply
voltage droop below 2.4 V.
Unique device serial number for identification.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
2 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Single 3.3 V power supply (2.6 V to 3.6 V).
Temperature range 40 C to +85 C.
Available as LQFP48 package, HVQFN33 (7 7) and HVQFN33 (5 5) packages, and
in a very small WLCSP20 package.
3. Applications
Power management
Industrial control
Remote monitoring
Point-of-sale
Test and measurement equipment
Network appliances and services
Factory automation
Gaming equipment
Motion control
Medical instrumentation
Fire and security
Sensors
Precision instrumentation
HVAC and building control
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC11A02UK
WLCSP20 wafer level chip-size package; 20 bumps; 2.5 2.5 0.6 mm
-
LPC11A04UK
WLCSP20 wafer level chip-size package; 20 bumps; 2.5 2.5 0.6 mm
-
LPC11A11FHN33/001 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 7 7 0.85 mm
LPC11A12FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 7 7 0.85 mm
LPC11A13FHI33/201
HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 5 5 0.85 mm
LPC11A14FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 7 7 0.85 mm
LPC11A12FBD48/101 LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm
SOT313-2
LPC11A14FBD48/301 LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm
SOT313-2
LPC11AXX
Product data sheet
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Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
4.1 Ordering options
Flash
SRAM
EEPROM
10-bit DAC
Temperature sensor
Analog comparator
USART
SSP/SPI
I2C
GPIO
Ordering options
Type number
10-bit ADC channels
Table 2.
Package
LPC11A02UK
16 kB
4 kB
2 kB
8
1
1
1
1
1
1
18
WLCSP20
LPC11A04UK
32 kB
8 kB
4 kB
8
1
1
1
1
1
1
18
WLCSP20
LPC11A11FHN33/001
8 kB
2 kB
512 B
8
1
1
1
1
2
1
28
HVQFN33
LPC11A12FHN33/101
16 kB
4 kB
1 kB
8
1
1
1
1
2
1
28
HVQFN33
LPC11A12FBD48/101
16 kB
4 kB
1 kB
8
1
1
1
1
2
1
42
LQFP48
LPC11A13FHI33/201
24 kB
6 kB
2 kB
8
1
1
1
1
2
1
28
HVQFN33
LPC11A14FHN33/301
32 kB
8 kB
4 kB
8
1
1
1
1
2
1
28
HVQFN33
LPC11A14FBD48/301
32 kB
8 kB
4 kB
8
1
1
1
1
2
1
42
LQFP48
LPC11AXX
Product data sheet
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Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
SWD
XTALIN XTALOUT
LPC11Axx
SysOsc(3)
ARM
CORTEX-M0
system bus
BOD
CLKOUT
CLKIN
POR
EEPROM
512 B/
1/4 kB
clocks, internal voltage reference,
and controls
FLASH
8/16/24/32 kB
slave
HIGH-SPEED
GPIO
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
IRC, LFOSC, WDOSC
TEST/DEBUG
INTERFACE
GPIO ports
RESET
SRAM
2/4/6/8 kB
slave
ROM
16 kB
slave
slave
AHB-LITE BUS
slave
RXD
TXD
CTS, DCD, DSR, RI
RTS, DTR
SCLK
CT32B0_MAT[3:0]
CT32B0_CAP[2:0]
CT32B1_MAT[3:0]
CT32B1_CAP[2:0]
CT16B0_MAT[3:0]
CT16B0_CAP[2:0]
CT16B1_MAT[3:0]
CT16B1_CAP[2:0]
AHB TO APB
BRIDGE
USART(4)
AD[7:0]
ATRG[1:0]
10-bit ADC
TEMPERATURE SENSOR
32-bit COUNTER/TIMER 0
ACMP_I[5:1]
ACMP_O
VDDCMP
ANALOG COMPARATOR
32-bit COUNTER/TIMER 1
10-bit DAC
16-bit COUNTER/TIMER 0
AOUT
16-bit COUNTER/TIMER 1
SCL, SDA(1)
SCL, SDA(2)
SCL, SDA(2)
SCL, SDA(2)
I2C-BUS
WINDOWED WATCHDOG
TIMER
IOCONFIG
PMU
SYSTEM CONTROL
SSP0
SCK0, SSEL0,
MISO0, MOSI0
SSP1(3)
SCK1, SSEL1,
MISO1, MOSI1
002aaf428
(1) Open-drain pins.
(2) Standard I/O pins.
(3) Not available on WLCSP packages.
(4) Modem control pins not available on WLCSP packages.
Fig 1.
LPC11Axx block diagram
LPC11AXX
Product data sheet
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Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
6. Pinning information
LPC11AXX
Product data sheet
37 PIO1_2
38 SWDIO/PIO0_10
39 PIO0_11
40 PIO0_30
42 VSS
41 PIO0_15
44 VDD(3V3)
43 PIO0_27
45 PIO0_23
46 PIO0_12
PIO0_26
1
36 PIO1_1
PIO0_28
2
35 TRST/PIO0_9
RESET/PIO0_0
3
34 TDO/PIO0_8
PIO0_1
4
33 TMS/PIO0_7
VSS(IO)
5
XTALIN
6
XTALOUT
7
30 PIO0_14
VDD(IO)
8
29 TCK/SWCLK/PIO0_5
PIO0_24
9
28 PIO0_4
32 TDI/PIO0_6
LPC11A12FBD48/101
LPC11A14FBD48/301
31 PIO1_0
PIO0_31 24
PIO0_21 23
PIO0_20 22
PIO0_17 21
PIO1_5 20
PIO1_4 19
PIO0_16 18
PIO0_25 17
25 PIO1_7
PIO0_3 16
26 PIO1_8
PIO1_9 12
PIO0_2 15
27 PIO0_22
PIO1_6 11
PIO0_19 14
PIO0_18 10
PIO0_29 13
Fig 2.
47 PIO0_13
48 PIO1_3
6.1 Pinning
002aaf499
Pin configuration LQFP48 package
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LPC11Axx
NXP Semiconductors
VDD(3V3)
PIO0_27
PIO0_15
PIO0_11
SWDIO/PIO0_10
27
26
25
PIO0_23
28
PIO0_12
30
29
PIO0_13
31
terminal 1
index area
32
32-bit ARM Cortex-M0 microcontroller
PIO0_26
1
24
RESET/PIO0_0
2
23
TDO/PIO0_8
PIO0_1
3
22
TMS/PIO0_7
TRST/PIO0_9
XTALIN
4
21
TDI/PIO0_6
XTALOUT
5
20
PIO0_14
VDD(IO)
6
19
TCK/SWCLK/PIO0_5
PIO0_24
7
18
PIO0_4
PIO0_18
8
17
PIO0_22
9
10
11
12
13
14
15
16
PIO0_19
PIO0_2
PIO0_3
PIO0_25
PIO0_16
PIO0_17
PIO0_20
PIO0_21
33 VSS
002aaf500
Transparent top view
Parts: LPC11A11FHN33/001, LPC11A12FHN33/101, LPC11A13FHI33/201,
LPC11A14FHN33/301
Fig 3.
Pin configuration HVQFN 33 package
E
D
C
B
A
1
2
3
4
002aaf175
Parts: LPC11A02UK, LPC11A04UK
Fig 4.
Pin configuration WLCSP20 package
6.2 Pin description
All functional pins on the LPC11Axx are mapped to GPIO port 0 and port 1 (see Table 4).
The port pins are multiplexed to accommodate more than one function (see Table 3).
The pin function is controlled by the pin’s IOCON register (see the LPC11Axx user
manual). The standard I/O pad configuration is illustrated in Figure 31 and a detailed pin
description is given in Table 4.
LPC11AXX
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Function
Pin multiplexing
Type
LQFP48
HVQFN33
WCSP20
Glitch filter
Pin
Pin
Ball
PIO0_1
no
4
3
B2
PIO0_12
no
46
31
E1
PIO0_19
no
14
9
-
PIO0_24
no
9
7
-
PIO0_1
no
4
3
B2
PIO0_19
no
14
9
-
Port
System clocks, reset, and wake-up
CLKIN
CLKOUT
I
O
XTALIN
I
(analog)
-
-
6
4
-
XTALOUT
O
(analog)
-
-
7
5
-
RESET
I
PIO0_0
20 ns[1]
3
2
C1
PIO0_9
10 ns[2]
35
24
D4
PIO0_5
10
ns[2]
29
19
B3
10
ns[2]
32
21
C3
Serial Wire Debug (SWD) and JTAG
TRST
TCK
TDI
I
I
I
PIO0_6
TDO
O
PIO0_8
no
34
23
C2
TMS
I
PIO0_7
10 ns[2]
33
22
C4
PIO0_2
50
ns[2]
15
10
A1
10
ns[2]
29
19
B3
PIO0_3
50
ns[2]
16
11
B1
PIO0_10
10 ns[2]
38
25
D3
SWCLK
I
PIO0_5
SWDIO
I/O
Analog peripherals (ADC, DAC, comparator)
LPC11AXX
Product data sheet
ACMP_I1
I
(analog)
PIO0_27
no
43
28
-
ACMP_I2
I
(analog)
PIO0_13
no
47
32
D1
ACMP_I3
I
(analog)
PIO0_16
no
18
13
A2
ACMP_I4
I
(analog)
PIO0_17
no
21
14
A3
ACMP_I5
I
(analog)
PIO0_22
no
27
17
-
ACMP_O
O
(digital)
PIO0_2
no
15
10
A1
PIO0_3
no
16
11
B1
PIO0_12
no
46
31
E1
PIO0_21
no
23
16
-
PIO0_23
no
45
30
-
AD0
I
(analog)
PIO0_6
no
32
21
C3
AD1
I
(analog)
PIO0_7
no
33
22
C4
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Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin multiplexing
Function
Type
LQFP48
HVQFN33
WCSP20
Port
Glitch filter
Pin
Pin
Ball
AD2
I
(analog)
PIO0_8
no
34
23
C2
AD3
I
(analog)
PIO0_9
no
35
24
D4
AD4
I
(analog)
PIO0_10
no
38
25
D3
AD5
I
(analog)
PIO0_11
no
39
26
D2
AD6
I
(analog)
PIO0_14
no
30
20
B4
AD7
I
(analog)
PIO0_15
no
41
27
E4
AOUT
O
(analog)
PIO0_4
no
28
18
A4
ATRG0
I
PIO0_16
10 ns[2]
18
13
A2
ATRG1
I
PIO0_17
10 ns[2]
21
14
A3
VDDCMP
I
(analog)
PIO0_14
no
30
20
-
PIO0_5
no
-
-
B3
PIO0_2
50 ns[2]
15
10
A1
PIO0_12
no
46
31
E1
18
13
A2
I2C-bus
interface
SCL
I/O
PIO0_16
SDA
I/O
10
ns[2]
PIO0_24
no
9
7
-
PIO0_3
50 ns[2]
16
11
B1
10
ns[2]
47
32
D1
PIO0_15
10
ns[2]
41
27
E4
PIO0_25
no
17
12
-
PIO0_6
10 ns[2]
32
21
C3
ns[2]
27
17
-
PIO0_13
SSP0 controller
MISO0
I/O
PIO0_22
MOSI0
SCK0
SSEL0
LPC11AXX
Product data sheet
I/O
I/O
I/O
10
PIO1_2
no
37
-
-
PIO0_4
10 ns[2]
28
18
A4
PIO0_19
no
14
9
-
PIO1_3
no
48
-
-
PIO1_7
no
25
-
-
PIO0_5
10 ns[2]
29
19
B3
PIO0_20
no
22
15
-
PIO1_0
no
31
-
-
PIO0_1
no
4
3
B2
PIO0_18
no
10
8
-
PIO1_1
no
36
-
-
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Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin multiplexing
Function
Type
LQFP48
HVQFN33
WCSP20
Port
Glitch filter
Pin
Pin
Ball
PIO0_14
10 ns[2]
30
20
-
SSP1 controller
MISO1
MOSI1
SCK1
SSEL1
I/O
I/O
I/O
I/O
PIO0_26
no
1
1
-
PIO1_8
no
26
-
-
43
28
-
24
-
-
PIO0_27
10
PIO0_31
no
ns[2]
PIO0_30
no
40
-
-
PIO1_6
no
11
-
-
PIO0_8
10 ns[2]
34
23
-
PIO1_5
no
20
-
-
PIO0_29
no
13
-
-
PIO0_25
no
17
12
-
PIO1_4
no
19
-
-
PIO0_28
no
2
-
-
PIO0_1
no
4
3
B2
PIO0_12
no
46
31
E1
PIO1_4
no
19
-
-
USART
RXD
TXD
SCLK
CTS
RTS
DCD
DSR
DTR
LPC11AXX
Product data sheet
I
O
I/O
I
O
I
I
O
PIO1_8
no
26
-
-
PIO0_13
no
47
32
D1
PIO0_15
no
41
27
E4
PIO0_26
no
1
1
-
PIO1_5
no
20
-
-
PIO0_11
10 ns[2]
39
26
D2
PIO0_21
no
23
16
-
PIO0_23
no
45
30
-
ns[2]
PIO0_9
10
35
24
D4
PIO0_21
no
23
16
-
PIO1_7
no
25
-
-
PIO0_10
no
38
25
D3
PIO0_23
no
45
30
-
PIO1_6
no
11
-
-
PIO1_9
no
12
-
-
PIO1_0
no
31
-
-
PIO0_29
no
13
-
-
PIO1_2
no
37
-
-
PIO0_28
no
2
-
-
PIO1_1
no
36
-
-
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Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
10 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Function
RI
Pin multiplexing
Type
I
LQFP48
HVQFN33
WCSP20
Port
Glitch filter
Pin
Pin
Ball
PIO0_30
no
40
-
-
PIO0_31
no
24
-
-
PIO1_3
no
48
-
-
PIO0_2
50 ns[2]
15
10
A1
PIO0_18
no
10
8
-
16-bit counter/timer CT16B0
CT16B0_CAP0 I
CT16B0_CAP1 I
PIO0_30
no
40
-
-
PIO0_16
10 ns[2]
18
13
A2
PIO1_4
no
19
-
-
21
14
A3
ns[2]
CT16B0_CAP2 I
PIO0_17
10
PIO1_5
no
20
-
-
CT16B0_MAT0 O
PIO0_7
no
33
22
C4
PIO0_17
no
21
14
A3
PIO1_6
no
11
-
-
CT16B0_MAT1 O
CT16B0_MAT2 O
PIO0_4
no
28
18
A4
PIO0_9
no
35
24
D4
PIO1_0
no
31
-
-
PIO0_5
no
29
19
B3
PIO0_10
no
38
25
D3
PIO1_7
no
25
-
-
50 ns[2]
16
11
B1
16-bit counter/timer CT16B1
CT16B1_CAP0 I
CT16B1_CAP1 I
CT16B1_CAP2 I
CT16B1_MAT0 O
CT16B1_MAT1 O
CT16B1_MAT2 O
LPC11AXX
Product data sheet
PIO0_3
PIO0_24
no
9
7
-
PIO1_3
no
48
-
-
PIO0_18
no
10
8
-
PIO0_26
no
1
1
-
PIO0_31
no
24
-
-
PIO0_27
10 ns[2]
43
28
-
PIO1_7
no
25
-
-
PIO0_19
no
14
9
-
PIO0_25
no
17
12
-
PIO1_1
no
36
-
-
PIO0_14
no
30
20
B4
PIO1_2
no
37
-
-
PIO1_8
no
26
-
-
PIO0_20
no
22
15
-
PIO1_2
no
37
-
-
PIO1_9
no
12
-
-
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
11 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Function
Pin multiplexing
Type
LQFP48
HVQFN33
WCSP20
Glitch filter
Pin
Pin
Ball
PIO0_11
10 ns[2]
39
26
D2
PIO0_23
no
45
30
-
PIO0_28
no
2
-
-
30
20
B4
13
-
-
Port
32-bit counter/timer CT32B0
CT32B0_CAP0 I
CT32B0_CAP1 I
CT32B0_CAP2 I
CT32B0_MAT0 O
CT32B0_MAT1 O
CT32B0_MAT2 O
CT32B0_MAT3 O
PIO0_14
10
PIO0_29
no
ns[2]
ns[2]
PIO0_15
10
41
27
E4
PIO0_26
no
1
1
-
PIO0_12
no
46
31
E1
PIO0_30
no
40
-
-
PIO0_13
no
47
32
D1
PIO1_4
no
19
-
-
PIO0_1
no
4
3
B2
PIO1_5
no
20
-
-
PIO0_6
no
32
21
C3
PIO1_6
no
11
-
-
PIO0_7
10 ns[2]
33
22
C4
PIO0_20
no
22
15
-
PIO1_4
no
19
-
-
PIO0_21
no
23
16
-
PIO1_5
no
20
-
-
32-bit counter/timer CT32B1
CT32B1_CAP0 I
CT32B1_CAP1 I
CT32B1_CAP2 I
CT32B1_MAT0 O
CT32B1_MAT1 O
CT32B1_MAT2 O
CT32B1_MAT3 O
ns[2]
PIO0_22
10
27
17
-
PIO1_6
no
11
-
-
PIO0_8
no
34
23
C2
PIO0_31
no
24
-
-
PIO1_8
no
26
-
-
PIO0_9
no
35
24
D4
PIO0_27
no
43
28
-
PIO1_7
no
25
-
-
PIO0_10
no
38
25
D3
PIO0_22
no
27
17
-
PIO1_9
no
12
-
-
PIO0_11
no
39
26
D2
PIO1_1
no
36
-
-
PIO1_0
no
31
-
-
-
-
8
6
E2
Supply and ground pins
VDD(IO)
LPC11AXX
Product data sheet
Supply
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
12 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin multiplexing
Function
Type
LQFP48
HVQFN33
WCSP20
Port
Glitch filter
Pin
Pin
Ball
VDD(3V3)
Supply
-
-
44
29
E2
VSS
Ground
-
-
42
33
E3
VSS(IO)
Ground
-
-
5
33
E3
[1]
Always on.
[2]
Programmable on/off. By default, the glitch filter is disabled.
Table 4 shows all pins in order of their port number. The default function after reset is
listed first. All port pins PIO0_0 to PIO1_9 have internal pull-up resistors enabled after
reset with the exception of the true open-drain pins PIO0_2 and PIO0_3.
Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed
through the IOCON registers for each of the port pins.
Table 4.
LPC11Axx pin description table
Symbol
Pin/Ball
Type Reset Description
state
LQFP48
HVQFN33
WLCSP20
[1]
3
2
C1
[2]
PIO0_1/RXD/CLKOUT/ 4
CT32B0_MAT2/SSEL0/
CLKIN
3
B2
[3]
RESET/PIO0_0
PIO0_2/SCL/ACMP_O/ 15 10 A1
TCK/SWCLK/
CT16B0_CAP0
LPC11AXX
Product data sheet
[4][5]
I
I; PU
RESET — External reset input with fixed 20 ns glitch filter: A
LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states and processor
execution to begin at address 0.
I/O
-
PIO0_0 — General purpose digital input/output pin.
I/O
I; PU
PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
I
-
RXD — Receiver data input for USART.
O
-
CLKOUT — Clock output.
O
-
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
I/O
-
SSEL0 — Slave Select for SSP0.
I
-
CLKIN — External clock input.
I/O
I; IA
PIO0_2 — General purpose digital input/output pin.
High-current sink (20 mA) or standard-current sink (4 mA)
programmable; true open-drain for all pin functions. Input
glitch filter (50 ns) capable.
I/O
-
SCL — I2C-bus clock (true open-drain) input/output. Input
glitch filter (50 ns) capable.
O
-
ACMP_O — Analog comparator output.
I
-
TCK/SWCLK — Serial Wire Debug Clock (secondary for
LQFP and HVQFN packages). Input glitch filter (50 ns)
capable. For the WLCSP20 package only, this pin is
configured to the SWCLK function by the boot loader after
reset.
I
-
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. Input
glitch filter (50 ns) capable.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
13 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
LPC11Axx pin description table
Symbol
Pin/Ball
Type Reset Description
state
WLCSP20
PIO0_3/SDA/ACMP_O/ 16 11
SWDIO/CT16B1_CAP0
B1
LQFP48
HVQFN33
[1]
PIO0_4/R/AOUT/
CT16B0_MAT1/MOSI0
TCK/SWCLK/PIO0_5/
R/CT16B0_MAT2/
SCK0
TCK/SWCLK/PIO0_5/
VDDCMP/
CT16B0_MAT2/
SCK0
LPC11AXX
Product data sheet
28 18 A4
29 19 -
-
-
B3
[4][6]
[7]
[9]
[7][8]
I/O
I; IA
PIO0_3 — General purpose digital input/output pin.
High-current sink (20 mA) or standard-current sink (4 mA)
programmable; true open-drain for all pin functions. Input
glitch filter (50 ns) capable.
I/O
-
SDA — I2C-bus data (true open-drain) input/output. Input
glitch filter (50 ns) capable.
O
-
ACMP_O — Analog comparator output.
I/O
-
SWDIO — Serial Wire Debug I/O (secondary for LQFP and
HVQFN packages). Input glitch filter (50 ns) capable. For the
WLCSP20 package only, this pin is configured to the SWDIO
function by the boot loader after reset.
I
-
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. Input
glitch filter (50 ns) capable.
I/O
I; PU
PIO0_4 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
-
-
R — Reserved.
O
-
AOUT — D/A converter output.
O
-
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
I/O
-
MOSI0 — Master Out Slave In for SSP0. Input glitch filter
(10 ns) capable.
I
I; PU
TCK/SWCLK — Test clock TCK for JTAG interface and
primary (default) Serial Wire Debug Clock. Input glitch filter (10
ns) capable.
I/O
-
PIO0_5 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
-
-
R — Reserved.
O
-
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
I/O
-
SCK0 — Serial clock for SSP0. Input glitch filter (10 ns)
capable.
I
I; PU
TCK/SWCLK — Test clock TCK for JTAG interface and
secondary Serial Wire Debug ClocK. Use PIO0_2 for the
default TCK/SWCLK function. Input glitch filter (10 ns)
capable.
I/O
-
PIO0_5 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
VDDCMP — Analog comparator alternate reference voltage.
O
-
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
I/O
-
SCK0 — Serial clock for SSP0. Input glitch filter (10 ns)
capable.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
14 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
LPC11Axx pin description table
Symbol
Pin/Ball
Type Reset Description
state
TDI/PIO0_6/AD0/
CT32B0_MAT3/MISO0
TMS/PIO0_7/AD1/
CT32B1_CAP0/
CT16B0_MAT0
TDO/PIO0_8/AD2/
CT32B1_MAT0/SCK1
TRST/PIO0_9/AD3/
CT32B1_MAT1/
CT16B0_MAT1/CTS
LPC11AXX
Product data sheet
WLCSP20
HVQFN33
LQFP48
[1]
32 21 C3
33 22 C4
34 23 C2
35 24 D4
[9]
[9]
[9]
[9]
I
I; PU
TDI — Test Data In for JTAG interface. Input glitch filter (10 ns)
capable.
I/O
-
PIO0_6 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
AD0 — A/D converter input 0.
O
-
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
I/O
-
MISO0 — Master In Slave Out for SSP0. Input glitch filter
(10 ns) capable.
I
I; PU
TMS — Test Mode Select for JTAG interface. Input glitch filter
(10 ns) capable.
I/O
-
PIO0_7 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
AD1 — A/D converter input 1.
I
-
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. Input
glitch filter (10 ns) capable.
O
-
CT16B0_MAT0 — Match output 2 for 16-bit timer 0.
O
I; PU
TDO — Test Data Out for JTAG interface.
I/O
-
PIO0_8 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
AD2 — A/D converter input 2.
O
-
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
I/O
-
SCK1 — Serial clock for SSP1. Input glitch filter (10 ns)
capable.
I
I; PU
TRST — Test Reset for JTAG interface. Input glitch filter
(10 ns) capable.
I/O
-
PIO0_9 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
AD3 — A/D converter, input 3.
O
-
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
O
-
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
I
-
CTS — Clear To Send input for USART. Input glitch filter
(10 ns) capable.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
15 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
LPC11Axx pin description table
Symbol
Pin/Ball
Type Reset Description
state
SWDIO/PIO0_10/AD4/
CT32B1_MAT2/
CT16B0_MAT2/RTS
PIO0_11/SCLK/
AD5/CT32B1_MAT3/
CT32B0_CAP0
PIO0_12/RXD/
ACMP_O/
CT32B0_MAT0/SCL/
CLKIN
PIO0_13/TXD/
ACMP_I2/
CT32B0_MAT1/SDA
LPC11AXX
Product data sheet
WLCSP20
HVQFN33
LQFP48
[1]
38 25 D3
39 26 D2
46 31 E1
47 32 D1
[9]
[9]
[3]
[9]
I/O
I; PU
SWDIO — Primary (default) Serial Wire Debug I/O for the
LQFP48 and HVQFN33 packages. For the WLCSP20
package, use PIO0_3. Input glitch filter (10 ns) capable.
I/O
-
PIO0_10 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
AD4 — A/D converter, input 4.
O
-
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
O
-
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
O
-
RTS — Request To Send output for USART.
I/O
I; PU
PIO0_11 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I/O
-
SCLK — Serial clock for USART. Input glitch filter (10 ns)
capable.
I
-
AD5 — A/D converter, input 5.
O
-
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
I
-
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. Input
glitch filter (10 ns) capable.
I/O
I; PU
PIO0_12 — General purpose digital input/output pin.
I
-
RXD — Receiver data input for USART. This pin is used for
ISP communication.
O
-
ACMP_O — Analog comparator output.
O
-
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
I/O
-
SCL — I2C-bus clock input/output. This is not an I2C-bus
open-drain pin[10].
I
-
CLKIN — External clock input.
I/O
I; PU
PIO0_13 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
O
-
TXD — Transmitter data output for USART. This pin is used
for ISP communication.
I
-
ACMP_I2 — Analog comparator input 2.
O
-
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
I/O
-
SDA — I2C-bus data input/output. This is not an I2C-bus
open-drain pin[10]. Input glitch filter (10 ns) capable.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
16 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
LPC11Axx pin description table
Symbol
Pin/Ball
Type Reset Description
state
PIO0_14/MISO1/AD6/
CT32B0_CAP1/
CT16B1_MAT1/
VDDCMP
PIO0_14/MISO1/AD6/
CT32B0_CAP1/
CT16B1_MAT1
PIO0_15/TXD/AD7/
CT32B0_CAP2/SDA
PIO0_16/
ATRG0/ACMP_I3/
CT16B0_CAP1/SCL
LPC11AXX
Product data sheet
WLCSP20
HVQFN33
LQFP48
[1]
30 20 -
-
-
B4
41 27 E4
18 13 A2
[7]
[9]
[9]
[9]
I/O
I; PU
PIO0_14 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I/O
-
MISO1 — Master In Slave Out for SSP1. Input glitch filter
(10 ns) capable.
I
-
AD6 — A/D converter, input 6.
I
-
CT32B0_CAP1 — Capture input 1 for 32-bit timer 0. Input
glitch filter (10 ns) capable.
O
-
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
I
-
VDDCMP — Analog comparator alternate reference voltage.
I/O
I; PU
PIO0_14 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I/O
-
MISO1 — Master In Slave Out for SSP1. Input glitch filter
(10 ns) capable.
I
-
AD6 — A/D converter, input 6.
I
-
CT32B0_CAP1 — Capture input 1 for 32-bit timer 0. Input
glitch filter (10 ns) capable.
O
-
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
I/O
I; PU
PIO0_15 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
O
-
TXD — Transmitter data output for USART.
I
-
AD7 — A/D converter, input 7.
I
-
CT32B0_CAP2 — Capture input 2 for 32-bit timer 0. Input
glitch filter (10 ns) capable.
I/O
-
SDA — I2C-bus data input/output. This is not an I2C-bus
open-drain pin[10]. Input glitch filter (10 ns) capable.
I/O
I; PU
PIO0_16 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
ATRG0 — Conversion trigger 0 for ADC or DAC. Input glitch
filter (10 ns) capable.
I
-
ACMP_I3 — Analog comparator input 3.
I
-
CT16B0_CAP1 — Capture input 1 for 16-bit timer 0. Input
glitch filter (10 ns) capable.
I/O
-
SCL — I2C-bus clock input/output. This is not an I2C-bus
open-drain pin[10]. Input glitch filter (10 ns) capable.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
17 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
LPC11Axx pin description table
Symbol
Pin/Ball
Type Reset Description
state
PIO0_17/
ATRG1/ACMP_I4/
CT16B0_CAP2/
CT16B0_MAT0
PIO0_18/R/SSEL0/
CT16B0_CAP0/
CT16B1_CAP1
PIO0_19/CLKIN/
CLKOUT/
MOSI0/CT16B1_MAT0
PIO0_20/R/SCK0/
CT32B1_CAP0/
CT16B1_MAT2
PIO0_21/CTS/
ACMP_O/
CT32B1_CAP1/SCLK
PIO0_22/MISO0/
ACMP_I5/
CT32B1_MAT2/
CT32B1_CAP2
LPC11AXX
Product data sheet
WLCSP20
HVQFN33
LQFP48
[1]
21 14 A3
10 8
14 9
-
-
22 15 -
23 16 -
27 17 -
[9]
[3]
[3]
[3]
[3]
[9]
I/O
I; PU
PIO0_17 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
ATRG1 — Conversion trigger 1 for ADC or DAC. Input glitch
filter (10 ns) capable.
I
-
ACMP_I4 — Analog comparator input 4.
I
-
CT16B0_CAP2 — Capture input 2 for 16-bit timer 0. Input
glitch filter (10 ns) capable.
O
-
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
I/O
I; PU
PIO0_18 — General purpose digital input/output pin.
-
-
R — Reserved.
I/O
-
SSEL0 — Slave Select for SSP0.
I
-
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
I
-
CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.
I/O
I; PU
PIO0_19 — General purpose digital input/output pin.
I
-
CLKIN — External clock input.
O
-
CLKOUT — Clock output.
I/O
-
MOSI0 — Master Out Slave In for SSP0.
O
-
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
I/O
I; PU
PIO0_20 — General purpose digital input/output pin.
-
-
R — Reserved.
I/O
-
SCK0 — Serial clock for SSP0.
I
-
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
O
-
CT16B1_MAT2 — Match output 2 for 16-bit timer 1.
I/O
I; PU
PIO0_21 — General purpose digital input/output pin. If
configured as output, this pin is a high-current source output
driver (20 mA).
I
-
CTS — Clear To Send input for USART.
O
-
ACMP_O — Analog comparator output.
I
-
CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.
I/O
-
SCLK — Serial clock for USART.
I/O
I; PU
PIO0_22 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I/O
-
MISO0 — Master In Slave Out for SSP0. Input glitch filter
(10 ns) capable.
I
-
ACMP_I5 — Analog comparator input 5.
O
-
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
I
-
CT32B1_CAP2 — Capture input 2 for 32-bit timer 1. Input
glitch filter (10 ns) capable.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
18 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
LPC11Axx pin description table
Symbol
Pin/Ball
Type Reset Description
state
PIO0_23/RTS/
ACMP_O/
CT32B0_CAP0/SCLK
PIO0_24/SCL/CLKIN/
CT16B1_CAP0
PIO0_25/SDA/SSEL1/
CT16B1_MAT0
PIO0_26/TXD/MISO1/
CT16B1_CAP1/
CT32B0_CAP2
PIO0_27/MOSI1/
ACMP_I1/
CT32B1_MAT1/
CT16B1_CAP2
PIO0_28/DTR/SSEL1/
CT32B0_CAP0
PIO0_29/DSR/SCK1/
CT32B0_CAP1
LPC11AXX
Product data sheet
WLCSP20
HVQFN33
LQFP48
[1]
45 30 -
9
7
-
17 12 -
1
1
-
43 28 -
2
-
13 -
-
-
[3]
[3]
[3]
[3]
[9]
[3]
[3]
I/O
I; PU
PIO0_23 — General purpose digital input/output pin.
O
-
RTS — Request To Send output for USART.
O
-
ACMP_O — Analog comparator output.
I
-
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
I/O
-
SCLK — Serial clock for USART.
I/O
I; PU
PIO0_24 — General purpose digital input/output pin.
I/O
-
SCL — I2C-bus clock input/output. This is not an I2C-bus
open-drain pin[10].
I
-
CLKIN — External clock input.
I
-
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
I/O
I; PU
PIO0_25 — General purpose digital input/output pin.
I/O
-
SDA — I2C-bus data input/output. This is not an I2C-bus
open-drain pin[10].
I/O
-
SSEL1 — Slave Select for SSP1.
O
-
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
I/O
I; PU
PIO0_26 — General purpose digital input/output pin.
O
-
TXD — Transmitter data output for USART.
I/O
-
MISO1 — Master In Slave Out for SSP1.
I
-
CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.
I
-
CT32B0_CAP2 — Capture input 2 for 32-bit timer 0.
I/O
I; PU
PIO0_27 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I/O
-
MOSI1 — Master Out Slave In for SSP1. Input glitch filter
(10 ns) capable.
I
-
ACMP_I1 — Analog comparator input 1.
O
-
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
I
-
CT16B1_CAP2 — Capture input 2 for 16-bit timer 1. Input
glitch filter (10 ns) capable.
I/O
I; PU
PIO0_28 — General purpose digital input/output pin.
O
-
DTR — Data Terminal Ready output for USART.
I/O
-
SSEL1 — Slave Select for SSP1.
I
-
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
I/O
I; PU
PIO0_29 — General purpose digital input/output pin.
I
-
DSR — Data Set Ready input for USART.
I/O
-
SCK1 — Serial clock for SSP1.
I
-
CT32B0_CAP1 — Capture input 1 for 32-bit timer 0.
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LPC11Axx
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32-bit ARM Cortex-M0 microcontroller
Table 4.
LPC11Axx pin description table
Symbol
Pin/Ball
Type Reset Description
state
PIO0_30/RI/MOSI1/
CT32B0_MAT0/
CT16B0_CAP0
PIO0_31/RI/MOSI1/
CT32B1_MAT0/
CT16B1_CAP1
PIO1_0/DCD/SCK0/
CT32B1_MAT3/
CT16B0_MAT1
PIO1_1/DTR/SSEL0/
CT32B1_MAT3/
CT16B1_MAT0
PIO1_2/DSR/MISO0/
CT16B1_MAT2/
CT16B1_MAT1
PIO1_3/RI/MOSI0/
CT16B1_CAP0
PIO1_4/RXD/SSEL1/
CT32B0_MAT1/
CT32B1_CAP0/
CT16B0_CAP1
LPC11AXX
Product data sheet
40 -
24 -
31 -
36 -
37 -
48 -
19 -
WLCSP20
HVQFN33
LQFP48
[1]
-
-
-
-
-
-
-
[3]
[3]
[3]
[3]
[3]
[3]
[3]
I/O
I; PU
PIO0_30 — General purpose digital input/output pin.
I
-
RI — Ring Indicator input for USART.
I/O
-
MOSI1 — Master Out Slave In for SSP1.
O
-
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
I
-
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
I/O
I; PU
PIO0_31 — General purpose digital input/output pin.
I
-
RI — Ring Indicator input for USART.
I/O
-
MOSI1 — Master Out Slave In for SSP1.
O
-
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
I
-
CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.
I/O
I; PU
PIO1_0 — General purpose digital input/output pin.
I
-
DCD — Data Carrier Detect input for USART.
I/O
-
SCK0 — Serial clock for SSP0.
O
-
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
O
-
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
I/O
I; PU
PIO1_1 — General purpose digital input/output pin.
O
-
DTR — Data Terminal Ready output for USART.
I/O
-
SSEL0 — Slave Select for SSP0.
O
-
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
O
-
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
I/O
I; PU
PIO1_2 — General purpose digital input/output pin.
I
-
DSR — Data Set Ready input for USART.
I/O
-
MISO0 — Master In Slave Out for SSP0.
O
-
CT16B1_MAT2 — Match output 2 for 16-bit timer 1.
O
-
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
I/O
I; PU
PIO1_3 — General purpose digital input/output pin.
I
-
RI — Ring Indicator input for USART.
I/O
-
MOSI0 — Master Out Slave In for SSP0.
I
-
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
I/O
I; PU
PIO1_4 — General purpose digital input/output pin.
I
-
RXD — Receiver data input for USART.
I/O
-
SSEL1 — Slave Select for SSP1.
O
-
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
I
-
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
I
-
CT16B0_CAP1 — Capture input 1 for 16-bit timer 0.
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LPC11Axx
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32-bit ARM Cortex-M0 microcontroller
Table 4.
LPC11Axx pin description table
Symbol
Pin/Ball
Type Reset Description
state
PIO1_5/TXD/SCK1/
CT32B0_MAT2/
CT32B1_CAP1/
CT16B0_CAP2
PIO1_6/RTS/MOSI1/
CT32B0_MAT3/
CT32B1_CAP2/
CT16B0_MAT0
PIO1_7/CTS/MOSI0/
CT32B1_MAT1/
CT16B0_MAT2/
CT16B1_CAP2
PIO1_8/RXD / MISO1/
CT32B1_MAT0/
CT16B1_MAT1
PIO1_9/DCD/R/
CT32B1_MAT2 /
CT16B1_MAT2
20 -
11
-
25 -
26 -
12 -
WLCSP20
HVQFN33
LQFP48
[1]
-
-
-
-
-
[3]
[3]
[3]
[3]
[3]
I/O
I; PU
PIO1_5 — General purpose digital input/output pin.
O
-
TXD — Transmitter data output for USART.
I/O
-
SCK1 — Serial clock for SSP1.
O
-
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
I
-
CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.
I
-
CT16B0_CAP2 — Capture input 2 for 16-bit timer 0.
I/O
I; PU
PIO1_6 — General purpose digital input/output pin.
O
-
RTS — Request To Send output for USART.
I/O
-
MOSI1 — Master Out Slave In for SSP1.
O
-
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
I
-
CT32B1_CAP2 — Capture input 2 for 32-bit timer 1.
O
-
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
I/O
I; PU
PIO1_7 — General purpose digital input/output pin.
I
-
CTS — Clear To Send input for USART.
I/O
-
MOSI0 — Master Out Slave In for SSP0.
O
-
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
O
-
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
I
-
CT16B1_CAP2 — Capture input 2 for 16-bit timer 1.
I/O
I; PU
PIO1_8 — General purpose digital input/output pin.
I
-
RXD — Receiver data input for USART.
I/O
-
MISO1 — Master In Slave Out for SSP1.
O
-
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
O
-
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
I/O
I; PU
PIO1_9 — General purpose digital input/output pin.
I
-
DCD — Data Carrier Detect input for USART.
-
-
R — Reserved.
O
-
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
O
-
CT16B1_MAT2 — Match output 2 for 16-bit timer 1.
-
-
Input to the oscillator circuit and internal clock generator
circuits. Input voltage must not exceed 1.8 V.
XTALIN
6
4
-
[11]
XTALOUT
7
5
-
[11]
-
-
Output from the oscillator amplifier.
VDD(IO)
8
6
E2
[12]
-
-
3.3 V input/output supply voltage.
[13]
LPC11AXX
Product data sheet
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LPC11Axx
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32-bit ARM Cortex-M0 microcontroller
Table 4.
LPC11Axx pin description table
Symbol
Pin/Ball
Type Reset Description
state
LQFP48
HVQFN33
WLCSP20
[1]
VSS(IO)
5
33 E3
[14]
-
-
Ground.
VDD(3V3)
44 29 E2
[12]
-
-
3.3 V supply voltage to the analog blocks, internal regulator,
and internal clock generator circuits. Also used as the ADC
reference voltage.
-
-
Ground.
[13]
42 33 E3
VSS
[14]
[1]
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up resistor (weak PMOS device) enabled; IA = inactive, no
pull-up/down enabled.
[2]
See Figure 32 for the reset configuration.
[3]
5 V tolerant pin providing standard digital I/O functions with configurable modes and configurable hysteresis (Figure 31).
[4]
I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus.
[5]
For the SWD function, a pull-up resistor is recommended for the SWCLK pin (WLCSP20 parts only).
[6]
For the SWD function, a pull-up resistor is recommended for the SWDIO pin (WLCSP20 parts only).
[7]
Not a 5 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes,
configurable hysteresis, and analog I/O. When configured as an analog I/O, the digital section of the pin is disabled (Figure 31).
[8]
If this pin is configured for its VDDCMP function, it cannot be used for SWCLK when the part is on the board. The bypass filter of the
power supply filters out the SWCLK clock input signal.
[9]
5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O. When
configured as an analog I/O, digital section of the pin is disabled, and the pin is not 5 V tolerant (Figure 31).
[10] I2C-bus pins are standard digital I/O pins and have limited performance and electrical characteristics compared to the full I2C-bus
specification. Pins can be configured with an on-chip pull-up resistor (pMOS device) and with open-drain mode. In this mode, typical bit
rates of up to 100 kbit/s with 20 pF load are supported if the internal pull-ups are enabled. Higher bit rates can be achieved with an
external resistor.
[11] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. See Section 12.3 if an external clock is
connected to the XTALIN pin.
[12] If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the power supply pins are filtered for noise with respect to their
corresponding grounds VSS and VSS(IO) (LQFP48 package). Using separate filtered supplies reduces the noise to the analog blocks (see
also Section 12.1).
[13] If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference between both supplies is smaller than or equal
to 0.5 V.
[14] Thermal pad (HVQFN33 pin package). Connect to ground.
LPC11AXX
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LPC11Axx
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32-bit ARM Cortex-M0 microcontroller
7. Functional description
7.1 ARM Cortex-M0 processor
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
7.2 On-chip flash program memory
The LPC11Axx contain up to 32 kB of on-chip flash program memory.
7.3 On-chip EEPROM data memory
The LPC11Axx contain up to 4 kB of on-chip EEPROM data memory.
Remark: The top 64 bytes of the 4 kB EEPROM memory are reserved and cannot be
written to. The entire EEPROM is writable for smaller EEPROM sizes.
7.4 On-chip SRAM
The LPC11Axx contain a total of 8 kB, 4 kB, or 2 kB on-chip static RAM data memory.
7.5 On-chip ROM
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (API):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming
• Power profiles for configuring power consumption and PLL settings
• 32-bit integer division routines
• I2C-bus driver routines
7.6 Memory map
The LPC11Axx incorporates several distinct memory regions, shown in the following
figures. Figure 5 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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Product data sheet
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32-bit ARM Cortex-M0 microcontroller
LPC11Axx
4 GB
0xFFFF FFFF
reserved
0xE010 0000
private peripheral bus
0xE000 0000
reserved
APB peripherals
0x5004 0000
GPIO
25 - 31 reserved
0x5000 0000
24
GPIO GROUP1 INT
23
GPIO GROUP0 INT
22
SSP1
0x4008 0000
21
reserved
0x4000 0000
20
reserved
19
GPIO interrupts
18
system control
17
IOCONFIG
16
15
SSP0
flash/EEPROM controller
14
reserved
reserved
APB peripherals
1 GB
reserved
0x2000 0000
0.5 GB
reserved
0x1FFF 4000
16 kB boot ROM
11 - 13 reserved
0x1FFF 0000
6 kB SRAM (LPC11A1x/201)
4 kB SRAM (LPC11Ax/101, LPC11A02))
2 kB SRAM (LPC11Ax/001)
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
0x4002 C000
0x1000 2000
8
reserved
0x4002 0000
0x1000 1800
7
ADC
0x4001 C000
0x1000 1000
6
32-bit counter/timer 1
0x4001 8000
0x1000 0800
5
32-bit counter/timer 0
0x4001 4000
4
16-bit counter/timer 1
0x4001 0000
3
16-bit counter/timer 0
0x4000 C000
2
USART
0x4000 8000
1
0
WWDT
0x4000 4000
I2C-bus
0x4000 0000
0x0000 6000
0x4002 8000
0x4002 4000
0x0000 4000
16 kB on-chip flash (LPC11A12, LPC11A02)
0 GB
0x4005 0000
DAC
0x0000 8000
8 kB on-chip flash (LPC11A11)
0x4005 4000
9
reserved
24 kB on-chip flash (LPC11A13)
0x4005 8000
analog comparator
0x1000 0000
32 kB on-chip flash (LPC11A14, LPC11A04)
0x4005 C000
10
reserved
8 kB SRAM (LPC11A1x/301, LPC11A04)
0x4008 0000
0x0000 2000
0x0000 00C0
active interrupt vectors
0x0000 0000
0x0000 0000
002aaf429
Fig 5.
LPC11Axx memory map
7.7 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.7.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC11Axx, the NVIC supports 32 vectored interrupts including up to 8 inputs to
the start logic from the individual GPIO pins.
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• Four programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation.
7.7.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Up to eight GPIO pins, regardless of the selected function, can be programmed to
generate an interrupt on a level, or rising edge or falling edge, or both. The interrupt
generating GPIOs can be selected from the GPIO pins with a configurable input glitch
filter.
7.8 IOCON block
The IOCON block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Up to 16 pins can be configured with a digital input glitch filter for removing voltage
glitches with widths of 10 ns or less (see Table 3 and Table 4), two pins (PIO0_2 and
PIO0_3) can be configured with a 50 ns digital input glitch filter.
7.9 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC11Axx use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
• An entire port value can be written in one instruction.
Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
7.9.1 Features
• Bit level port registers allow a single instruction to set and clear any number of bits in
one write operation.
• Direction control of individual bits.
• All I/O default to inputs with internal pull-up resistors enabled after reset - except for
the I2C-bus true open-drain pins PIO0_2 and PIO0_3.
• Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed
through the IOCON block for each GPIO pin (see Figure 31 and Figure 32 for
functional diagrams).
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• Control of the digital output slew rate allowing to switch more outputs simultaneously
without degrading the power/ground distribution of the device.
7.10 USART
The LPC11Axx contains one USART.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The USART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.10.1 Features
•
•
•
•
•
Maximum USART data bit rate of 3.125 MBit/s.
•
•
•
•
FIFO control mechanism that enables software flow control implementation.
16-byte Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Support for RS-485/9-bit mode.
Supports a full modem control handshake interface.
Support for synchronous mode.
7.11 SSP serial I/O controller
The LPC11Axx contain two SSP controllers.
The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SSP supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
7.11.1 Features
• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SPI mode)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
•
•
•
•
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
7.12 I2C-bus serial I/O controller
The LPC11Axx contains one I2C-bus controller.
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The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
Remark: On the WLCSP package, the bootloader configures the open-drain pins
(PIO0_2 and PIO0_3) for the Serial Wire Debug (SWD) function.
7.12.1 Features
• The I2C-interface is a standard I2C-bus compliant interface with open-drain pins
(PIO0_2 and PIO0_3). The I2C-bus interface also supports Fast-mode Plus with bit
rates up to 1 Mbit/s. For the I2C-bus specification, see UM10204.
• The true open-drain pins PIO0_2 and PIO0_3 can be configured with a 50 ns digital
input glitch filter.
• If the true open-drain pins are used for other purposes, a limited-performance I2C-bus
interface can be configured from a choice of six GPIO pins configured in open-drain
mode and with a pull-up resistor. In this mode, typical bit rates of up to 100 kbit/s with
20 pF load are supported if the internal pull-ups are enabled. Higher bit rates can be
achieved with an external resistor.
• Fail-safe operation: When the power to an I2C-bus device is switched off, the SDA
and SCL pins connected to the I2C-bus are floating and do not disturb the bus.
•
•
•
•
•
•
Easy to configure as master, slave, or master/slave.
ROM-based I2C-bus driver routines to easily create applications.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.13 Configurable analog/mixed-signal subsystems
Multiple analog/mixed-signal subsystems can be configured by software from
interconnected digital and analog peripherals. See Figure 6.
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CONFIGURABLE ANALOG/MIXED-SIGNAL SUBSYSTEM
AD[7:0]
10-bit ADC
ATRG[1:0]
TRIG
TEMPERATURE
SENSOR
32-bit TIMER
CAP
0.9 V VOLTAGE
REFERENCE
MAT
16-bit TIMER
CAP
VOLTAGE
DIVIDER REF
VDD(3V3)
VDDCMP
TRIG
10-bit
DAC
AOUT
MAT
ANALOG
COMPARATOR
ACMP_I[5:1]
ACMP_O
EDGE DETECT
INTERRUPT
CONTROLLER
ARM
CORTEX-M0
analog
digital
SIGNAL LEGEND:
aaa-003042
Fig 6.
Configurable analog/mixed signal subsystem
7.14 10-bit ADC
The LPC11Axx contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
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TEMPERATURE
SENSOR
to
comparator
10-bit ADC
INPUT
MUX
SENSOR
AD7
IOCONFIG
to
comparator
INTERNAL
VOLTAGE REFERENCE
AD6
ADC
IOCONFIG
AD5
IOCONFIG
AD0
IOCONFIG
Fig 7.
ADC control
register
aaa-003043
ADC block diagram
7.14.1 Features
•
•
•
•
•
•
•
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to VDD(3V3).
10-bit conversion time 2.44 s (up to 400 kSamples/s).
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pins ATRG0 or ATRG1, timer match signal,
or comparator output. (Input signals must be held for a minimum of three system clock
periods). Also see Section 12.2.
• Individual result registers for each ADC channel to reduce interrupt overhead.
7.15 Internal voltage reference
The internal voltage reference is an accurate 0.9 V and is the output of a low voltage band
gap circuit. A typical value at Tamb = 25 C is 0.903 V and varies typically only 3 mV over
the 0 C to 85 C temperature range (see Table 21 and Figure 27). The internal voltage
reference can be used in the following applications:
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• When the supply voltage VDD(3V3) is known accurately, the internal voltage reference
can be used to reduce the offset error EO of the ADC code output. The ADC error
correction then increases the accuracy of temperature sensor voltage output
measurements.
• When the ADC is accurately calibrated, the internal voltage reference can be used to
measure the power supply voltage. This requires calibration by recording the ADC
code of the internal voltage reference at different power supply levels yielding a
different ADC code value for each supply voltage level. In a particular application, the
internal voltage reference can be measured and the actual power supply voltage can
be determined from the stored calibration values. The calibration values can be stored
in the EEPROM for easy access.
After power-up and after switching the input channels of the ADC or the comparator, the
internal voltage reference must be allowed to settle to its stable value before it can be
used as an ADC reference voltage input. Settling times are given in Table 21.
For an accurate measurement of the internal voltage reference by the ADC, the ADC must
be configured in single-channel burst mode. The last value of a nine-conversion (or more)
burst provides an accurate result.
7.16 Temperature sensor
The temperature sensor transducer uses an intrinsic pn-junction diode reference and
outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage
varies inversely with device temperature with an absolute accuracy of better than 3 C
over the full temperature range (40 C to +85 C). The temperature sensor is only
approximately linear with a slight curvature. The output voltage is measured over different
ranges of temperatures and fit with linear-least-square lines. See Table 23 and Figure 28.
For a voltage to temperature conversion, the temperature for a given voltage is calculated
using the parameters of the linear-least-square line (see Table 23).
After power-up and after switching the input channels of the ADC or the comparator, the
temperature sensor output must be allowed to settle to its stable value before it can be
used as an accurate ADC input. Settling times are given in Table 22.
For an accurate measurement of the temperature sensor by the ADC, the ADC must be
configured in single-channel burst mode. The last value of a nine-conversion (or more)
burst provides an accurate result.
7.17 10-bit DAC
The DAC allows generation of a variable, rail-to-rail analog output.
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APB REGISTERS
INPUT
REGISTER
10
10
DAC
AOUT
CT32B1_MAT0
CT32B1_MAT1
CT16B1_MAT0
CT16B1_MAT1
ATRG0
ATRG1
analog comparator output
D/A
CONVERTER
CONTROL
AND DATA
REGISTER
Fig 8.
aaa-003044
DAC block diagram
7.17.1 Features
•
•
•
•
•
•
10-bit DAC.
Resistor string architecture.
Buffered output.
Power-down mode.
Conversion speed controlled via a programmable bias current.
Optional output update modes:
– write operations to the DAC register.
– a transition of pins ATRG0 or ATRG1. Input signals must be held for a minimum of
three system clock periods.
– a timer match signal.
– a comparator output signal held for a minimum of two system clock periods.
• Holds output value during Sleep mode if the DAC is not powered down.
7.18 Analog comparator
The analog comparator with selectable hysteresis can compare voltage levels on external
pins and internal voltages. See Table 24.
After power-up and after switching the input channels of the comparator, the output of the
voltage ladder must be allowed to settle to its stable value before it can be used as a
comparator reference input. Settling times are given in Table 25.
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VDD
COMPARATOR ANALOG BLOCK
COMPARATOR DIGITAL BLOCK
VDDCMP
to ADC and DAC
5
32
comparator
level
sync
edge detect
comparator
edge
internal
voltage
reference
temperature
sensor
ACMPI[5:1]
5
aaa-003045
Fig 9.
Comparator block diagram
7.18.1 Features
• Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input
hysteresis.
• Five selectable external voltages; fully configurable on either positive or negative
input channel.
• Internal voltage reference from band gap and temperature sensor selectable on either
positive or negative input channel.
• 32-stage voltage ladder with the internal reference voltage selectable on either the
positive or the negative input channel. See Table 24 to Table 26.
• Voltage ladder source voltage is selectable from an external pin or the main 3.3 V
supply voltage rail.
• Voltage ladder can be separately powered down for applications only requiring the
comparator function.
• Interrupt output is connected to NVIC.
• Comparator level output is connected to output pin ACMP_O.
• Comparator output is internally connected to the ADC and DAC and can be used to
trigger a conversion.
• The comparator output is also connected internally to capture channel 3 on each of
the 32-bit and 16-bit counter/timers.
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7.19 General purpose external event counter/timers
The LPC11Axx includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes four capture inputs to trap the timer
value when an input signal transitions, optionally generating an interrupt.
7.19.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• Four capture channels per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt. Up to three
capture channels are pinned out. One channel is internally connected to the
comparator output ACMP_O.
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
7.20 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.21 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.21.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect feed sequence causes reset or interrupt if enabled.
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• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) source can be selected from the internal RC oscillator
(IRC), or the dedicated watchdog oscillator (WDOsc). This gives a wide range of
potential timing choices of watchdog operation under different power conditions.
7.22 Clocking and power control
7.22.1 Crystal and internal oscillators
The LPC11Axx include four independent oscillators.
1. The crystal oscillator (SysOsc) operating at frequencies between 1 MHz and 25 MHz.
2. The internal RC Oscillator (IRC) with a fixed frequency of 12 MHz, trimmed to 1%
accuracy.
3. The internal low-power, Low-Frequency Oscillator (LFOsc) with a programmable
nominal frequency between 9.4 kHz and 2.3 MHz with 40% accuracy.
4. The dedicated Watchdog Oscillator (WDOsc) with a programmable nominal
frequency between 9.4 kHz and 2.3 MHz with 40% accuracy.
Each oscillator, except the WDOsc, can be used for more than one purpose as required in
a particular application.
Following reset, the LPC11Axx will operate from the IRC until switched by software. This
allows systems to operate without any external crystal and the bootloader code to operate
at a known frequency.
See Figure 10 for an overview of the LPC11Axx clock generation.
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system
SYSTEM CLOCK
DIVIDER
system clock
18
memories
and peripherals
SYSCLKCTRL[1:18]
SSP0 PERIPHERAL
CLOCK DIVIDER
IRC
SSP0
main clock
USART PERIPHERAL
CLOCK DIVIDER
LFOsc
SSP1 PERIPHERAL
CLOCK DIVIDER
MAINCLKSEL
(main clock select)
IRC
SysOsc
CLKIN
IRC
SysOsc
LFOsc
SYSTEM PLL
SYSPLLCLKSEL
(system PLL clock select)
CLKOUT PIN CLOCK
DIVIDER
USART
SSP1
CLKOUT pin
CLKOUTUEN
(CLKOUT update enable)
IRC
WWDT CLOCK
DIVIDER
WWDT
WDOsc
WDCLKSEL
002aaf430
Fig 10. LPC11Axx clock generation block diagram
7.22.1.1
Internal RC Oscillator (IRC)
The IRC may be used as the clock source for the WWDT, and/or as the clock that drives
the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is
trimmed to 1 % accuracy over the entire voltage and temperature range.
The IRC can be used as a clock source for the CPU with or without using the PLL. The
IRC frequency can be boosted to a higher frequency, up to the maximum CPU operating
frequency, by the system PLL.
Upon power-up or any chip reset, the LPC11Axx use the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.22.1.2
Crystal Oscillator (SysOsc)
The crystal oscillator can be used as the clock source for the CPU, with or without using
the PLL.
The SysOsc operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted
to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.
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7.22.1.3
Internal Low-Frequency Oscillator (LFOsc) and Watchdog Oscillator (WDOsc)
The LFOsc and the WDOsc are identical internal oscillators. The nominal frequency is
programmable between 9.4 kHz and 2.3 MHz. The frequency spread over silicon process
variations is 40%.
The WDOsc is a dedicated oscillator for the windowed WWDT.
The LFOsc can be used as a clock source that directly drives the CPU or the CLKOUT
pin.
7.22.2 Clock input
A 3.3 V external clock source (25 MHz typical) can be supplied on the selected CLKIN pin
or a 1.8 V external clock source can be supplied on the XTALIN pin (see Section 12.3).
7.22.3 System PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the
minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.
The PLL is turned off and bypassed following a chip reset and may be enabled by
software. The program must configure and activate the PLL, wait for the PLL to lock, and
then connect to the PLL as a clock source. The PLL settling time is 100 s.
7.22.4 Clock output
The LPC11Axx features a clock output function that routes the IRC, the SysOsc, the
LFOsc, or the main clock to an output pin.
7.22.5 Wake-up process
The LPC11Axx begin operation at power-up by using the IRC as the clock source. This
allows chip operation to resume quickly. If the SysOsc, the external clock source, or the
PLL is needed by the application, software will need to enable these features and wait for
them to stabilize before they are used as a clock source.
7.22.6 Power control
The LPC11Axx supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also
be controlled as needed by changing clock sources, reconfiguring PLL values, and/or
altering the CPU clock divider value. This allows a trade-off of power versus processing
speed based on application requirements. In addition, a register is provided for shutting
down the clocks to individual on-chip peripherals, allowing fine tuning of power
consumption by eliminating all dynamic power use in any peripherals that are not required
for the application. Selected peripherals have their own clock divider which provides even
better power control.
7.22.6.1
Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
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In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.22.6.2
Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC11Axx for one of the following power modes:
• Default mode corresponding to power configuration after reset.
• CPU performance mode corresponding to optimized processing capability.
• Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
7.23 System control
7.23.1 UnderVoltage LockOut (UVLO) protection
The BOD and POR circuits remain enabled at all times to provide UVLO protection from
an unexpected power supply droop below a typical threshold level of 2.4 V (see also the
LPC11Axx user manual). UVLO protection means that the LPC11Axx is held in reset
whenever the supply voltage falls below 2.4 V.
See also Section 10.1 “Power supply fluctuations”, Section 12.7 “UVLO protection and
reset timer circuit”, and Section 12.8 “Guidelines for selecting a power supply filter for
UVLO protection”.
7.23.2 Reset
Reset has several sources on the LPC11Axx: the RESET pin, the Watchdog reset,
power-on reset (POR), the ARM SYSRESETREQ software request, and the Brown-Out
Detection (BOD) circuit. After the BOD and the POR resets are released, the internal reset
timer counts for 100 μs until the internal reset is removed.
Assertion of chip reset by any source (after the operating voltage attains a usable level)
starts the IRC and initializes the flash memory controller.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Writing to a special function register allows the software to reset the following peripherals:
the I2C-bus interface, the USART, both SSP controllers, the four counter/timers, the
comparator, the ADC, and the DAC.
The RESET pin is a Schmitt trigger input pin and uses a special pad. See Figure 32.
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7.23.3 Brown-out detection
The LPC11Axx include two programmable levels for monitoring the voltage on the
VDD(3V3) pin. If this voltage falls below the selected level, the BOD asserts an interrupt
signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable
Register in the NVIC in order to cause a CPU interrupt; alternatively, software can monitor
the signal by reading a dedicated status register. In addition, the BOD circuit supports one
hardware controlled voltage level for triggering a chip reset.
7.23.4 Code security (Code Read Protection - CRP)
This feature of the LPC11Axx allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System-Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC11Axx user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the USART.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC11Axx user manual.
7.23.5 APB interface
The APB peripherals are located on one APB bus.
7.23.6 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
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7.23.7 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
7.24 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. JTAG and Serial Wire Debug
(SWD) with four breakpoints and two watchpoints are supported.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11Axx is in reset.
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.
2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode and release the RESET pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
On the WLCSP package, the TCK signal is shared with the VDDCMP input on pin
PIO0_5. To perform a boundary scan on a blank device, make sure that the PIO0_5 pin is
not filtered on the board. The bypass filter usually added to the comparator voltage
reference input (VDDCMP) filters out the SWCLK/TCK input signal.
For SWD debug, an alternative TCK/SWCLK clock pin is available on pin PIO0_2. This is
the default function after booting for the WLCSP package.
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8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Min
Max
Unit
supply voltage (3.3 V)
[2]
0.5
4.6
V
VDD(IO)
input/output supply voltage
[2]
0.5
4.6
V
VI
input voltage
[3][4]
0.5
+5.5
V
on pins PIO0_2
and PIO0_3
[5]
0.5
+5.5
V
3 V tolerant I/O
pins without
over-voltage
protection
[6]
0.5
+3.6
V
0.5 V
4.6
V
0.5
+2.5
V
VDD(3V3)
VIA
Parameter
Conditions
5 V tolerant I/O
pins; only valid
when the VDD(IO)
supply voltage is
present
[7][8]
analog input voltage
[9]
Vi(xtal)
crystal input voltage
[2]
IDD
supply current
per supply pin
-
100
mA
ISS
ground current
per ground pin
-
100
mA
Ilatch
I/O latch-up current
(0.5VDD(IO)) < VI <
(1.5VDD(IO));
-
100
mA
65
+150
C
-
150
C
-
1.5
W
Tj < 125 C
[10]
Tstg
storage temperature
Tj(max)
maximum junction temperature
Ptot(pack)
total power dissipation (per package)
based on package
heat transfer, not
device power
consumption
Vesd
electrostatic discharge voltage
human body
model; all pins
[11]
6.5
+6.5
kV
Vtrig
trigger voltage
for LVTSCR based
ESD pin protection;
[12]
8.2
-
V
8.5
-
V
1 ns to 10 ns rise
time
10 ns rise time
[1]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2]
Maximum/minimum voltage above the maximum operating voltage (see Table 6) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3]
Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_2 and PIO0_3 and except the 3 V tolerant pins PIO0_4 and
PIO0_14 (LQFP and HVQFN packages) or PIO0_5 (WLCSP package).
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[4]
Including the voltage on outputs in 3-state mode.
[5]
VDD(IO) present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD(IO) is powered down.
[6]
Applies to 3 V tolerant pins PIO0_4 and PIO0_14 (LQFP and HVQFN packages) or PIO0_5 (WLCSP package).
[7]
An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated
exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the
ADC inputs for a long time affects the reliability of the device and reduces its lifetime.
[8]
If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below
VDD without affecting the hysteresis range of the comparator function.
[9]
It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.
[10] Dependent on package type.
[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[12] Not characterized.
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9. Static characteristics
Table 6.
Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Min
Typ[1]
Max
Unit
supply voltage (3.3 V)
2.6
3.3
3.6
V
VDD(IO)
input/output supply
voltage
2.6
3.3
3.6
V
IDD
supply current
Symbol
Parameter
VDD(3V3)
Conditions
Active mode; code
while(1){}
executed from flash;
VDD(3V3) = VDD(IO) = 3.3 V;
low-current mode (see
Section 7.22.6.2)
system clock = 12 MHz;
all peripherals disabled
[2][4][5]
-
3
-
mA
system clock = 48 MHz;
all peripherals disabled
[2][6][5]
-
8
-
mA
all peripherals disabled;
12 MHz
[2][4][5]
-
2
-
mA
all peripherals disabled;
48 MHz
[2][4][5]
-
5
-
mA
Sleep mode;
system clock = 12 MHz;
VDD(3V3) = VDD(IO) = 3.3 V;
low-current mode (see
Section 7.22.6.2)
Standard port pins, RESET
IIL
LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
-
0.5
1000
nA
IIH
HIGH-level input
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
-
0.5
1000
nA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD(IO);
on-chip pull-up/down
resistors disabled
-
0.5
1000
nA
VI
input voltage
pin configured to provide
a digital function
0
-
5.0
V
[7][8]
5 V tolerant pins
3 V tolerant pins:
PIO0_4 and PIO0_14
(LQFP and HVQFN
packages) or PIO0_5
(HVQFN package)
[7][8]
VO
output voltage
0
-
VDD(IO)
V
VIH
HIGH-level input
voltage
0.7VDD(IO)
-
-
V
VIL
LOW-level input voltage
-
-
0.3VDD(IO)
V
Vhys
hysteresis voltage
0.4
-
-
V
LPC11AXX
Product data sheet
output active
VDD(IO)
3.0 V VDD(IO) 3.6 V
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 6.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
VOH
HIGH-level output
voltage
2.6 V VDD(IO) 3.6 V;
IOH = 4 mA
VOL
LOW-level output
voltage
IOH
IOL
Typ[1]
Max
Unit
0.85VDD(IO) -
-
V
2.6 V VDD(IO) 3.6 V;
IOL = 4 mA
-
-
0.15VDD(IO) V
HIGH-level output
current
VOH = VDD(IO) 0.4 V;
4
-
-
mA
LOW-level output
current
VOL = 0.4 V
4
-
-
mA
2.6 V VDD(IO) 3.6 V
2.6 V VDD(IO) 3.6 V
IOHS
HIGH-level short-circuit VOH = 0 V
output current
[9]
-
-
45
mA
IOLS
LOW-level short-circuit
output current
VOL = VDD(IO)
[9]
-
-
50
mA
Ipd
pull-down current
VI = 5 V
10
50
150
A
Ipu
pull-up current
VI = 0 V;
15
50
85
A
0
0
0
A
[10]
2.6 V VDD(IO) 3.6 V
VDD(IO) < VI < 5 V
High-drive output pin (PIO0_21)
IIL
LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
-
0.5
10
nA
IIH
HIGH-level input
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
-
0.5
10
nA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD(IO);
on-chip pull-up/down
resistors disabled
-
0.5
10
nA
VI
input voltage
pin configured to provide
a digital function
0
-
5.0
V
VO
output voltage
output active
0
-
VDD(IO)
V
VIH
HIGH-level input
voltage
0.7VDD(IO)
-
-
V
VIL
LOW-level input voltage
-
-
0.3VDD(IO)
V
Vhys
hysteresis voltage
VOH
HIGH-level output
voltage
[7][8]
0.4
-
-
V
2.6 V VDD(IO) 3.6 V;
IOH = 20 mA
VDD(IO)
0.4
-
-
V
2.6 V VDD(IO) 2.5 V;
IOH = 12 mA
VDD(IO)
0.4
-
-
V
VOL
LOW-level output
voltage
2.6 V VDD(IO) 3.6 V;
IOL = 4 mA
-
-
0.4
V
IOH
HIGH-level output
current
VOH = VDD(IO) 0.4 V;
20
-
-
mA
LOW-level output
current
VOL = 0.4 V
4
-
-
mA
IOL
LPC11AXX
Product data sheet
2.6 V VDD(IO) 3.6 V
2.6 V VDD(IO) 3.6 V
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 6.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
-
-
160
mA
-
-
50
mA
IOHS
HIGH-level short-circuit VOH = 0 V
output current
[9]
IOLS
LOW-level short-circuit
output current
VOL = VDD(IO)
[9]
Ipd
pull-down current
VI = 5 V
10
50
150
A
Ipu
pull-up current
VI = 0 V
15
50
85
A
0
0
0
A
2.6 V VDD(IO) 3.6 V
VDD(IO) < VI < 5 V
I2C-bus
pins (PIO0_2 and PIO0_3)
VIH
HIGH-level input
voltage
0.7VDD(IO)
-
-
V
VIL
LOW-level input voltage
-
-
0.3VDD(IO)
V
Vhys
hysteresis voltage
-
0.05VDD(IO) -
V
4
-
-
mA
20
-
-
mA
-
2
4
A
-
10
22
A
I2C-bus
IOL
LOW-level output
current
VOL = 0.4 V;
pins
configured as standard
mode pins
IOL
LOW-level output
current
VOL = 0.4 V; I2C-bus pins
configured as high-current
sink pins
2.6 V VDD(IO) 3.6 V
2.6 V VDD(IO) 3.6 V
input leakage current
ILI
VI = VDD(IO)
VI = 5 V
[11]
Oscillator pins
Vi(xtal)
crystal input voltage
0.5
1.8
1.95
V
Vo(xtal)
crystal output voltage
0.5
1.8
1.95
V
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2]
Tamb = 25 C.
[3]
IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4]
IRC enabled; SysOsc disabled; system PLL disabled.
[5]
All digital peripherals disabled in the SYSCLKCTRL register except ROM, RAM, and flash. Peripheral clocks to USART and SSP0/1
disabled in system configuration block. Analog peripherals disabled in the PDRUNCFG register except flash memory.
[6]
IRC disabled; SysOsc enabled; system PLL enabled.
[7]
Including voltage on outputs in 3-state mode.
[8]
All supply voltages must be present.
[9]
Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[10] Does not apply to 3 V tolerant pins PIO0_4 and PIO0_14 (LQFP and HVQFN packages) or PIO0_5 (HVQFN package).
[11] To VSS.
LPC11AXX
Product data sheet
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
9.1 Power consumption
Power measurements in Active and Sleep modes were performed under the following
conditions (see LPC11Axx user manual):
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIOnDIR registers.
• Write 0 to all GPIO DIR registers to drive the outputs LOW.
002aah184
8
IDD
(mA)
48 MHz(2)
6.4
36 MHz(2)
4.8
24 MHz(2)
3.2
12 MHz(1)
1.6
0
-40
-15
10
35
60
temperature (°C)
85
Conditions: VDD(3V3) = 3.3 V; active mode entered executing code while(1){} from flash; all
peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; all analog
peripherals disabled in the PDRUNCFG register; low-current mode (see Section 7.22.6.2).
(1) SysOsc and system PLL disabled; IRC enabled.
(2) SysOsc and system PLL enabled; IRC disabled.
Fig 11. Active mode: Typical supply current IDD versus temperature for different system
clock frequencies (all peripherals disabled)
LPC11AXX
Product data sheet
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
002aah185
8
IDD
(mA)
48 MHz(2)
6.4
36 MHz(2)
4.8
24 MHz(2)
3.2
12 MHz(1)
1.6
0
2.7
3
3.3
3.6
VDD(3V3) (V)
Conditions: Tamb = 25 °C; active mode entered executing code while(1){} from flash; all peripherals
disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; all analog peripherals
disabled in the PDRUNCFG register; low-current mode (see Section 7.22.6.2).
(1) SysOsc and system PLL disabled; IRC enabled.
(2) SysOsc and system PLL enabled; IRC disabled.
Fig 12. Active mode: Typical supply current IDD versus core voltage VDD(3V3) for different
system clock frequencies (all peripherals disabled)
002aah186
8
IDD
(mA)
6.4
48 MHz(2)
4.8
36 MHz(2)
3.2
24 MHz(2)
12 MHz(1)
1.6
0
-40
-15
10
35
60
temperature (°C)
85
Conditions: VDD(3V3) = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register and PDRUNCFG register; all peripheral clocks disabled; BOD
disabled; low-current mode (see Section 7.22.6.2).
(1) SysOsc and system PLL disabled; IRC enabled.
(2) SysOsc and system PLL enabled; IRC disabled.
Fig 13. Sleep mode: Typical supply current IDDversus temperature for different system
clock frequencies (all peripherals disabled)
LPC11AXX
Product data sheet
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
9.2 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Measured on a typical sample at Tamb = 25 C.
Table 7.
Power consumption for individual analog and digital blocks
Peripheral
Typical supply
current in mA
12 MHz[1]
Average A/MHz
BOD
0.05
-
BOD, comparator
0.14
-
Analog peripherals
BOD, comparator, ADC, DAC, temperature sensor
0.40
-
DAC
0.26
-
ADC
0.01
-
Temperature sensor, ADC
0.01
-
USART
0.15
12
I2C
0.02
2
16-bit counter/timer 0/1
0.02
2
32-bit counter/timer 0/1
0.02
2
WWDT
0.02
2
Digital peripherals
[1]
IRC on; PLL off.
9.3 Electrical pin characteristics
002aae990
3.6
VOH
(V)
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
10
20
30
40
50
60
IOH (mA)
Conditions: VDD(IO) = 3.3 V; on pin PIO0_21.
Fig 14. High-current source output driver: Typical HIGH-level output voltage VOH versus
HIGH-level output current IOH
LPC11AXX
Product data sheet
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
002aaf019
60
T = 85 °C
25 °C
−40 °C
IOL
(mA)
40
20
0
0
0.2
0.4
0.6
VOL (V)
Conditions: VDD(IO) = 3.3 V; on pins PIO0_2 and PIO0_3.
Fig 15. High-current sink pins: Typical LOW-level output current IOL versus LOW-level
output voltage VOL
002aae991
15
IOL
(mA)
T = 85 °C
25 °C
−40 °C
10
5
0
0
0.2
0.4
0.6
VOL (V)
Conditions: VDD(IO) = 3.3 V; standard port pins and PIO0_21.
Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL
LPC11AXX
Product data sheet
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
002aae992
3.6
VOH
(V)
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
8
16
24
IOH (mA)
Conditions: VDD(IO) = 3.3 V; standard port pins.
Fig 17. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
002aae988
10
Ipu
(μA)
−10
−30
T = 85 °C
25 °C
−40 °C
−50
−70
0
1
2
3
4
5
VI (V)
Conditions: VDD(IO) = 3.3 V; standard port pins.
Fig 18. Typical pull-up current Ipu versus input voltage VI
LPC11AXX
Product data sheet
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
002aae989
80
T = 85 °C
25 °C
−40 °C
Ipd
(μA)
60
40
20
0
0
1
2
3
4
5
VI (V)
Conditions: VDD(IO) = 3.3 V; standard port pins.
Fig 19. Typical pull-down current Ipd versus input voltage VI
LPC11AXX
Product data sheet
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
10. Dynamic characteristics
10.1 Power supply fluctuations
If the input voltage (VDD(3V3)) to the internal regulator fluctuates, the LPC11Axx is held in
reset during a brown-out condition as long as the UVLO circuit is operating. The settling
times of the BOD and POR circuits, which constitute the UVLO, determine the minimum
time the supply level must remain in the shallow or deep brown-out condition to ensure
that the internal reset is asserted properly.
See also Section 7.23.1, Section 12.7, and Section 12.8.
Table 8.
UVLO circuits settling characteristics
Symbol Parameter
ts
settling time
Conditions
Min
Typ
Max Unit
power droop:
5
-
-
s
12
-
-
s
from active level to shallow
brown-out level
(0.9 V VDD(3V3) 2.4 V)
from active level to deep brown-out
level (0 < VDD(3V3) < 0.9 V)
supply
voltage
VDD(3V3)
cold
start-up
brown-out
shallow
brown-out
deep
External
power supply
BOD trip point
(typical)
2.4 V
> 5 μs
POR trip point
(typical)
0.9 V
0V
> 12 μs
internal reset
time
002aah326
Fig 20. UVLO timing
10.2 Flash/EEPROM memory
Table 9.
Flash characteristics
Tamb = 40 C to +85 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as
specified below.
Symbol
Nendu
LPC11AXX
Product data sheet
Parameter
Conditions
[2][1]
endurance
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
Min
Typ
Max
Unit
10000
100000
-
cycles
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 9.
Flash characteristics
Tamb = 40 C to +85 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as
specified below.
Symbol
tret
Parameter
Conditions
retention time
ter
erase time
tprog
programming
time
Min
Typ
Max
Unit
powered
[2]
10
20
-
years
unpowered
[2]
20
40
-
years
sector or multiple
consecutive
sectors
[2]
95
100
105
ms
0.95
1
1.05
ms
[2][3]
[1]
Number of program/erase cycles.
[2]
Min and max values are valid for Tamb = 40 C to +85 C only.
[3]
Programming times are given for writing 256 bytes to the flash. Tamb < +85 C. Data must be written to the
flash in blocks of 256 bytes. Flash programming is accomplished via IAP calls (see LPC11Axx user
manual). Execution time of IAP calls depends on the system clock and is typically between 1.5 and 2 ms
per 256 bytes.
Table 10. EEPROM characteristics
Tamb = 55 C to +125 C; VDD(3V3) = 2.7 V to 3.6 V. Based on JEDEC NVM qualification. Failure
rate < 10 ppm for parts as specified below.
Symbol
Nendu
tret
Parameter
Conditions
Min
Typ
Max
Unit
endurance
[1]
100000
1000000
-
cycles
retention time
powered
[1]
100
200
-
years
unpowered
[1]
150
300
-
years
64 bytes
[2]
-
1.1
-
ms
programming
time
tprog
[1]
Min and max values are valid for Tamb = 40 C to +85 C only.
[2]
Tamb < +85 C.
10.3 External clock for oscillator in slave mode
Remark: The input voltage on the XTALIN pin must be 1.95 V (see Table 6). For
connecting the oscillator to the XTALIN/XTALOUT pins also see Section 12.3.
Table 11. Dynamic characteristic: external clock (XTALIN or CLKIN pin)
Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1]
LPC11AXX
Product data sheet
Min
Typ[2]
Max
Unit
oscillator frequency
1
-
25
MHz
Tcy(clk)
clock cycle time
40
-
1000
ns
tCHCX
clock HIGH time
Tcy(clk) 0.4
-
-
ns
tCLCX
clock LOW time
Tcy(clk) 0.4
-
-
ns
tCLCH
clock rise time
-
-
5
ns
tCHCL
clock fall time
-
-
5
ns
Symbol
Parameter
fosc
Conditions
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
tCHCL
tCHCX
tCLCH
tCLCX
Tcy(clk)
002aaa907
Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
10.4 Internal oscillators
Table 12. Dynamic characteristic: IRC
Tamb = 40 C to +85 C; 2.7 V VDD(3V3) 3.6 V.[1]
Symbol
Parameter
Conditions
fosc(RC)
internal RC oscillator frequency -
Min
Typ[2]
Max
Unit
11.88
12
12.12
MHz
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
002aah011
12.15
f
(MHz)
VDD = 3.6 V
3.3 V
3.0 V
2.7 V
12.05
11.95
11.85
-40
-15
10
35
60
85
temperature (°C)
Conditions: Frequency values are typical values. 12 MHz 1% accuracy is guaranteed for
2.7 V VDD(3V3) 3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the
IRC to fall outside the 12 MHz 1% accuracy specification for voltages below 2.7 V.
Fig 22. Internal IRC frequency vs. temperature
Table 13.
Dynamic characteristics: WDOsc and LFOsc
Min
Typ[1]
Max
Unit
internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1
frequency
in the WDTOSCCTRL register;
[2][3]
-
9.4
-
kHz
DIVSEL = 0x00, FREQSEL = 0xF
in the WDTOSCCTRL register
[2][3]
-
2300
-
kHz
Symbol Parameter
fosc
[1]
LPC11AXX
Product data sheet
Conditions
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
[2]
The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40%.
[3]
See the LPC11Axx user manual.
10.5 I/O pins
Table 14. Dynamic characteristic: digital I/O pins[1]
Tamb = 40 C to +85 C; 3.0 V VDD(IO) 3.6 V; load capacitor = 30 pF.
Symbol
Parameter
Conditions
tr
rise time
pin
configured as
output
fall time
tf
Min
Typ
Max
Unit
SSO = 1
[2][3]
2.5
-
5.0
ns
SSO = 6
[2][3]
2.5
-
4.5
ns
SSO = 16
[2][4]
3.0
-
5.0
ns
pin
configured as
output
[2][3]
SSO = 1
2.0
-
4.5
ns
SSO = 6
[2][3]
2.0
-
4.5
ns
SSO = 16
[2][4]
2.5
-
5.0
ns
[1]
Applies to standard port pins and RESET pin. Simulated results.
[2]
SSO indicates maximum number of simultaneously switching digital output pins. The pins are optimized for
half of the maximum SSO.
[3]
Set SLEW bit in the IOCON register to 1.
[4]
Set SLEW bit in the IOCON register to 0.
10.6 I2C-bus
Remark: All I2C modes (Standard-mode, Fast-mode, Fast-mode Plus) can be configured
for the true open-drain pins PIO0_2 and PIO0_3. If the limited-performance I2C-bus pins
are used (I2C-bus functions on standard I/O pins), only Standard-mode with internal
pull-up enabled or Fast-mode with external pull-up resistor are supported.
Table 15. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
SCL clock
frequency
Standard-mode
0
100
kHz
Fast-mode
0
400
kHz
tf
[4][5][6][7]
fall time
Fast-mode Plus
0
1
MHz
of both SDA and
SCL signals
-
300
ns
Fast-mode
20 + 0.1 Cb
300
ns
Fast-mode Plus
-
120
ns
4.7
-
s
Standard-mode
tLOW
LPC11AXX
Product data sheet
LOW period of
the SCL clock
Standard-mode
Fast-mode
1.3
-
s
Fast-mode Plus
0.5
-
s
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 15. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol
Parameter
Conditions
Min
Max
Unit
tHIGH
HIGH period of
the SCL clock
Standard-mode
4.0
-
s
Fast-mode
0.6
-
s
tHD;DAT
tSU;DAT
[1]
data hold time
data set-up
time
[3][4][8]
[9][10]
Fast-mode Plus
0.26
-
s
Standard-mode
0
-
s
Fast-mode
0
-
s
Fast-mode Plus
0
-
s
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
See the I2C-bus specification UM10204 for details.
[2]
Parameters are valid over operating temperature range unless otherwise specified.
[3]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[4]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5]
Cb = total capacitance of one bus line in pF.
[6]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[7]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[8]
The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if
the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the
data must be valid by the set-up time before it releases the clock.
[9]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT =
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
LPC11AXX
Product data sheet
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tf
SDA
tSU;DAT
70 %
30 %
70 %
30 %
tHD;DAT
tf
70 %
30 %
SCL
tVD;DAT
tHIGH
70 %
30 %
70 %
30 %
70 %
30 %
tLOW
S
1 / fSCL
002aaf425
Fig 23. I2C-bus pins clock timing
10.7 SSP interfaces
Table 16. Dynamic characteristics of SSP pins in SPI mode
2.6 V IDD ts/VDD(3V3) with
• VDD(3V3) 100 mV for the voltage drop below the BOD or POR trip points.
• IDD 3 mA with the IRC running and PLL/SysOsc off (see Figure 12).
LPC11AXX
Product data sheet
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• ts = 5 s for shallow brown-out (see Table 8).
• ts = 12 s for deep brown-out (see Table 8).
With these parameters, the decoupling/bypass capacitor to add to the supply line is:
• C 0.15 F for shallow brown-out
• C >> 0.36 F for deep brown-out
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13. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
pin 1 index
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7o
o
0
0.95
0.55
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 34. Package outline LQFP48
LPC11AXX
Product data sheet
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HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
A
B
D
terminal 1
index area
E
A
A1
c
detail X
e1
e
9
16
C
C A B
C
v
w
b
y
y1 C
L
8
17
e
e2
Eh
33
1
terminal 1
index area
24
32
X
25
Dh
0
2.5
scale
Dimensions
Unit
mm
5 mm
A(1)
A1
b
max 1.00 0.05 0.35
nom 0.85 0.02 0.28
min 0.80 0.00 0.23
c
D(1)
Dh
E(1)
0.2
7.1
7.0
6.9
4.85
4.70
4.55
7.1
7.0
6.9
Eh
e
e1
e2
L
0.75
4.85
4.70 0.65 4.55 4.55 0.60
0.45
4.55
v
0.1
w
y
0.05 0.08
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
References
IEC
JEDEC
JEITA
---
hvqfn33_po
European
projection
Issue date
09-03-17
09-03-23
Fig 35. Package outline HVQFN33 (7x7)
LPC11AXX
Product data sheet
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HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
D
B
A
terminal 1
index area
A
A1
E
c
detail X
C
e1
e
9
y1 C
C A B
C
v
w
1/2 e b
y
16
L
17
8
e
e2
Eh
1/2 e
24
1
terminal 1
index area
32
25
X
Dh
0
2.5
Dimensions (mm are the original dimensions)
Unit(1)
mm
A(1)
A1
b
max
0.05 0.30
nom 0.85
min
0.00 0.18
c
D(1)
Dh
E(1)
Eh
5.1
3.75
5.1
3.75
0.2
4.9
5 mm
scale
3.45
4.9
e
e1
e2
0.5
3.5
3.5
L
v
w
y
y1
0.5
0.1
0.05 0.05
0.1
0.3
3.45
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
References
IEC
JEDEC
JEITA
hvqfn33f_po
European
projection
Issue date
11-10-11
11-10-17
MO-220
Fig 36. Package outline HVQFN33 (5x5)
LPC11AXX
Product data sheet
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WLCSP20: wafer level chip-size package; 20 bumps; 2.5 x 2.5 x 0.6 mm
B
D
LPC11AxxUK
A
ball A1
index area
A2
E
A
A1
detail X
e1
e
C
C A B
C
Øv
Øw
b
y1 C
y
E
e
D
e2
C
B
A
ball A1
index area
1
2
3
4
X
0
0.5
1 mm
scale
Dimensions (mm are the original dimensions)
Unit
mm
A
A1
A2
b
D
E
max 0.65 0.27 0.38 0.35 2.60 2.60
nom 0.60 0.24 0.36 0.32 2.55 2.55
min 0.55 0.21 0.34 0.29 2.50 2.50
e
e1
e2
0.5
1.5
2.0
v
w
y
0.15 0.05 0.05
wlcsp20_lpc11axxuk_po
Outline
version
References
IEC
JEDEC
JEITA
European
projection
Issue date
12-03-26
LPC11AxxUK
Fig 37. Package outline (WLCSP20)
LPC11AXX
Product data sheet
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14. Soldering
Footprint information for reflow soldering of LQFP48 package
SOT313-2
Hx
Gx
P2
Hy
(0.125)
P1
Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
0.500
0.560
Ax
Ay
10.350 10.350
Bx
By
C
D1
D2
Gx
7.350
7.350
1.500
0.280
0.500
7.500
Gy
Hx
Hy
7.500 10.650 10.650
sot313-2_fr
Fig 38. Reflow soldering of the LQFP48 package
LPC11AXX
Product data sheet
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Footprint information for reflow soldering of HVQFN33 package
OID = 8.20 OA
PID = 7.25 PA+OA
OwDtot = 5.10 OA
evia = 4.25
0.20 SR
chamfer (4×)
W = 0.30 CU
SPD = 1.00 SP
LaE = 7.95 CU
PIE = 7.25 PA+OA
LbE = 5.80 CU
evia = 4.25
evia = 1.05
0.45 DM
SPE = 1.00 SP
GapE = 0.70 SP
4.55 SR
SEhtot = 2.70 SP
EHS = 4.85 CU
OwEtot = 5.10 OA
OIE = 8.20 OA
e = 0.65
0.45 DM
GapD = 0.70 SP
evia = 2.40
B-side
SDhtot = 2.70 SP
4.55 SR
DHS = 4.85 CU
Solder resist
covered via
0.30 PH
LbD = 5.80 CU
0.60 SR cover
LaD = 7.95 CU
0.60 CU
(A-side fully covered)
number of vias: 20
solder land
solder land plus solder paste
solder paste deposit
solder resist
occupied area
Dimensions in mm
Remark:
Stencil thickness: 0.125 mm
001aao134
Fig 39. Reflow soldering of the HVQFN33(7x7) package
LPC11AXX
Product data sheet
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Footprint information for reflow soldering of HVQFN33 package
Hx
Gx
see detail X
P
nSPx
By
Hy Gy SLy
Ay
nSPy
C
D
SLx
Bx
Ax
0.60
solder land
0.30
solder paste
detail X
occupied area
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
Gx
Gy
Hx
Hy
SLx
SLy
nSPx
nSPy
0.5
5.95
5.95
4.25
4.25
0.85
0.27
5.25
5.25
6.2
6.2
3.75
3.75
3
3
Issue date
11-11-15
11-11-20
002aag766
Fig 40. Reflow soldering of the HVQFN33(5x5) package
LPC11AXX
Product data sheet
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15. Abbreviations
Table 29.
LPC11AXX
Product data sheet
Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
AHB
Advanced High-performance Bus
AMBA
Advanced Microcontroller Bus Architecture
APB
Advanced Peripheral Bus
BOD
Brown-Out Detection
GPIO
General Purpose Input/Output
I2C
Inter Integrated Circuit
JEDEC
Joint Electron Devices Engineering Council
LVTSCR
Low-Voltage Triggered Silicon-Controlled Rectifier
NVM
Non-Volatile Memory
PLL
Phase-Locked Loop
SPI
Serial Peripheral Interface
SSI
Serial Synchronous Interface
TTL
Transistor-Transistor Logic
USART
Universal Synchronous/Asynchronous Receiver/Transmitter
UVLO
Under-Voltage LockOut
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16. Revision history
Table 30.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
LPC11AXX v.4
20121030
Product data sheet
-
LPC11AXX v.3
LPC11AXX v.3
LPC11AXX v.2.1
•
•
•
Parameter tPD corrected in Table 25.
•
Limiting values for parameter VI added for open-drain pins PIO0_2 and PIO0_3 in
Table 5 “Limiting values”.
•
•
Table 26 “Comparator voltage ladder reference static characteristics” updated.
•
Parameters VIA and Vtrig and Vi(xtal) added to Table 5.
Product data sheet
Maximum and minimum values for VDD and VDD(IO) updated in Table 5 “Limiting
values”.
Parameters ts(pu) and ts(sw) added to Table 21 “Internal voltage reference static and
dynamic characteristics”.
20120907
Product data sheet
-
LPC11AXX v.2.1
•
•
Section 10.1 abbreviated for clarity.
•
Table “Slew rate for the internal regulator power-up from ground” removed. This
specification is included in the cold start-up description in the LPC11Axx user manual.
•
•
Details regarding boundary scan added to Section 7.24 “Emulation and debugging”.
•
Section 12.8 “Guidelines for selecting a power supply filter for UVLO protection”
added.
•
•
•
Section 7.23.2 updated to include internal reset timer.
UVLO description including description of cold start-up behavior moved to the
LPC11Axx user manual.
Figure 33 “Functional diagram of the UVLO protection and reset timer circuit” updated
to include the reset timer circuit.
Parameter tPD corrected in Table 24.
Parameter EV(O) corrected in Table 26.
20120704
•
•
•
•
•
•
•
LPC11AXX
Editorial updates.
Product data sheet
-
LPC11AXX v.2
Data sheet status changed to Product.
Changed Table note [2] in Table 24.
Changed Table note [1] in Table 8.
Added Table note [1] in Table 9.
Moved DTsen and EL values from typ to max in Table 22.
Corrected Vesd in Table 5.
Added Table note [5] and Table note [6] to Table 4.
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Table 30.
Revision history …continued
Document ID
Release date
Data sheet status
LPC11AXX v.2
20120625
Preliminary data sheet -
LPC11AXX v.1
LPC11AXX
Product data sheet
Change notice
Supersedes
LPC11AXX v.1
•
•
•
•
•
•
Data sheet status changed to Preliminary.
•
Power consumption data for active and sleep modes with all peripherals enabled
removed in Table 6 and Section 9.1.
•
•
•
•
•
•
Parameters ts(pu) and ts(sw) removed from Section 7.15.
•
Parameter VO corrected for condition Tamb = 40 C to +85 C in Table 22.
Parameter fclk removed from Table 11.
ter removed in Table 11.
Writable EEPROM size specified in Section 7.3.
Section 10.3 “UVLO reset behavior” added.
Power consumption data updated for active mode and sleep mode (see Figure 11 to
Figure 13).
Parameter tPD updated in Table 25.
SSP dynamic characteristics added in Table 17.
WDOsc and LFOsc max and min frequency values updated throughout the data sheet.
Section 12.7 “UVLO protection circuit” added.
Typical values for parameters ED, EL(adj), EO, EG, and CL in Table 20 “DAC static and
dynamic characteristics” changed to maximum values.
20120322
Objective data sheet
-
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-
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17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
LPC11AXX
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC11AXX
Product data sheet
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19. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.7.1
7.7.2
7.8
7.9
7.9.1
7.10
7.10.1
7.11
7.11.1
7.12
7.12.1
7.13
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional description . . . . . . . . . . . . . . . . . . 23
ARM Cortex-M0 processor . . . . . . . . . . . . . . . 23
On-chip flash program memory . . . . . . . . . . . 23
On-chip EEPROM data memory. . . . . . . . . . . 23
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 23
On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 23
Nested Vectored Interrupt Controller (NVIC) . 24
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 25
IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 25
Fast general purpose parallel I/O . . . . . . . . . . 25
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SSP serial I/O controller . . . . . . . . . . . . . . . . . 26
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2C-bus serial I/O controller . . . . . . . . . . . . . . 26
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Configurable analog/mixed-signal
subsystems. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.14
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.14.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.15
Internal voltage reference . . . . . . . . . . . . . . . . 29
7.16
Temperature sensor . . . . . . . . . . . . . . . . . . . . 30
7.17
10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.17.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.18
Analog comparator . . . . . . . . . . . . . . . . . . . . . 31
7.18.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.19
General purpose external event
counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.19.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.20
System tick timer . . . . . . . . . . . . . . . . . . . . . . 33
7.21
Windowed WatchDog Timer (WWDT) . . . . . . 33
7.21.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.22
Clocking and power control . . . . . . . . . . . . . . 34
7.22.1
Crystal and internal oscillators . . . . . . . . . . . . 34
7.22.1.1 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . 35
7.22.1.2
7.22.1.3
Crystal Oscillator (SysOsc) . . . . . . . . . . . . . .
Internal Low-Frequency Oscillator (LFOsc)
and Watchdog Oscillator (WDOsc) . . . . . . . .
7.22.2
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.22.3
System PLL . . . . . . . . . . . . . . . . . . . . . . . . . .
7.22.4
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . .
7.22.5
Wake-up process . . . . . . . . . . . . . . . . . . . . . .
7.22.6
Power control . . . . . . . . . . . . . . . . . . . . . . . . .
7.22.6.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . .
7.22.6.2 Power profiles . . . . . . . . . . . . . . . . . . . . . . . .
7.23
System control . . . . . . . . . . . . . . . . . . . . . . . .
7.23.1
UnderVoltage LockOut (UVLO) protection . . .
7.23.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.23.3
Brown-out detection . . . . . . . . . . . . . . . . . . . .
7.23.4
Code security (Code Read Protection - CRP)
7.23.5
APB interface . . . . . . . . . . . . . . . . . . . . . . . . .
7.23.6
AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.23.7
External interrupt inputs . . . . . . . . . . . . . . . . .
7.24
Emulation and debugging . . . . . . . . . . . . . . .
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
9
Static characteristics . . . . . . . . . . . . . . . . . . .
9.1
Power consumption . . . . . . . . . . . . . . . . . . .
9.2
Peripheral power consumption . . . . . . . . . . .
9.3
Electrical pin characteristics. . . . . . . . . . . . . .
10
Dynamic characteristics. . . . . . . . . . . . . . . . .
10.1
Power supply fluctuations . . . . . . . . . . . . . . .
10.2
Flash/EEPROM memory . . . . . . . . . . . . . . . .
10.3
External clock for oscillator in slave mode . . .
10.4
Internal oscillators . . . . . . . . . . . . . . . . . . . . .
10.5
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7
SSP interfaces . . . . . . . . . . . . . . . . . . . . . . . .
11
Characteristics of analog peripherals. . . . . .
12
Application information . . . . . . . . . . . . . . . . .
12.1
ADC usage notes. . . . . . . . . . . . . . . . . . . . . .
12.2
Use of ADC input trigger signals . . . . . . . . . .
12.3
XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4
XTAL Printed Circuit Board (PCB) layout
guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5
Standard I/O pad configuration . . . . . . . . . . .
12.6
Reset pad configuration . . . . . . . . . . . . . . . . .
12.7
UVLO protection and reset timer circuit . . . . .
12.8
Guidelines for selecting a power supply filter
for UVLO protection . . . . . . . . . . . . . . . . . . . .
13
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
14
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
36
36
36
36
36
36
36
37
37
37
37
38
38
38
38
39
39
40
42
45
47
47
51
51
51
52
53
54
54
56
58
66
66
66
66
68
68
69
69
69
71
75
continued >>
LPC11AXX
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 30 October 2012
© NXP B.V. 2012. All rights reserved.
83 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
15
16
17
17.1
17.2
17.3
17.4
18
19
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
79
81
81
81
81
82
82
83
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 October 2012
Document identifier: LPC11AXX
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