LPC15xx
32-bit ARM Cortex-M3 microcontroller; up to 256 kB flash and
36 kB SRAM; FS USB, CAN, RTC, SPI, USART, I2C
Rev. 1.1 — 29 April 2015
Product data sheet
1. General description
The LPC15xx are ARM Cortex-M3 based microcontrollers for embedded applications
featuring a rich peripheral set with very low power consumption. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as enhanced debug features
and a higher level of support block integration.
The LPC15xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The LPC15xx includes up to 256 kB of flash memory, 32 kB of ROM, a 4 kB EEPROM,
and up to 36 kB of SRAM. The peripheral complement includes one full-speed USB 2.0
device, two SPI interfaces, three USARTs, one Fast-mode Plus I2C-bus interface, one
C_CAN module, PWM/timer subsystem with four configurable, multi-purpose State
Configurable Timers (SCTimer/PWM) with input pre-processing unit, a Real-time clock
module with independent power supply and a dedicated oscillator, two 12-channel/12-bit,
2 Msamples/s ADCs, one 12-bit, 500 kSamples/s DAC, four voltage comparators with
internal voltage reference, and a temperature sensor. A DMA engine can service most
peripherals.
For additional documentation related to the LPC15xx parts, see Section 17 “References”.
2. Features and benefits
System:
ARM Cortex-M3 processor (version r2p1), running at frequencies of up to 72 MHz.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
System tick timer.
Serial Wire Debug (SWD) with four breakpoints and two watchpoints.
Single-cycle multiplier supported.
Memory Protection Unit (MPU) included.
Memory:
Up to 256 kB on-chip flash programming memory with 256 Byte page write and
erase.
Up to 36 kB SRAM.
4 kB EEPROM.
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
ROM API support:
Boot loader with boot options from flash or external source via USART, C_CAN, or
USB
USB drivers
ADC drivers
SPI drivers
USART drivers
I2C drivers
Power profiles and power mode configuration with low-power mode configuration
option
DMA drivers
C_CAN drivers
Flash In-Application Programming (IAP) and In-System Programming (ISP).
Digital peripherals:
Simple DMA engine with 18 channels and 20 programmable input triggers.
High-speed GPIO interface with up to 76 General-Purpose I/O (GPIO) pins with
configurable pull-up/pull-down resistors, open-drain mode, input inverter, and
programmable digital glitch filter.
GPIO interrupt generation capability with boolean pattern-matching feature on eight
external inputs.
Two GPIO grouped port interrupts.
Switch matrix for flexible configuration of each I/O pin function.
CRC engine.
Quadrature Encoder Interface (QEI).
Configurable PWM/timer/motor control subsystem:
Up to four 32-bit counter/timers or up to eight 16-bit counter/timers or combinations
of 16-bit and 32-bit timers.
Up to 28 match outputs and 22 configurable capture inputs with input multiplexer.
Up to 28 PWM outputs total.
Dither engine for improved average resolution of pulse edges.
Four State Configurable Timers (SCTimers) for highly flexible, event-driven timing
and PWM applications.
SCT Input Pre-processor Unit (SCTIPU) for processing timer inputs and immediate
handling of abort situations.
Integrated with ADC threshold compare interrupts, temperature sensor, and analog
comparator outputs for motor control feedback using analog signals.
Special-application and simple timers:
24-bit, four-channel, multi-rate timer (MRT) for repetitive interrupt generation at up
to four programmable, fixed rates.
Repetitive interrupt timer for general purpose use.
Windowed Watchdog timer (WWDT).
High-resolution 32-bit Real-time clock (RTC) with selectable 1 s or 1 ms time
resolution running in the always-on power domain. RTC can be used for wake-up
from all low power modes including Deep power-down.
LPC15XX
Product data sheet
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Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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32-bit ARM Cortex-M3 microcontroller
Analog peripherals:
Two 12-bit ADC with up to 12 input channels per ADC and with multiple internal
and external trigger inputs and sample rates of up to 2 Msamples/s. Each ADC
supports two independent conversion sequences. ADC conversion clock can be
the system clock or an asynchronous clock derived from one of the three PLLs.
One 12-bit DAC.
Integrated temperature sensor and band gap internal reference voltage.
Four comparators with external and internal voltage references (ACMP0 to 3).
Comparator outputs are internally connected to the SCTimer/PWMs and ADCs and
externally to pins. Each comparator output contains a programmable glitch filter.
Serial interfaces:
Three USART interfaces with DMA, RS-485 support, autobaud, and with
synchronous mode and 32 kHz mode for wake-up from Deep-sleep and
Power-down modes. The USARTs share a fractional baud-rate generator.
Two SPI controllers.
One I2C-bus interface supporting fast mode and Fast-mode Plus with data rates of
up to 1Mbit/s and with multiple address recognition and monitor mode.
One C_CAN controller.
One USB 2.0 full-speed device controller with on-chip PHY.
Clock generation:
12 MHz internal RC oscillator trimmed to 1 % accuracy for 25 C Tamb +85 C
that can optionally be used as a system clock.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Watchdog oscillator with a frequency range of 503 kHz.
32 kHz low-power RTC oscillator with 32 kHz, 1 kHz, and 1 Hz outputs.
System PLL allows CPU operation up to the maximum CPU rate without the need
for a high-frequency crystal. May be run from the system oscillator or the internal
RC oscillator.
Two additional PLLs for generating the USB and SCTimer/PWM clocks.
Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption.
Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode.
APIs provided for optimizing power consumption in active and sleep modes and for
configuring Deep-sleep, Power-down, and Deep power-down modes.
Wake-up from Deep-sleep and Power-down modes on activity on USB, USART,
SPI, and I2C peripherals.
Wake-up from Sleep, Deep-sleep, Power-down, and Deep power-down modes
from the RTC alarm or wake-up interrupts.
Timer-controlled self wake-up from Deep power-down mode using the RTC
high-resolution/wake-up 1 kHz timer.
Power-On Reset (POR).
BrownOut Detect BOD).
JTAG boundary scan modes supported.
Unique device serial number for identification.
LPC15XX
Product data sheet
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Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 107
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Single power supply 2.4 V to 3.6 V.
Temperature range 40 °C to +105 °C.
Available as LQFP100, LQFP64, and LQFP48 packages.
3. Applications
Motor control
Motion drives
Digital power supplies
Industrial and medical
Solar inverters
Home appliances
Building and factory automation
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC1549JBD100
LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm
LPC1549JBD64
LQFP64
plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm
SOT314-2
LPC1549JBD48
LQFP48
plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm
SOT313-2
LPC1548JBD100
LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm
LPC1548JBD64
LQFP64
plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm
SOT314-2
LPC1547JBD64
LQFP64
plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm
SOT314-2
LPC1547JBD48
LQFP48
plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm
SOT313-2
LPC1519JBD100
LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm
LPC1519JBD64
LQFP64
LPC1518JBD100
LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm
LPC1518JBD64
LQFP64
plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm
SOT314-2
LPC1517JBD64
LQFP64
plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm
SOT314-2
LPC1517JBD48
LQFP48
plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm
SOT313-2
LPC15XX
Product data sheet
plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 29 April 2015
SOT407-1
SOT407-1
SOT407-1
SOT314-2
SOT407-1
© NXP Semiconductors N.V. 2015. All rights reserved.
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LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
4.1 Ordering options
Table 2.
Ordering options for LPC15xx
Type number
Flash/
kB
EEPROM/ Total
USB
kB
SRAM/
kB
USART I2C SPI
C_CAN SCTimer/ 12-bit
DAC GPIO
PWM
ADC0/1
channels
LPC1549JBD100 256
4
36
yes
3
1
2
1
4
12/12
1
76
LPC1549JBD64
256
4
36
yes
3
1
2
1
4
12/12
1
44
LPC1549JBD48
256
4
36
yes
3
1
2
1
4
9/7
1
30
LPC1548JBD100 128
4
20
yes
3
1
2
1
4
12/12
1
76
LPC1548JBD64
128
4
20
yes
3
1
2
1
4
12/12
1
44
LPC1547JBD64
64
4
12
yes
3
1
2
1
4
12/12
1
44
LPC1547JBD48
64
4
12
yes
3
1
2
1
4
9/7
1
30
LPC1519JBD100 256
4
36
no
3
1
2
1
4
12/12
1
78
LPC1519JBD64
256
4
36
no
3
1
2
1
4
12/12
1
46
LPC1518JBD100 128
4
20
no
3
1
2
1
4
12/12
1
78
LPC1518JBD64
128
4
20
no
3
1
2
1
4
12/12
1
46
LPC1517JBD64
64
4
12
no
3
1
2
1
4
12/12
1
46
LPC1517JBD48
64
4
12
no
3
1
2
1
4
9/7
1
32
LPC15XX
Product data sheet
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Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
5. Marking
n
n
Terminal 1 index area
1
aaa-011231
Fig 1.
LQFP64/100 package marking
Terminal 1 index area
Fig 2.
1
aaa-011232
LQFP48 package marking
The LPC15xx devices typically have the following top-side marking for LQFP100
packages:
LPC15xxJxxx
Xxxxxx xx
xxxyywwxxx
The LPC15xx devices typically have the following top-side marking for LQFP64 packages:
LPC15xxJ
Xxxxxx xx
xxxyywwxxx
The LPC15xx devices typically have the following top-side marking for LQFP48 packages:
LPC15xxJ
Xxxxxx
Xxxyy
wwxxx
Field ‘yy’ states the year the device was manufactured. Field ‘ww’ states the week the
device was manufactured during that year.
LPC15XX
Product data sheet
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Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 107
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
6. Block diagram
LPC15xx
PROCESSOR CORE
ARM
CORTEX-M3
NVIC
TEST/DEBUG INTERFACE
SWD/ETM
MPU
HS GPIO
MEMORY
256/128/64 kB FLASH
PORT0/1/2
pads
n
SYSTICK
AHB MULTILAYER
MATRIX
PINT/
PATTERN MATCH
4 kB EEPROM
INPUT MUX
36/20/12 kB SRAM
GINT0/1
AHB/APB BRIDGES
32 kB ROM
ANALOG PERIPHERALS
ACMP1
ACMP0/
TEMPERATURE
SENSOR
12-bit DAC
ACMP2
ACMP3
12-bit ADC0
12-bit ADC1
TRIGGER MUX
TRIGGER MUX
INPUT MUX
INPUT MUX
SWM
pads
n
SCTIMER/PWM/MOTOR CONTROL SUBSYSTEM
DMA TRIGGER
QEI
SCTIMER0/ SCTIMER1/ SCTIMER2/ SCTIMER3/
PWM
PWM
PWM
PWM
DMA
SCTIPU
SERIAL PERIPHERALS
C_CAN
FS USB/
PHY
USART0
FM+ I2C0
SPI1
USART1
USART2
SPI0
TIMERS
CLOCK
GENERATION
MRT
RIT
PRECISION
IRC
WATCHDOG
OSCILLATOR
SYSTEM
PLL
USB
PLL
SCT
PLL
WWDT
RTC
SYSTEM
OSCILLATOR
FREQUENCY
MEASUREMENT
RTC
OSCILLATOR
INPUT MUX
SYSTEM/MEMORY CONTROL
SYSCON
IOCON
PMU
CRC
FLASH CTRL
EEPROM CTRL
aaa-010869
Grey-shaded blocks show peripherals that can provide hardware triggers for DMA transfers or have DMA request lines.
Fig 3.
LPC15xx Block diagram
LPC15XX
Product data sheet
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Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
7. Pinning information
25 XTALOUT
26 XTALIN
27 VDD
28 PIO0_17/WAKEUP/TRST
29 SWCLK/ PIO0_19/TCK
30 VBAT
31 RTCXIN
32 RTCXOUT
33 SWDIO/ PIO0_20/SCT1_OUT6/ TMS
34 RESET/PIO0_21
35 USB_DP
36 USB_DM
7.1 Pinning
PIO0_22/I2C0_SCL 37
24 PIO0_16/ADC1_9
PIO0_23/I2C0_SDA 38
23 PIO0_15/ADC1_8
VDD 39
22 PIO0_14/ADC1_7/ SCT1_OUT5
VSS 40
21 PIO0_13/ADC1_6
VSS 41
20 VSS
VDD 42
19 PIO0_12/DAC_OUT
LPC1547JBD48
LPC1549JBD48
PIO0_24/SCT0_OUT6 43
18 PIO0_11/ADC1_3
PIO0_25/ACMP0_I4 44
17 VSSA
PIO0_26/ACMP0_I3/ SCT3_OUT3 45
16 VDDA
PIO0_27/ACMP_I1 46
15 PIO0_10/ADC1_2
PIO0_28/ACMP1_I3 47
14 VREFP_DAC_VDDCMP
PIO0_9/ADC1_1/TDI 12
VREFN 11
VREFP_ADC 10
PIO0_7/ADC0_1 8
PIO0_8/ADC0_0/TDO 9
PIO0_5/ADC0_3 6
PIO0_6/ADC0_2/ SCT2_OUT3 7
PIO0_4/ADC0_4 5
PIO0_3/ADC0_5/ SCT1_OUT4 4
PIO0_2/ADC0_6/ SCT1_OUT3 3
PIO0_1/ADC0_7/ SCT0_OUT4 2
13 PIO0_18/ SCT0_OUT5
PIO0_0/ADC0_10/ SCT0_OUT3 1
PIO0_29/ACMP2_I3/ SCT2_OUT4 48
aaa-009352
Fig 4.
LQFP48 pin configuration (with USB)
LPC15XX
Product data sheet
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Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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LPC15xx
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25 XTALOUT
26 XTALIN
27 VDD
28 PIO0_17/WAKEUP/TRST
29 SWCLK/ PIO0_19/TCK
30 VBAT
31 RTCXIN
32 RTCXOUT
33 SWDIO/ PIO0_20/SCT1_OUT6/ TMS
34 RESET/PIO0_21
35 PIO2_12
36 PIO2_13
32-bit ARM Cortex-M3 microcontroller
PIO0_22/I2C0_SCL 37
24 PIO0_16/ADC1_9
PIO0_23/I2C0_SDA 38
23 PIO0_15/ADC1_8
VDD 39
22 PIO0_14/ADC1_7/ SCT1_OUT5
VSS 40
21 PIO0_13/ADC1_6
VSS 41
20 VSS
VDD 42
19 PIO0_12/DAC_OUT
LPC1517JBD48
PIO0_24/SCT0_OUT6 43
18 PIO0_11/ADC1_3
PIO0_25/ACMP0_I4 44
17 VSSA
PIO0_26/ACMP0_I3/ SCT3_OUT3 45
16 VDDA
PIO0_27/ACMP_I1 46
15 PIO0_10/ADC1_2
PIO0_28/ACMP1_I3 47
14 VREFP_DAC_VDDCMP
PIO0_9/ADC1_1/TDI 12
VREFN 11
VREFP_ADC 10
PIO0_7/ADC0_1 8
PIO0_8/ADC0_0/TDO 9
PIO0_5/ADC0_3 6
PIO0_6/ADC0_2/ SCT2_OUT3 7
PIO0_4/ADC0_4 5
PIO0_3/ADC0_5/ SCT1_OUT4 4
PIO0_2/ADC0_6/ SCT1_OUT3 3
PIO0_1/ADC0_7/ SCT0_OUT4 2
13 PIO0_18/ SCT0_OUT5
PIO0_0/ADC0_10/ SCT0_OUT3 1
PIO0_29/ACMP2_I3/ SCT2_OUT4 48
aaa-009354
Fig 5.
LQFP48 pin configuration (without USB)
LPC15XX
Product data sheet
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Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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LPC15xx
NXP Semiconductors
33 PIO1_4
34 PIO1_5
35 XTALOUT
36 XTALIN
37 VDD
38 PIO1_11
39 PIO0_17/WAKEUP
40 SWCLK/ PIO0_19
41 VBAT
42 RTCXIN
43 RTCXOUT
44 SWDIO/ PIO0_20
45 RESET/PIO0_21
46 PIO1_6
47 USB_DP
48 USB_DM
32-bit ARM Cortex-M3 microcontroller
PIO0_22 49
32 PIO0_16
PIO0_23 50
31 PIO0_15
PIO1_7 51
30 PIO0_14
VDD 52
29 PIO0_13
PIO1_8 53
28 PIO1_3
PIO1_9 54
27 VSS
VSS 55
26 VSS
LPC1549JBD64
LPC1548JBD64
LPC1547JBD64
VSS 56
VDD 57
25 PIO1_2
24 PIO0_12
PIO0_9 16
VREFN 14
PIO1_1 15
PIO0_8 12
VREFP_ADC 13
PIO0_7 11
17 PIO0_18
PIO0_6 10
PIO0_29 64
PIO0_5 9
18 VREFP_DAC_VDDCMP
PIO0_4 8
19 PIO0_10
PIO0_28 63
PIO0_3 7
PIO0_27 62
PIO0_2 6
20 VDDA
PIO0_1 5
21 VSSA
PIO0_26 61
PIO1_0 4
PIO0_25 60
PIO0_0 2
22 VDD
PIO0_31 3
23 PIO0_11
PIO1_10 59
PIO0_30 1
PIO0_24 58
aaa-009353
See Table 3 for the full pin name.
Fig 6.
LQFP64 pin configuration (with USB)
LPC15XX
Product data sheet
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Rev. 1.1 — 29 April 2015
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LPC15xx
NXP Semiconductors
33 PIO1_4
34 PIO1_5
35 XTALOUT
36 XTALIN
37 VDD
38 PIO1_11
39 PIO0_17/WAKEUP
40 SWCLK/ PIO0_19
41 VBAT
42 RTCXIN
43 RTCXOUT
44 SWDIO/ PIO0_20
45 RESET/PIO0_21
46 PIO1_6
47 PIO2_12
48 PIO2_13
32-bit ARM Cortex-M3 microcontroller
PIO0_22 49
32 PIO0_16
PIO0_23 50
31 PIO0_15
PIO1_7 51
30 PIO0_14
VDD 52
29 PIO0_13
PIO1_8 53
28 PIO1_3
PIO1_9 54
27 VSS
VSS 55
26 VSS
LPC1519JBD64
LPC1518JBD64
LPC1517JBD64
VSS 56
VDD 57
24 PIO0_12
PIO0_9 16
VREFN 14
PIO1_1 15
PIO0_8 12
VREFP_ADC 13
17 PIO0_18
PIO0_7 11
PIO0_29 64
PIO0_6 10
18 VREFP_DAC_VDDCMP
PIO0_5 9
19 PIO0_10
PIO0_28 63
PIO0_4 8
PIO0_27 62
PIO0_3 7
20 VDDA
PIO0_2 6
21 VSSA
PIO0_26 61
PIO0_1 5
PIO0_25 60
PIO1_0 4
22 VDD
PIO0_0 2
23 PIO0_11
PIO1_10 59
PIO0_31 3
PIO0_24 58
PIO0_30 1
aaa-009376
51
LQFP64 pin configuration (without USB)
75
Fig 7.
25 PIO1_2
76
50
LPC1548JBD100
LPC1518JBD100
25
26
1
100
aaa-009351
Fig 8.
LPC15XX
Product data sheet
LQFP100 pin configuration
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 107
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
7.2 Pin description
Most pins are configurable for multiple functions, which can be analog or digital. Digital
inputs can be connected to several peripherals at once, however only one digital output or
one analog function can be assigned to any on pin. The pin’s connections to internal
peripheral blocks are configured by the switch matrix (SWM), the input multiplexer (INPUT
MUX), and the SCT Input Pre-processor Unit (SCTIPU).
The switch matrix enables certain fixed-pin functions that can only reside on specific pins
(see Table 3) and assigns all other pin functions (movable functions) to any available pin
(see Table 4), so that the pinout can be optimized for a given application.
The input multiplexer provides many choices (pins and internal signals) for selecting the
inputs of the SCTimer/PWMs and the frequency measure block. Pins that are connected
to the input multiplexer are listed in Table 5. If a pin is selected in the input multiplexer, it is
directly connected to the peripheral input without being routed through the switch matrix.
Independently of being selected in the input multiplexer, the same pin can also be
assigned by the switch matrix to another peripheral input.
Four pins can also be connected directly to the SCTIPU and at the same time be inputs to
the input multiplexer and the switch matrix (see Table 5).
PIO0_1/ADC0_7/
SCT0_OUT4
LQFP100
PIO0_0/ADC0_10/
SCT0_OUT3
LQFP64
Pin description with fixed-pin functions
Symbol
LQFP48
Table 3.
1
2
2
2
PIO0_2/ADC0_6/
SCT1_OUT3
3
PIO0_3/ADC0_5/
SCT1_OUT4
4
PIO0_4/ADC0_4
5
6
6
8
[2]
[2]
[2]
5
7
8
10
[2]
I; PU
I; PU
I; PU
I; PU
9
14
PIO0_6/ADC0_2/
SCT2_OUT3
7
10
16
[2]
8
11
I; PU
13
6
Product data sheet
I; PU
[2]
PIO0_5/ADC0_3
LPC15XX
Description
IO
PIO0_0 — General purpose port 0 input/output 0.
A
ADC0_10 — ADC0 input 10.
O
SCT0_OUT3 — SCTimer0/PWM output 3.
IO
PIO0_1 — General purpose port 0 input/output 1.
A
ADC0_7 — ADC0 input 7.
O
SCT0_OUT4 — SCTimer0/PWM output 4.
IO
PIO0_2 — General purpose port 0 input/output 2.
ADC0_6 — ADC0 input 6.
[2]
PIO0_7/ADC0_1
Reset Type
state[1]
17
[2]
I; PU
I; PU
O
SCT1_OUT3 — SCTimer1/PWM output 3.
IO
PIO0_3 — General purpose port 0 input/output 3.
A
ADC0_5 — ADC0 input 5.
O
SCT1_OUT4 — SCTimer1/PWM output 4.
IO
PIO0_4 — General purpose port 0 input/output 4. This is
the ISP_0 boot pin for the LQFP48 package.
A
ADC0_4 — ADC0 input 4.
IO
PIO0_5 — General purpose port 0 input/output 5.
A
ADC0_3 — ADC0 input 3.
IO
PIO0_6 — General purpose port 0 input/output 6.
A
ADC0_2 — ADC0 input 2.
O
SCT2_OUT3 — SCTimer2/PWM output 3.
IO
PIO0_7 — General purpose port 0 input/output 7.
A
ADC0_1 — ADC0 input 1.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 107
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
PIO0_8/ADC0_0/TDO
LQFP100
Symbol
LQFP64
Pin description with fixed-pin functions
LQFP48
Table 3.
9
12
19
[2]
Reset Type
state[1]
Description
I; PU
PIO0_8 — General purpose port 0 input/output 8.
IO
In boundary scan mode: TDO (Test Data Out).
PIO0_9/ADC1_1/TDI
12
16
24
[2]
I; PU
A
ADC0_0 — ADC0 input 0.
IO
PIO0_9 — General purpose port 0 input/output 9.
In boundary scan mode: TDI (Test Data In).
PIO0_10/ADC1_2
15
19
28
[2]
PIO0_11/ADC1_3
18
23
33
[2]
I; PU
I; PU
A
ADC1_1 — ADC1 input 1.
IO
PIO0_10 — General purpose port 0 input/output 10.
A
ADC1_2 — ADC1 input 2.
IO
PIO0_11 — General purpose port 0 input/output 11.
On the LQFP64 package, this pin is assigned to
CAN0_RD in ISP C_CAN mode.
PIO0_12/DAC_OUT
PIO0_13/ADC1_6
19
21
24
29
35
[3]
43
[2]
I; PU
I; PU
A
ADC1_3 — ADC1 input 3.
IO
PIO0_12 — General purpose port 0 input/output 12. If this
pin is configured as a digital input, the input voltage level
must not be higher than VDDA.
A
DAC_OUT — DAC analog output.
IO
PIO0_13 — General purpose port 0 input/output 13.
On the LQFP64 package, this pin is assigned to U0_RXD
in ISP USART mode.
On the LQFP48 package, this pin is assigned to
CAN0_RD in ISP C_CAN mode.
PIO0_14/ADC1_7/
SCT1_OUT5
PIO0_15/ADC1_8
22
30
45
[2]
I; PU
A
ADC1_6 — ADC1 input 6.
IO
PIO0_14 — General purpose port 0 input/output 14.
On the LQFP48 package, this pin is assigned to U0_RXD
in ISP USART mode.
23
31
47
[2]
I; PU
A
ADC1_7 — ADC1 input 7.
O
SCT1_OUT5 — SCTimer1/PWM output 5.
IO
PIO0_15 — General purpose port 0 input/output 15.
On the LQFP48 package, this pin is assigned to U0_TXD
in ISP USART mode.
PIO0_16/ADC1_9
24
32
49
[2]
I; PU
A
ADC1_8 — ADC1 input 8.
IO
PIO0_16 — General purpose port 0 input/output 16.
On the LQFP48 package, this is the ISP_1 boot pin.
PIO0_17/WAKEUP/
TRST
28
39
61
[4]
I; PU
A
ADC1_9 — ADC1 input 9.
IO
PIO0_17 — General purpose port 0 input/output 17. In
boundary scan mode: TRST (Test Reset).
This pin triggers a wake-up from Deep power-down mode.
For wake up from Deep power-down mode via an external
pin, do not assign any movable function to this pin. Pull
this pin HIGH externally while in Deep power-down mode.
Pull this pin LOW to exit Deep power-down mode. A
LOW-going pulse as short as 50 ns wakes up the part.
LPC15XX
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 107
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
PIO0_18/
SCT0_OUT5
LQFP100
Symbol
LQFP64
Pin description with fixed-pin functions
LQFP48
Table 3.
13
17
26
[5]
Reset Type
state[1]
Description
I; PU
PIO0_18 — General purpose port 0 input/output 18.
IO
On the LQFP64 package, this pin is assigned to U0_TXD
in ISP USART mode.
On the LQFP48 package, this pin is assigned to
CAN0_TD in ISP C_CAN mode.
SWCLK/
PIO0_19/TCK
29
40
63
[5]
I; PU
O
SCT0_OUT5 — SCTimer0/PWM output 5.
I
SWCLK — Serial Wire Clock. SWCLK is enabled by
default on this pin.
In boundary scan mode: TCK (Test Clock).
SWDIO/
PIO0_20/SCT1_OUT6/
TMS
RESET/PIO0_21
33
44
69
[5]
I; PU
IO
PIO0_19 — General purpose port 0 input/output 19.
I/O
SWDIO — Serial Wire Debug I/O. SWDIO is enabled by
default on this pin.
In boundary scan mode: TMS (Test Mode Select).
34
45
71
[6]
I; PU
I/O
PIO0_20 — General purpose port 0 input/output 20.
O
SCT1_OUT6 — SCTimer1/PWM output 6.
I
RESET — External reset input: A LOW-going pulse as
short as 50 ns on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and
processor execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH
externally. The RESET pin can be left unconnected or be
used as a GPIO or for any movable function if an external
RESET function is not needed and the Deep power-down
mode is not used.
PIO0_22/I2C0_SCL
PIO0_23/I2C0_SDA
PIO0_24/SCT0_OUT6
PIO0_25/ACMP0_I4
PIO0_26/ACMP0_I3/
SCT3_OUT3
LPC15XX
Product data sheet
37
38
43
44
45
49
50
58
60
61
78
79
[7]
[7]
90
[8]
93
[2]
95
[2]
IA
IA
I; PU
I; PU
I; PU
I/O
PIO0_21 — General purpose port 0 input/output 21.
IO
PIO0_22 — General purpose port 0 input/output 22
(open-drain)
I/O
I2C0_SCL — Open-drain I2C-bus clock input/output.
High-current sink if I2C Fast-mode Plus is selected in the
I/O configuration register.
IO
PIO0_23 — General purpose port 0 input/output 23
(open-drain).
I/O
I2C0_SDA — I2C-bus data input/output. High-current sink
if I2C Fast-mode Plus is selected in the I/O configuration
register.
IO
PIO0_24 — General purpose port 0 input/output 24.
High-current output driver.
O
SCT0_OUT6 — SCTimer0/PWM output 6.
IO
PIO0_25 — General purpose port 0 input/output 25.
A
ACMP0_I4 — Analog comparator 0 input 4.
IO
PIO0_26 — General purpose port 0 input/output 26.
A
ACMP0_I3 — Analog comparator 0 input 3.
O
SCT3_OUT3 — SCTimer3/PWM output 3.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 107
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Table 3.
Pin description with fixed-pin functions
IO
PIO0_27 — General purpose port 0 input/output 27.
A
ACMP_I1 — Analog comparator common input 1.
IO
PIO0_28 — General purpose port 0 input/output 28.
A
ACMP1_I3 — Analog comparator 1 input 3.
IO
PIO0_29 — General purpose port 0 input/output 29.
A
ACMP2_I3 — Analog comparator 2 input 3.
O
SCT2_OUT4 — SCTimer2/PWM output 4.
IO
PIO0_30 — General purpose port 0 input/output 30.
A
ADC0_11 — ADC0 input 11.
IO
PIO0_31 — General purpose port 0 input/output 31.
LQFP100
Description
LQFP64
Reset Type
state[1]
LQFP48
Symbol
PIO0_27/ACMP_I1
46
62
97
[2]
I; PU
PIO0_28/ACMP1_I3
47
63
98
[2]
I; PU
100
[2]
PIO0_29/ACMP2_I3/
SCT2_OUT4
PIO0_30/ADC0_11
PIO0_31/ADC0_9
48
-
64
1
3
1
[2]
3
[2]
I; PU
I; PU
I; PU
On the LQFP64 package, this pin is assigned to
CAN0_TD in ISP C_CAN mode.
PIO1_0/ADC0_8
-
4
5
[2]
I; PU
I; PU
I; PU
PIO1_1/ADC1_0
-
15
23
[2]
PIO1_2/ADC1_4
-
25
36
[2]
I; PU
I; PU
PIO1_3/ADC1_5
-
28
41
[2]
PIO1_4/ADC1_10
-
33
51
[2]
I; PU
I; PU
PIO1_5/ADC1_11
-
34
52
[2]
PIO1_6/ACMP_I2
-
46
73
[2]
I; PU
I; PU
PIO1_7/ACMP3_I4
-
51
81
[2]
PIO1_8/ACMP3_I3/
SCT3_OUT4
-
53
84
[2]
PIO1_9/ACMP2_I4
-
54
85
[2]
I; PU
A
ADC0_9 — ADC0 input 9.
IO
PIO1_0 — General purpose port 1 input/output 0.
A
ADC0_8 — ADC0 input 8.
IO
PIO1_1 — General purpose port 1 input/output 1.
A
ADC1_0 — ADC1 input 0.
IO
PIO1_2 — General purpose port 1 input/output 2.
A
ADC1_4 — ADC1 input 4.
IO
PIO1_3 — General purpose port 1 input/output 3.
A
ADC1_5 — ADC1 input 5.
IO
PIO1_4 — General purpose port 1 input/output 4.
A
ADC1_10 — ADC1 input 10.
IO
PIO1_5 — General purpose port 1 input/output 5.
A
ADC1_11 — ADC1 input 11.
IO
PIO1_6 — General purpose port 1 input/output 6.
A
ACMP_I2 — Analog comparator common input 2.
IO
PIO1_7 — General purpose port 1 input/output 7.
A
ACMP3_I4 — Analog comparator 3 input 4.
IO
PIO1_8 — General purpose port 1 input/output 8.
A
ACMP3_I3 — Analog comparator 3 input 3.
O
SCT3_OUT4 — SCTimer3/PWM output 4.
IO
PIO1_9 — General purpose port 1 input/output 9.
On the LQFP64 package, this is the ISP_0 boot pin.
A
PIO1_10/ACMP1_I4
PIO1_11
-
59
38
91
58
[2]
[5]
I; PU
I; PU
ACMP2_I4 — Analog comparator 2 input 4.
IO
PIO1_10 — General purpose port 1 input/output 10.
A
ACMP1_I4 — Analog comparator 1 input 4.
IO
PIO1_11 — General purpose port 1 input/output 11.
On the LQFP64 package, this is the ISP_1 boot pin.
LPC15XX
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 107
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
PIO1_12
LQFP100
Symbol
LQFP64
Pin description with fixed-pin functions
LQFP48
Table 3.
-
-
9
Reset Type
state[1]
Description
[5]
I; PU
IO
PIO1_12 — General purpose port 1 input/output 12.
I; PU
IO
PIO1_13 — General purpose port 1 input/output 13.
I; PU
IO
PIO1_14 — General purpose port 1 input/output 14.
O
SCT0_OUT7 — SCTimer0/PWM output 7.
PIO1_13
-
-
11
[5]
PIO1_14/SCT0_OUT7
-
-
12
[5]
15
[5]
I; PU
IO
PIO1_15 — General purpose port 1 input/output 15.
I; PU
IO
PIO1_16 — General purpose port 1 input/output 16.
I; PU
IO
PIO1_17 — General purpose port 1 input/output 17.
O
SCT1_OUT7 — SCTimer1/PWM output 7.
PIO1_15
-
-
PIO1_16
-
-
18
[5]
PIO1_17/SCT1_OUT7
-
-
20
[5]
25
[5]
I; PU
IO
PIO1_18 — General purpose port 1 input/output 18.
I; PU
IO
PIO1_19 — General purpose port 1 input/output 19.
I; PU
IO
PIO1_20 — General purpose port 1 input/output 20.
O
SCT2_OUT5 — SCTimer2/PWM output 5.
PIO1_18
-
-
PIO1_19
-
-
29
[5]
PIO1_20/SCT2_OUT5
-
-
34
[5]
37
[5]
I; PU
IO
PIO1_21 — General purpose port 1 input/output 21.
PIO1_21
-
-
PIO1_22
-
-
38
[5]
I; PU
IO
PIO1_22 — General purpose port 1 input/output 22.
PIO1_23
-
-
42
[5]
I; PU
IO
PIO1_23 — General purpose port 1 input/output 23.
44
[5]
I; PU
IO
PIO1_24 — General purpose port 1 input/output 24.
O
SCT3_OUT5 — SCTimer3/PWM output 5.
PIO1_24/SCT3_OUT5
-
-
PIO1_25
-
-
46
[5]
I; PU
IO
PIO1_25 — General purpose port 1 input/output 25.
PIO1_26
-
-
48
[5]
I; PU
IO
PIO1_26 — General purpose port 1 input/output 26.
50
[5]
I; PU
IO
PIO1_27 — General purpose port 1 input/output 27.
55
[5]
I; PU
IO
PIO1_28 — General purpose port 1 input/output 28.
PIO1_27
PIO1_28
-
-
PIO1_29
-
-
56
[5]
I; PU
IO
PIO1_29 — General purpose port 1 input/output 29.
PIO1_30
-
-
59
[5]
I; PU
IO
PIO1_30 — General purpose port 1 input/output 30.
60
[5]
I; PU
IO
PIO1_31 — General purpose port 1 input/output 31.
62
[5]
I; PU
IO
PIO2_0 — General purpose port 2 input/output 0.
PIO1_31
PIO2_0
-
-
PIO2_1
-
-
64
[5]
I; PU
IO
PIO2_1 — General purpose port 2 input/output 1.
PIO2_2
-
-
72
[5]
I; PU
IO
PIO2_2 — General purpose port 2 input/output 2.
76
[5]
I; PU
IO
PIO2_3 — General purpose port 2 input/output 3.
77
[5]
I; PU
IO
PIO2_4 — General purpose port 2 input/output 4.
I; PU
IO
I; PU
IO
PIO2_3
PIO2_4
-
-
On the LQFP100 package, this is the ISP_1 boot pin.
PIO2_5
-
-
80
[5]
PIO2_6
-
-
82
[5]
PIO2_5 — General purpose port 2 input/output 5.
On the LQFP100 package, this is the ISP_0 boot pin.
PIO2_6 — General purpose port 2 input/output 6.
On the LQFP100 package, this pin is assigned to U0_TXD
in ISP USART mode.
PIO2_7
-
-
86
[5]
I; PU
IO
PIO2_7 — General purpose port 2 input/output 7.
On the LQFP100 package, this pin is assigned to
U0_RXD in ISP USART mode.
LPC15XX
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
16 of 107
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
PIO2_8
LQFP100
Symbol
LQFP64
Pin description with fixed-pin functions
LQFP48
Table 3.
-
-
92
[5]
Reset Type
state[1]
Description
I; PU
PIO2_8 — General purpose port 2 input/output 8.
IO
On the LQFP100 package, this pin is assigned to
CAN0_TD in ISP C_CAN mode.
PIO2_9
-
-
94
[5]
I; PU
IO
PIO2_9 — General purpose port 2 input/output 9.
On the LQFP100 package, this pin is assigned to
CAN0_RD in ISP C_CAN mode.
PIO2_10
-
-
96
[5]
I; PU
IO
PIO2_10 — General purpose port 2 input/output 10.
PIO2_11
-
-
99
[5]
I; PU
IO
PIO2_11 — General purpose port 2 input/output 11.
PIO2_12
35
47
74
[5]
I; PU
IO
PIO2_12 — General purpose port 2 input/output 12. On
parts LPC1519/17/18 only.
PIO2_13
36
48
75
[5]
I; PU
IO
PIO2_13 — General purpose port 2 input/output 13. On
parts LPC1519/17/18 only.
USB_DP
35
47
74
[10]
-
IO
USB bidirectional D+ line. Pad includes internal 33 Ω
series termination resistor. On parts LPC1549/48/47 only.
USB_DM
36
48
75
[10]
-
IO
USB bidirectional D line. Pad includes internal 33 Ω
series termination resistor. On parts LPC1549/48/47 only.
RTCXIN
31
42
66
[9]
-
RTC oscillator input. This input should be grounded if the
RTC is not used.
RTCXOUT
32
43
67
[9]
-
RTC oscillator output.
54
[9]
-
Input to the oscillator circuit and internal clock generator
circuits. Input voltage must not exceed 1.8 V.
-
Output from the oscillator amplifier.
XTALIN
26
36
[11]
XTALOUT
25
35
53
[9]
[11]
VBAT
30
41
65
-
Battery supply voltage. Supplies power to the RTC. If no
battery is used, tie VBAT to VDD or to ground.
VDDA
16
20
30
-
Analog supply voltage. VDD and the analog reference
voltages VREFP_ADC and VREFP_DAC_VDDCMP must
not exceed the voltage level on VDDA. VDDAshould typically
be the same voltages as VDD but should be isolated to
minimize noise and error. VDDA should be tied to VDD if the
ADC is not used.
VDD
39,
27,
42
22,
52,
37,
57
4,
32,
70,
83,
57,
89
-
3.3 V supply voltage (2.4 V to 3.6 V). The voltage level on
VDD must be equal or lower than the analog supply
voltage VDDA.
VREFP_DAC_VDDCMP 14
18
27
-
DAC positive reference voltage and analog comparator
reference voltage. The voltage level on
VREFP_DAC_VDDCMP must be equal to or lower than
the voltage applied to VDDA.
VREFN
14
22
-
ADC and DAC negative voltage reference. If the ADC is
not used, tie VREFN to VSS.
LPC15XX
Product data sheet
11
[9]
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
17 of 107
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
LQFP64
LQFP100
Pin description with fixed-pin functions
LQFP48
Table 3.
Symbol
Reset Type
state[1]
Description
VREFP_ADC
10
13
21
-
ADC positive reference voltage. The voltage level on
VREFP_ADC must be equal to or lower than the voltage
applied to VDDA. If the ADC is not used, tie VREFP_ADC
to VDD.
VSSA
17
21
31
-
Analog ground. VSSAshould typically be the same voltage
as VSS but should be isolated to minimize noise and error.
VSSA should be tied to VSS if the ADC is not used.
VSS
41,
20,
40
56,
26,
27,
55
88,
7,
39,
40,
68,
87
-
Ground.
[1]
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.
[2]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as analog input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin includes a 10 ns on/off
glitch filter. By default, the glitch filter is turned on.
[3]
This pin is not 5 V tolerant due to special analog functionality. When configured for a digital function, this pin is 3 V tolerant and provides
standard digital I/O functions with configurable internal pull-up and pull-down resistors and hysteresis. When configured for DAC_OUT,
the digital section of the pin is disabled and this pin is a 3 V tolerant analog output. This pin includes a 10 ns on/off glitch filter. By default,
the glitch filter is turned on.
[4]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, and configurable hysteresis. This pin
includes a 10 ns on/off glitch filter. By default, the glitch filter is turned on. This pin is powered in deep power-down mode and can wake
up the part. The wake-up pin function can be disabled and the pin can be used for other purposes, if the RTC is enabled for waking up
the part from Deep power-down mode.
[5]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[6]
5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.
[7]
I2C-bus pin compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. The pin requires an
external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines.
Open-drain configuration applies to all functions on this pin.
[8]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes
high-current output driver.
[9]
Special analog pin.
[10] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only). This pad is not 5 V tolerant.
[11] When the main oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
Table 4.
LPC15XX
Product data sheet
Movable functions
Function name
Type
Description
U0_TXD
O
Transmitter output for USART0.
U0_RXD
I
Receiver input for USART0.
U0_RTS
O
Request To Send output for USART0.
U0_CTS
I
Clear To Send input for USART0.
U0_SCLK
I/O
Serial clock input/output for USART0 in synchronous mode.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
18 of 107
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Table 4.
LPC15XX
Product data sheet
Movable functions …continued
Function name
Type
Description
U1_TXD
O
Transmitter output for USART1.
U1_RXD
I
Receiver input for USART1.
U1_RTS
O
Request To Send output for USART1.
U1_CTS
I
Clear To Send input for USART1.
U1_SCLK
I/O
Serial clock input/output for USART1 in synchronous mode.
U2_TXD
O
Transmitter output for USART2.
U2_RXD
I
Receiver input for USART2.
U2_SCLK
I/O
Serial clock input/output for USART1 in synchronous mode.
SPI0_SCK
I/O
Serial clock for SPI0.
SPI0_MOSI
I/O
Master Out Slave In for SPI0.
SPI0_MISO
I/O
Master In Slave Out for SPI0.
SPI0_SSEL0
I/O
Slave select 0 for SPI0.
SPI0_SSEL1
I/O
Slave select 1 for SPI0.
SPI0_SSEL2
I/O
Slave select 2 for SPI0.
SPI0_SSEL3
I/O
Slave select 3 for SPI0.
SPI1_SCK
I/O
Serial clock for SPI1.
SPI1_MOSI
I/O
Master Out Slave In for SPI1.
SPI1_MISO
I/O
Master In Slave Out for SPI1.
SPI1_SSEL0
I/O
Slave select 0 for SPI1.
SPI1_SSEL1
I/O
Slave select 1 for SPI1.
CAN0_TD
O
CAN0 transmit.
CAN0_RD
I
CAN0 receive.
USB_VBUS
I
USB VBUS.
SCT0_OUT0
O
SCTimer0/PWM output 0.
SCT0_OUT1
O
SCTimer0/PWM output 1.
SCT0_OUT2
O
SCTimer0/PWM output 2.
SCT1_OUT0
O
SCTimer1/PWM output 0.
SCT1_OUT1
O
SCTimer1/PWM output 1.
SCT1_OUT2
O
SCTimer1/PWM output 2.
SCT2_OUT0
O
SCTimer2/PWM output 0.
SCT2_OUT1
O
SCTimer2/PWM output 1.
SCT2_OUT2
O
SCTimer2/PWM output 2.
SCT3_OUT0
O
SCTimer3/PWM output 0.
SCT3_OUT1
O
SCTimer3/PWM output 1.
SCT3_OUT2
O
SCTimer3/PWM output 2.
SCT_ABORT0
I
SCT abort 0.
SCT_ABORT1
I
SCT abort 1.
ADC0_PINTRIG0
I
ADC0 external pin trigger input 0.
ADC0_PINTRIG1
I
ADC0 external pin trigger input 1.
ADC1_PINTRIG0
I
ADC1 external pin trigger input 0.
ADC1_PINTRIG1
I
ADC1 external pin trigger input 1.
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Table 4.
Movable functions …continued
Function name
Type
Description
DAC_PINTRIG
I
DAC external pin trigger input.
DAC_SHUTOFF
I
DAC shut-off external input.
ACMP0_O
O
Analog comparator 0 output.
ACMP1_O
O
Analog comparator 1 output.
ACMP2_O
O
Analog comparator 2 output.
ACMP3_O
O
Analog comparator 3 output.
CLKOUT
O
Clock output.
ROSC
O
Analog comparator ring oscillator output.
ROSC_RESET
I
Analog comparator ring oscillator reset.
USB_FTOGGLE
O
USB frame toggle. Do not assign this function to a pin until a USB
device is connected and the first SOF interrupt has been received
by the device.
QEI_PHA
I
QEI phase A input.
QEI_PHB
I
QEI phase B input.
QEI_IDX
I
QEI index input.
GPIO_INT_BMAT
O
Output of the pattern match engine.
SWO
O
Serial wire output.
LQFP48
LQFP100
Pins connected to the INPUT multiplexer and SCT IPU
Symbol
LQFP64
Table 5.
Description
PIO0_2/ADC0_6/SCT1_OUT3
3
6
8
SCT0 input multiplexer
PIO0_3/ADC0_5/SCT1_OUT4
4
7
10
SCT0 input multiplexer
PIO0_4/ADC0_4
5
8
13
SCT2 input multiplexer
PIO0_5/ADC0_3
6
9
14
FREQMEAS
PIO0_7/ADC0_1
8
11
17
SCT3 input multiplexer
PIO0_14/ADC1_7/SCT1_OUT5
22
30
45
SCTIPU input SAMPLE_IN_A0
PIO0_15/ADC1_8
23
31
47
SCT1 input multiplexer
PIO0_16/ADC1_9
24
32
49
SCT1 input multiplexer
PIO0_17/WAKEUP/TRST
28
39
61
SCT0 input multiplexer
SWCLK/PIO0_19/TCK
29
40
63
FREQMEAS
RESET/PIO0_21
34
45
71
SCT1 input multiplexer
PIO0_25/ACMP0_I4
44
60
93
SCTIPU input SAMPLE_IN_A1
PIO0_27/ACMP_I1
46
62
97
SCT2 input multiplexer
PIO0_30/ADC0_11
-
1
1
FREQMEAS
SCT0 input multiplexer
LPC15XX
Product data sheet
PIO0_31/ADC0_9
-
3
3
SCT1 input multiplexer
PIO1_4/ADC1_10
-
33
51
SCT1 input multiplexer
PIO1_5/ADC1_11
-
34
52
SCT1 input multiplexer
PIO1_6/ACMP_I2
-
46
73
SCT0 input multiplexer
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LQFP64
LQFP100
Pins connected to the INPUT multiplexer and SCT IPU
LQFP48
Table 5.
Symbol
Description
PIO1_7/ACMP3_I4
-
51
81
SCT0 input multiplexer
PIO1_11
-
38
58
SCT3 input multiplexer
SCTIPU input SAMPLE_IN_A2
PIO1_12
-
-
9
SCT0 input multiplexer
PIO1_13
-
-
11
SCT0 input multiplexer
PIO1_15
-
-
12
SCT1 input multiplexer
PIO1_16
-
-
18
SCT1 input multiplexer
PIO1_18
-
-
25
SCT2 input multiplexer
PIO1_19
-
-
29
SCT2 input multiplexer
PIO1_21
-
-
37
SCT3 input multiplexer
PIO1_22
-
-
38
SCT3 input multiplexer
PIO1_26
-
-
48
SCTIPU input SAMPLE_IN_A3
PIO1_27
-
-
50
FREQMEAS
8. Functional description
8.1 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware division,
hardware single-cycle multiply, interruptible/continuable multiple load and store
instructions, automatic state save and restore for interrupts, tightly integrated interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual, which is available on the official ARM website.
8.2 Memory Protection Unit (MPU)
The LPC15xx have a Memory Protection Unit (MPU) which can be used to improve the
reliability of an embedded system by protecting critical data within the user application.
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
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The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions each of which can
be divided into eight subregions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will cause the Memory Management
Fault exception to take place.
8.3 On-chip flash programming memory
The LPC15xx contain up to 256 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip boot loader software. Flash updates via USB are supported as well.
The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages.
Individual pages of 256 byte each can be erased using the IAP erase page command.
8.3.1 ISP pin configuration
The LPC15xx supports ISP via the USART0, C_CAN, or USB interfaces. The ISP mode is
determined by the state of two pins (ISP_0 and ISP_1) at boot time:
Table 6.
ISP modes
Boot mode
ISP_0
ISP_1
Description
No ISP
HIGH
HIGH
ISP bypassed. Part attempts to boot
from flash. If the user code in flash is
not valid, then enters ISP via USB.
C_CAN
HIGH
LOW
Part enters ISP via C_CAN.
USB
LOW
HIGH
Part enters ISP via USB.
USART0
LOW
LOW
Part enters ISP via USART0.
The ISP pin assignment is different for each package, so that the fewest functions
possible are blocked. No more than four pins must be set aside for entering ISP in any
ISP mode. The boot code assigns two ISP pins for each package, which are probed when
the part boots to determine whether or not to enter ISP mode. Once the ISP mode has
been determined, the boot loader configures the necessary serial pins for each package.
Pins which are not configured by the boot loader for the selected boot mode (for example
CAN0_RD and CAN0_TD in USART mode) can be assigned to any function through the
switch matrix.
Table 7.
Pin assignments for ISP modes
Boot pin
LQFP48
LQFP64
LQFP100
ISP_0
PIO0_4
PIO1_9
PIO2_5
ISP_1
PIO0_16
PIO1_11
PIO2_4
U0_TXD
PIO0_15
PIO0_18
PIO2_6
U0_RXD
PIO0_14
PIO0_13
PIO2_7
CAN0_TD
PIO0_18
PIO0_31
PIO2_8
CAN0_RD
PIO0_13
PIO0_11
PIO2_9
PIO0_16
PIO1_11
PIO2_4
USART mode
C_CAN mode
USB mode
USB_VBUS (same as ISP_1)
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8.4 EEPROM
The LPC15xx contain 4 kB of on-chip byte-erasable and byte-programmable EEPROM
data memory. The EEPROM can be programmed using In-Application Programming (IAP)
via the on-chip boot loader software.
8.5 SRAM
The LPC15xx contain a total 36 kB, 20 kB or 12 kB of contiguous, on-chip static RAM
memory. For each SRAM configuration, the SRAM is divided into three blocks: 2 x 16 kB +
4 kB for 36 kB SRAM, 2 x 8 kB + 4 kB for 20 kB SRAM, and 2 x 4 kB + 4 kB for 12 kB
SRAM. The bottom 16 kB, 8 kB, or 4 kB are enabled by the bootloader and cannot be
disabled. The next two SRAM blocks in each configuration can be disabled or enabled
individually in the SYSCON block to save power.
Table 8.
LPC15xx SRAM configurations
SRAM0
SRAM1
SRAM2
LPC1549/19 (total SRAM = 36 kB)
address range
0x0200 0000 to
0x0200 3FFF
0x0200 4000 to
0x0200 7FFF
0x0200 8000 to
0x0200 8FFF
size
16 kB
16 kB
4 kB
control
cannot be disabled
disable/enable
disable/enable
default
enabled
enabled
enabled
LPC1548/18 (total SRAM = 20 kB)
address range
0x0200 0000 to
0x0200 1FFF
0x0200 2000 to
0x0200 3FFF
0x0200 4000 to
0x0200 4FFF
size
8 kB
8 kB
4 kB
control
cannot be disabled
disable/enable
disable/enable
default
enabled
enabled
enabled
LPC1547/17 (total SRAM = 12 kB)
address range
0x0200 0000 to
0x0200 0FFF
0x0200 1000 to
0x0200 1FFF
0x0200 2000 to
0x0200 2FFF
size
4 kB
4 kB
4 kB
control
cannot be disabled
disable/enable
disable/enable
default
enabled
enabled
enabled
8.6 On-chip ROM
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
including IAP erase page command.
•
•
•
•
•
LPC15XX
Product data sheet
IAP support for EEPROM.
Flash updates via USB and C_CAN supported.
USB API (HID, CDC, and MSC drivers).
DMA, I2C, USART, SPI, and C_CAN drivers.
Power profiles for configuring power consumption and PLL settings.
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• Power mode configuration for configuring deep-sleep, power-down, and deep
power-down modes.
• ADC drivers for analog-to-digital conversion and ADC calibration.
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8.7 AHB multilayer matrix
TEST/DEBUG
INTERFACE
ARM
CORTEX-M3
System
bus
I-code
bus
USB
DMA
masters
D-code
bus
slaves
FLASH
SRAM0
SRAM1
SRAM2
ROM
EEPROM
HS GPIO
SCTIMER0/PWM
SCTIMER1/PWM
SCTIMER2/PWM
SCTIMER3/PWM
CRC
AHB-TO-APB
BRIDGE0
WWDT
SWM
PMU
SPI1
AHB MULTILAYER MATRIX
ACMP
DAC
ADC0
INPUT MUX
USART1
I2C0
QEI
USART2
RTC
SPI0
SYSCON
AHB-TO-APB
BRIDGE1
RIT
PINT
MRT
ADC1
SCTIPU
IOCON
FLASH CTRL
GINT0
GINT1
USART2
C_CAN
EEPROM CTRL
= master-slave connection
aaa-010870
Fig 9.
AHB multilayer matrix
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8.8 Memory map
APB peripherals
0x400F 0000
31
EEPROM CTRL
30
IOCON
29
reserved
28
C_CAN
27
reserved
26
reserved
0xE010 0000
25:17
reserved
0xE000 0000
16
USART2
15
flash ctrl FMC
14
SCTIPU
13
RIT
12
reserved
11
GINT1
10
GINT0
9
PINT
8
MRT
LPC15xx
4 GB
0xFFFF FFFF
reserved
private peripheral bus
reserved
0x400F 0000
APB peripherals 1
0x4008 0000
APB peripherals 0
0x4000 0000
reserved
0x1C02 8000
SCTimer3/PWM
0x1C02 4000
SCTimer2/PWM
SCTimer1/PWM
SCTimer0/PWM
reserved
CRC
USB
reserved
DMA
GPIO
reserved
0x400E 8000
0x400C 4000
0x400C 0000
0x400B 4000
0x400B 0000
0x400A C000
0x400A 8000
0x400A 4000
0x400A 0000
reserved
31:30
reserved
29
SYSCON
28:23
reserved
0x4008 4000
ADC1
0x4008 0000
0x4008 0000
0x4007 8000
22
QEI
0x1C00 C000
21
reserved
0x1C00 8000
20
I2C0
0x1C00 4000
19
SPI1
0x1C00 0000
18
SPI0
17
USART1
16
USART0
15
PMU
14
switch matrix SWM
0x4005 8000
0x4005 4000
0x4005 0000
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
reserved
0x0300 8000
13:12
0x0300 0000
11
WWDT
10
RTC
9:7
reserved
6
reserved
5
INPUT MUX
0x0200 9000
36 kB SRAM (LPC1549/19)
0x0200 5000
20 kB SRAM (LPC1548/18)
0x4002 C000
0x4002 8000
0x4001 C000
0x4001 8000
4:3
0x0200 0000
2
analog comparators ACMP
1
DAC
0
ADC0
reserved
0x0004 0000
reserved
256 kB flash
0x4003 8000
0x4003 0000
0x0200 3000
12 kB SRAM (LPC1547/17)
0x4007 4000
0x4005 C000
0x1C01 0000
0x0320 0000
0x400B C000
0x400B 8000
0x1C01 8000
reserved
0x4001 4000
0x4000 C000
0x4000 8000
0x4000 4000
0x4000 0000
0x0000 00C0
active interrupt vectors
0 GB
0x400E C000
0
reserved
32 kB boot ROM
0x400F 0000
0x1C01 C000
0x0320 1000
4 kB EEPROM
0x400F 4000
7:1
0x1000 0000
reserved
0x400F 8000
0x1C02 0000
0x1C01 4000
0x400F C000
0x0000 0000
0x0000 0000
aaa-010871
See Section 8.5 “SRAM” for SRAM configuration.
Fig 10. Memory map
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8.9 Nested Vectored Interrupt controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M3. The tight
coupling to the CPU allows for low interrupt latency and efficient processing of late arriving
interrupts.
8.9.1 Features
•
•
•
•
•
•
•
•
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3.
Tightly coupled interrupt controller provides low interrupt latency.
Controls system exceptions and peripheral interrupts.
The NVIC supports 47 vectored interrupts.
Eight programmable interrupt priority levels with hardware priority level masking.
Software interrupt generation using the ARM exceptions SVCall and PendSV.
Support for NMI.
ARM Cortex-M3 Vector table offset register VTOR implemented.
8.9.2 Interrupt sources
Typically, each peripheral device has one interrupt line connected to the NVIC but can
have several interrupt flags. Individual interrupt flags can also represent more than one
interrupt source.
8.10 IOCON block
The IOCON block configures the electrical properties of the pins such as pull-up and
pull-down resistors, hysteresis, open-drain modes and input filters.
Remark: The pin function and whether the pin operates in digital or analog mode are
entirely under the control of the switch matrix.
Enabling an analog function through the switch matrix disables the digital pad. However,
the internal pull-up and pull-down resistors as well as the pin hysteresis must be disabled
to obtain an accurate reading of the analog input.
8.10.1 Features
• Programmable pull-up, pull-down, or repeater mode.
• All pins (except PIO0_22 and PIO0_23) are pulled up to 3.3 V (VDD = 3.3 V) if their
pull-up resistor is enabled.
• Programmable pseudo open-drain mode.
• Programmable (on/off) 10 ns glitch filter on 36 pins (PIO0_0 to PIO0_17, PIO0_25 to
PIO0_31, PIO1_0 to PIO1_10). The glitch filter is turned on by default.
• Programmable hysteresis.
• Programmable input inverter.
• Digital filter with programmable filter constant on all pins.
8.10.2 Standard I/O pad configuration
Figure 11 shows the possible pin modes for standard I/O pins with analog input function:
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•
•
•
•
•
•
•
Digital output driver with configurable open-drain output
Digital input: Weak pull-up resistor (PMOS device) enabled/disabled
Digital input: Weak pull-down resistor (NMOS device) enabled/disabled
Digital input: Repeater mode enabled/disabled
Digital input: Input digital filter configurable on all pins
Digital input: Input glitch filter enabled/disabled on select pins
Analog input
VDD
VDD
open-drain enable
strong
pull-up
output enable
ESD
data output
PIN
pin configured
as digital output
driver
strong
pull-down
ESD
VSS
VDD
weak
pull-up
pull-up enable
weak
pull-down
repeater mode
enable
pull-down enable
PROGRAMMABLE
DIGITAL FILTER
data input
pin configured
as digital input
10 ns GLITCH
FILTER
select data
inverter
select glitch
filter
select analog input
analog input
pin configured
as analog input
aaa-010776
Fig 11. Standard I/O pin configuration
8.11 Switch Matrix (SWM)
The switch matrix controls the function of each digital or mixed analog/digital pin in a
highly flexible way by allowing to connect many functions like the USART, SPI, SCT, and
I2C functions to any pin that is not power or ground. These functions are called movable
functions and are listed in Table 4.
Functions that need specialized pads like the ADC or analog comparator inputs can be
enabled or disabled through the switch matrix. These functions are called fixed-pin
functions and cannot move to other pins. The fixed-pin functions are listed in Table 3. If a
fixed-pin function is disabled, any other movable function can be assigned to this pin.
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8.12 Fast General-Purpose parallel I/O (GPIO)
Device pins that are not connected to a specific peripheral function through the switch
matrix are controlled by the GPIO registers. Pins may be dynamically configured as inputs
or outputs. Multiple outputs can be set or cleared in one write operation.
LPC15xx use accelerated GPIO functions.
• An entire port value can be written in one instruction.
• Mask, set, and clear operations are supported for the entire port.
8.12.1 Features
• Bit level port registers allow a single instruction to set and clear any number of bits in
one write operation.
• Direction control of individual bits.
8.13 Pin interrupt/pattern match engine (PINT)
The pin interrupt block configures up to eight pins from the digital pins on ports 1 and 2 for
providing eight external interrupts connected to the NVIC. The input multiplexer block is
used to select the pins.
The pattern match engine can be used, in conjunction with software, to create complex
state machines based on pin inputs.
Any digital pin on ports 0 and 1 can be configured through the SYSCON block as input to
the pin interrupt or pattern match engine. The registers that control the pin interrupt or
pattern match engine are located on the IO+ bus for fast single-cycle access.
8.13.1 Features
• Pin interrupts
– Up to eight pins can be selected from all digital pins on ports 0 and 1 as edge- or
level-sensitive interrupt requests. Each request creates a separate interrupt in the
NVIC.
– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
– Level-sensitive interrupt pins can be HIGH- or LOW-active.
– Pin interrupts can wake up the part from sleep mode, deep-sleep mode, and
power-down mode.
• Pin interrupt pattern match engine
– Up to 8 pins can be selected from all digital pins on ports 0 and 1 to contribute to a
boolean expression. The boolean expression consists of specified levels and/or
transitions on various combinations of these pins.
– Each minterm (product term) comprising the specified boolean expression can
generate its own, dedicated interrupt request.
– Any occurrence of a pattern match can be programmed to also generate an RXEV
notification to the ARM CPU.
– The pattern match engine does not facilitate wake-up.
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8.14 GPIO group interrupts (GINT0/1)
The GPIO pins can be used in several ways to set pins as inputs or outputs and use the
inputs as combinations of level and edge sensitive interrupts. For each port/pin connected
to one of the two the GPIO Grouped Interrupt blocks (GINT0 and GINT1), the GPIO
grouped interrupt registers determine which pins are enabled to generate interrupts and
what the active polarities of each of those inputs are.
The GPIO grouped interrupt registers also select whether the interrupt output will be level
or edge triggered and whether it will be based on the OR or the AND of all of the enabled
inputs.
When the designated pattern is detected on the selected input pins, the GPIO grouped
interrupt block generates an interrupt. If the part is in a power-savings mode, it first
asynchronously wakes the part up prior to asserting the interrupt request. The interrupt
request line can be cleared by writing a one to the interrupt status bit in the control
register.
8.14.1 Features
• Two group interrupts are supported to reflect two distinct interrupt patterns.
• The inputs from any number of digital pins can be enabled to contribute to a combined
group interrupt.
• The polarity of each input enabled for the group interrupt can be configured HIGH or
LOW.
• Enabled interrupts can be logically combined through an OR or AND operation.
• The grouped interrupts can wake up the part from sleep, deep-sleep or power-down
modes.
8.15 DMA controller
The DMA controller can access all memories and the USART, SPI, I2C, and DAC
peripherals using DMA requests. DMA transfers can also be triggered by internal events
like the ADC interrupts, the SCT DMA request signals, or the analog comparator outputs.
8.15.1 Features
• 18 channels with 14 channels connected to peripheral request inputs.
• DMA operations can be triggered by on-chip events. Each DMA channel can select
one trigger input from 24 sources through the input multiplexer.
•
•
•
•
•
•
LPC15XX
Product data sheet
Priority is user selectable for each channel.
Continuous priority arbitration.
Address cache with four entries.
Efficient use of data bus.
Supports single transfers up to 1,024 words.
Address increment options allow packing and/or unpacking data.
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8.16 Input multiplexing (Input mux)
The input multiplexer allows to select from multiple external and internal sources for the
SCT inputs, DMA trigger inputs, and the frequency measure block. The input multiplexer
is implemented as a register interface with one source selection register for each input.
The input multiplexer can for example connect SCT outputs, the ADC interrupts, or the
comparator outputs to the SCT inputs and thus enables the SCT to use a large variety of
events to control the timing operation.
The ADCs and analog comparators also support input multiplexing using source selection
registers as part of their configuration registers.
8.17 USB interface
Remark: The USB interface is available on parts LPC1549/48/47 only.
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The USB interface consists of a full-speed device controller with on-chip PHY (PHYsical
layer) for device functions.
Remark: Configure the part in default power mode with the power profiles before using
the USB (see Section 8.40.1). Do not use the USB when the part runs in performance,
efficiency, or low-power mode.
8.17.1 Full-speed USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
8.17.1.1
Features
•
•
•
•
•
•
Dedicated USB PLL available.
Fully compliant with USB 2.0 specification (full speed).
Supports 10 physical (5 logical) endpoints including one control endpoint.
Single and double buffering supported.
Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
Supports wake-up from Deep-sleep mode and Power-down mode on USB activity
and remote wake-up.
• Supports SoftConnect functionality through internal pull-up resistor.
• Internal 33 Ω series termination resistors on USB_DP and USB_DM lines eliminate
the need for external series resistors.
• Supports Link Power Management (LPM).
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8.18 USART0/1/2
Remark: All USART functions are movable functions and are assigned to pins through
the switch matrix. Do not connect USART functions to the open-drain pins PIO0_22 and
PIO0_23.
Interrupts generated by the USART peripherals can wake up the part from Deep-sleep
and power-down modes if the USART is in synchronous mode, the 32 kHz mode is
enabled, or the CTS interrupt is enabled.
8.18.1 Features
• Maximum bit rates of 4.5 Mbit/s in asynchronous mode, 15 Mbit/s in synchronous
mode master mode, and 18 Mbit/s in synchronous slave mode.
• 7, 8, or 9 data bits and 1 or 2 stop bits.
• Synchronous mode with master or slave operation. Includes data phase selection and
continuous clock option.
•
•
•
•
•
•
•
Multiprocessor/multidrop (9-bit) mode with software address compare.
•
•
•
•
•
•
Received data and status can optionally be read from a single register
RS-485 transceiver output enable.
Autobaud mode for automatic baud rate detection
Parity generation and checking: odd, even, or none.
Software selectable oversampling from 5 to 16 clocks in asynchronous mode.
One transmit and one receive data buffer.
RTS/CTS for hardware signaling for automatic flow control. Software flow control can
be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an
RTS output.
Break generation and detection.
Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.
Built-in Baud Rate Generator with auto-baud function.
A fractional rate divider is shared among all USARTs.
Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in
receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS
detect, and receiver sample noise detected.
• Loopback mode for testing of data and flow control.
• In synchronous slave mode, wakes up the part from deep-sleep and power-down
modes.
• Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC
oscillator as the UART clock. This mode can be used while the device is in
Deep-sleep or Power-down mode and can wake-up the device when a character is
received.
• USART transmit and receive functions work with the system DMA controller.
8.19 SPI0/1
All SPI functions are movable functions and are assigned to pins through the switch
matrix. Do not connect SPI functions to the open-drain pins PIO0_22 and PIO0_23.
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8.19.1 Features
• Maximum data rates of 17 Mbit/s in master mode and slave mode for SPI functions
connected to all digital pins except PIO0_22 and PIO0_23.
• Data transmits of 1 to 16 bits supported directly. Larger frames supported by software.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data. This can
be useful while setting up an SPI memory.
• Control information can optionally be written along with data. This allows very
versatile operation, including “any length” frames.
• Up to four Slave Select input/outputs with selectable polarity and flexible usage.
• Supports DMA transfers: SPIn transmit and receive functions work with the system
DMA controller.
Remark: Texas Instruments SSI and National Microwire modes are not supported.
8.20 I2C-bus interface
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
The I2C-bus functions are fixed-pin functions and must be enabled through the switch
matrix on the open-drain pins PIO0_22 and PIO0_23.
8.20.1 Features
• Supports standard and fast mode with data rates of up to 400 kbit/s.
• Supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Fail-safe operation: When the power to an I2C-bus device is switched off, the SDA
and SCL pins connected to the I2C-bus are floating and do not disturb the bus.
•
•
•
•
Independent Master, Slave, and Monitor functions.
Supports both Multi-master and Multi-master with Slave functions.
Multiple I2C slave addresses supported in hardware.
One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I2C bus addresses.
• 10-bit addressing supported with software assist.
• Supports SMBus.
• Supported by on-chip ROM API.
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8.21 C_CAN
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller can build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a high level of reliability.
The C_CAN functions are movable functions and are assigned to pins through the switch
matrix. Do not connect C_CAN functions to the open-drain pins PIO0_22 and PIO0_23.
8.21.1 Features
•
•
•
•
•
•
•
Conforms to protocol version 2.0 parts A and B.
Supports bit rate of up to 1 Mbit/s.
Supports 32 Message Objects.
Each Message Object has its own identifier mask.
Provides programmable FIFO mode (concatenation of Message Objects).
Provides maskable interrupts.
Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
• Provides programmable loop-back mode for self-test operation.
8.22 PWM/timer/motor control subsystem
The SCTimer/PWMs (State Configurable Timer/Pulse Width Modulators) and the analog
peripherals support multiple ways of interconnecting their inputs and outputs and of
interfacing to the pins and the DMA controller. Using the highly flexible and programmable
connection scheme makes it easy to configure various subsystems for motor control and
complex timing and tracking applications. Specifically, the inputs to the SCTs and the
trigger inputs of the ADCs and DMA are selected through the input multiplexer which
offers a choice of many possible sources for each input or trigger. SCT outputs are
assigned to pins through the switch matrix allowing for many pinout solutions.
8.22.1 SCtimer/PWM subsystem
The SCTimer/PWMs can be configured to build a PWM controller with multiple outputs by
programming the MATCH and MATCHRELOAD registers to control the base frequency
and the duty cycle of each SCTimer/PWM output. More complex waveforms that span
multiple counter cycles or change behavior across or within counter cycles can be
generated using the state capability built into the SCTimer/PWMs.
Combining the PWM functions with the analog functions, the PWM output can react to
control signals like comparator outputs or the ADC interrupts. The SCT IPU adds
emergency shut-down functions and pre-processing of controlling events. For an overview
of the PWM subsystem, see Figure 12 “PWM-Analog subsystem”.
For high-speed PWM functionality, use only outputs that are fixed-pin functions to
minimize pin-to-pin differences in output skew. See also Table 22 “SCTimer/PWM output
dynamic characteristics”. This reduces the number of PWM outputs to five for each large
SCT.
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digital signal from/to pins
analog peripheral
analog signal from/to pins
digital peripheral
digital signal internal
analog signal internal
ANALOG IN
TRIGGER
SWITCH MATRIX
THRESHOLD CROSSING
INTERRUPTS
ADC0/ADC1
4
VDDA DIVIDER
TEMP SENSOR
VOLTAGE
REFERENCE
SCT0
MATCH/
MATCHRELOAD OUTPUTS
8 x PWM OUT
TIMER0
SCT1
MATCH/
MATCHRELOAD OUTPUTS
8 x PWM OUT
TIMER1
TIMER2
SCT2
MATCH/
MATCHRELOAD OUTPUTS
TIMER3
SCT3
MATCH/
MATCHRELOAD OUTPUTS
6 x PWM OUT
ACMP0
ACMP1
ACMP2
ACMP3
OUTPUTS
ANALOG IN
SCT IPU
6 x PWM OUT
SWITCH MATRIX
INPUT MUX
SCT0/1/2/3
aaa-010873
Fig 12. PWM-Analog subsystem
8.22.2 Timer controlled subsystem
The timers, the analog components, and the DMA can be configured to form a subsystem
that can run independently of the main processor under the control of the SCTs and any
events that are generated by the A/D converters, the comparators, the SCT output
themselves, or the external pins. A/D conversions can be triggered by the timer outputs,
the comparator outputs or by events from external pins. Data can be transferred from the
ADCs to memory using the DMA controller, and the DMA transfers can be triggered by the
ADCs, the comparator outputs, or by the timer outputs.
For an overview of the subsystem, see Figure 13 “Subsystem with timers, switch matrix,
DMA, and analog components”.
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analog peripheral
analog signal from/to pins
digital peripheral
INPUT MUX
DMA
digital signal from/to pins
digital signal internal
analog signal internal
4
VOLTAGE
REFERENCE
SCT IPU
INPUT MUX
TEMP SENSOR
TIMER1 (SCT1)
TIMER2 (SCT2)
NVIC
OUTPUTS
TIMER0 (SCT0)
VDDA DIVIDER
THRESHOLD CROSSING
INTERRUPTS
TRIGGER
SWITCH MATRIX
ANALOG IN
ADC0/ADC1
SWITCH MATRIX
ACMP0
ACMP1
ACMP2
ACMP3
OUTPUTS
ANALOG IN
TIMER3 (SCT3)
DAC_SHUTOFF
DAC
aaa-010874
Fig 13. Subsystem with timers, switch matrix, DMA, and analog components
8.22.3 SCTimer/PWM in the large configuration (SCT0/1)
Remark: For applications that require exact timing of the SCT outputs (for example
PWM), assign the outputs only to fixed-pin functions to ensure that the output skew is
nearly the same for all outputs.
8.22.3.1
Features
The following feature list summarizes the configuration for the two large SCTs. Each large
SCT has a companion small SCT (see Section 8.22.4) with fewer inputs and outputs and
a reduced feature set.
• Each SCT supports:
– 16 match/capture registers
– 16 events
– 16 states
– Match register 0 to 5 support a fractional component for the dither engine
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– 8 inputs and 10 outputs
– DMA support
• Counter/timer features:
– Configurable as two 16-bit counters or one 32-bit counter.
– Counters clocked by system clock or selected input.
– Configurable as up counters or up-down counters.
– Configurable number of match and capture registers. Up to 16 match and capture
registers total.
– Upon match create the following events: stop, halt, limit counter or change counter
direction; toggle outputs; create an interrupt; change the state.
– Counter value can be loaded into capture register triggered by match or
input/output toggle.
• PWM features:
– Counters can be used in conjunction with match registers to toggle outputs and
create time-proportioned PWM signals.
– Up to eight single-edge or dual-edge controlled PWM outputs with up to eight
independent duty cycles when configured as 32-bit timers.
• Event creation features:
– The following conditions define an event: a counter match condition, an input (or
output) condition such as an rising or falling edge or level, a combination of match
and/or input/output condition.
– Events can only have an effect while the counter is running.
– Selected events can limit, halt, start, or stop a counter or change its direction.
– Events trigger state changes, output toggles, interrupts, and DMA transactions.
– Match register 0 can be used as an automatic limit.
– In bi-directional mode, events can be enabled based on the count direction.
– Match events can be held until another qualifying event occurs.
• State control features:
– A state is defined by the set of events that are allowed to happen in the state.
– A state changes into another state as result of an event.
– Each event can be assigned to one or more states.
– State variable allows sequencing across multiple counter cycles.
• Dither engine.
• Integrated with an input pre-processing unit (SCTIPU) to combine or delay input
events.
Inputs and outputs on the SCTimer0/PWM and SCTimer1/PWM are configured as follows:
• 8 inputs
– 7 inputs. Each input except input 7 can select one of 23 sources from an input
multiplexer.
– One input connected directly to the SCT PLL for a high-speed dedicated clock
input.
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• 10 outputs (some outputs are connected to multiple locations)
– Three outputs connected to external pins through the switch matrix as movable
functions.
– Five outputs connected to external pins through the switch matrix as fixed-pin
functions.
– Two outputs connected to the SCTIPU to sample or latch input events.
– One output connected to the other large SCT
– Four outputs connected to one small SCT
– Two outputs connected to each ADC trigger input
8.22.4 State-Configurable Timers in the small configuration (SCT2/3)
Remark: For applications that require exact timing of the SCT outputs (for example
PWM), assign the outputs only to fixed-pin functions to ensure that the output skew is
nearly the same for all outputs.
8.22.4.1
Features
The following feature list summarizes the configuration for the two small SCTs. Each small
SCT has a companion large SCT (see Section 8.22.3) with more inputs and outputs and a
dither engine.
• Each SCT supports:
– 8 match/capture registers
– 10 events
– 10 states
– 3 inputs and 6 outputs
– DMA support
• Counter/timer features:
– Configurable as two 16-bit counters or one 32-bit counter.
– Counters clocked by bus clock or selected input.
– Up counters or up-down counters.
– Configurable number of match and capture registers. Up to 16 match and capture
registers total.
– Upon match create the following events: interrupt, stop, limit timer or change
direction; toggle outputs; change state.
– Counter value can be loaded into capture register triggered by match or
input/output toggle.
• PWM features:
– Counters can be used in conjunction with match registers to toggle outputs and
create time-proportioned PWM signals.
– Up to six single-edge or dual-edge controlled PWM outputs with independent duty
cycles if configured as 32-bit timers.
• Event creation features:
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– The following conditions define an event: a counter match condition, an input (or
output) condition, a combination of a match and/or and input/output condition in a
specified state.
– Selected events can limit, halt, start, or stop a counter.
– Events control state changes, outputs, interrupts, and DMA requests.
– Match register 0 can be used as an automatic limit.
– In bi-directional mode, events can be enabled based on the count direction.
– Match events can be held until another qualifying event occurs.
• State control features:
– A state is defined by events that can take place in the state while the counter is
running.
– A state changes into another state as result of an event.
– Each event can be assigned to one or more states.
– State variable allows sequencing across multiple counter cycles.
• Integrated with an input pre-processing unit (SCTIPU) to combine or delay input
events.
Inputs and outputs on the SCTimer2/PWM and SCTimer3/PWM are configured as follows:
• 3 inputs. Each input selects one of 21 sources from a pin multiplexer.
• 6 outputs (some outputs are connected to multiple locations)
– Three outputs connected to external pins through the switch matrix as movable
functions.
– Three outputs connected to external pins through the switch matrix as fixed-pin
functions.
– Two outputs connected to the SCT IPU to sample or latch input events.
– Four outputs connected to the accompanying large SCT
– Two outputs connected to each ADC trigger input
8.22.5 SCT Input processing unit (SCTIPU)
The SCTIPU allows to block or propagate signals to inputs of the SCT under the control of
an SCT output. Using the SCTIPU in this way, allows signals to be blocked from entering
the SCT inputs for a certain amount of time, for example while they are known to be
invalid.
In addition, the SCTIPU can generate a common signal from several combined input
sources that can be selected on all SCT inputs. Such a mechanism can be useful to
create an abort signal that stops all timers.
8.22.5.1
Features
The SCTIPU pre-processes inputs to the State-Configurable Timers (SCT).
• Four outputs created from a selection of input transitions. Each output can be used as
abort input to the SCTs or for any other application which requires a collection of
multiple SCT inputs to trigger an identical SCT response.
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• Four registers to indicate which specific input sources caused the abort input to the
SCTs.
• Four additional outputs which can be sampled at certain times and latched at others
before being routed to SCT inputs.
• Nine abort inputs. Any combination of the abort inputs can trigger the dedicated abort
input of each SCT.
8.23 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, the user code can track the position, direction of rotation,
and velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In
addition, the QEI can capture the velocity of the encoder wheel.
8.23.1 Features
•
•
•
•
•
•
•
•
•
•
Tracks encoder position.
Increments/decrements depending on direction.
Programmable for 2 or 4 position counting.
Velocity capture using built-in timer.
Velocity compare function with “less than” interrupt.
Uses 32-bit registers for position and velocity.
Three position-compare registers with interrupts.
Index counter for revolution counting.
Index compare register with interrupts.
Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.
• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clock and direction).
8.24 Analog-to-Digital Converter (ADC)
The ADC supports a resolution of 12 bit and fast conversion rates of up to 2 Msamples/s.
Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible
trigger sources are internal connections to other on-chip peripherals such as the SCT and
analog comparator outputs, external pins, and the ARM TXEV interrupt.
The ADC supports a variable clocking scheme with clocking synchronous to the system
clock or independent, asynchronous clocking for high-speed conversions.
The ADC includes a hardware threshold compare function with zero-crossing detection.
The threshold crossing interrupt is connected internally to the SCT inputs for tight timing
control between the ADC and the SCTs.
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8.24.1 Features
•
•
•
•
12-bit successive approximation analog-to-digital converter.
•
•
•
•
Two configurable conversion sequences with independent triggers.
12-bit conversion rate of 2 MHz.
Input multiplexing among 12 pins and up to 4 internal sources.
Internal sources are the temperature sensor voltage, internal reference voltage, core
voltage regulator output, and VDDA/2.
Optional automatic high/low threshold comparison and zero-crossing detection.
Power-down mode and low-power operating mode.
Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage
level).
• Burst conversion mode for single or multiple inputs.
• Synchronous or asynchronous operation. Asynchronous operation maximizes
flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger
latency and can eliminate uncertainty and jitter in response to a trigger.
8.25 Digital-to-Analog Converter (DAC)
The DAC supports a resolution of 12 bits. Conversions can be triggered by an external pin
input or an internal timer.
The DAC includes an optional automatic hardware shut-off feature which forces the DAC
output voltage to zero while a HIGH level on the external DAC_SHUTOFF pin is detected.
8.25.1 Features
• 12-bit digital-to-analog converter.
• Supports DMA.
• Internal timer or pin external trigger for staged, jitter-free DAC
conversion sequencing.
• Automatic hardware shut-off triggered by an external pin.
8.26 Analog comparator (ACMP)
The LPC15xx include four analog comparators with seven selectable inputs each for each
positive or negative input channel. Two analog inputs are common to all four comparators.
Internal voltage inputs include a voltage ladder reference with selectable voltage supply
source, the temperature sensor or the internal voltage reference.
The analog inputs to the comparators are fixed-pin functions and must be enabled through
the switch matrix.
The outputs of each analog comparator are internally connected to the ADC trigger inputs
and to the SCT inputs, so that the result of a voltage comparison can trigger a timer
operation or an analog-to-digital conversion.
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8.26.1 Features
• Seven selectable inputs. Fully configurable on either the positive side or the negative
input channel.
• 32-stage voltage ladder internal reference for selectable voltages on each
comparator; configurable on either positive or negative comparator input.
• Voltage ladder source voltage is selectable from an external pin or the 3.3 V analog
voltage supply.
• 0.9 V internal band gap reference voltage selectable as either positive or negative
input on each comparator.
• Temperature sensor voltage selectable as either positive or negative input on each
comparator.
• Voltage ladder can be separately powered down for applications only requiring the
comparator function.
• Individual comparator outputs can be connected internally to the SCT and ADC trigger
inputs or the external pins.
• Separate interrupt for each comparator.
• Pin filter included on each comparator output.
• Three propagation delay values are programmable to optimize between speed and
power consumption.
• Relaxation oscillator circuitry output for a 555 style timer operation using comparator
blocks 0 and 1.
8.27 Temperature sensor
The temperature sensor transducer uses an intrinsic pn-junction diode reference and
outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage
varies inversely with device temperature with an absolute accuracy of better than ±5 C
over the full temperature range (40 C to +105 C). The temperature sensor is only
approximately linear with a slight curvature. The output voltage is measured over different
ranges of temperatures and fit with linear-least-square lines.
After power-up, the temperature sensor output must be allowed to settle to its stable value
before it can be used as an accurate ADC input.
For an accurate measurement of the temperature sensor by the ADC, the ADC must be
configured in single-channel burst mode. The last value of a nine-conversion (or more)
burst provides an accurate result.
8.28 Internal voltage reference
The internal voltage reference is an accurate 0.9 V and is the output of a low voltage band
gap circuit. A typical value at Tamb = 25 C is 0.905 V. The internal voltage reference can
be used in the following applications:
• When the supply voltage VDD is known accurately, the internal voltage reference can
be used to reduce the offset error EO of the ADC code output. The ADC error
correction then increases the accuracy of temperature sensor voltage output
measurements.
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• When the ADC is accurately calibrated, the internal voltage reference can be used to
measure the power supply voltage. This requires calibration by recording the ADC
code of the internal voltage reference at different power supply levels yielding a
different ADC code value for each supply voltage level. In a particular application, the
internal voltage reference can be measured and the actual power supply voltage can
be determined from the stored calibration values. The calibration values can be stored
in the EEPROM for easy access.
After power-up, the internal voltage reference must be allowed to settle to its stable value
before it can be used as an ADC reference voltage input.
For an accurate measurement of the internal voltage reference by the ADC, the ADC must
be configured in single-channel burst mode. The last value of a nine-conversion (or more)
burst provides an accurate result.
8.29 Multi-Rate Timer (MRT)
The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each
channel can be programmed with an independent time interval, and each channel
operates independently from the other channels.
8.29.1 Features
• 24-bit interrupt timer
• Four channels independently counting down from individually set values
• Repeat and one-shot interrupt modes
8.30 Windowed WatchDog Timer (WWDT)
The watchdog timer resets the controller if software fails to periodically service it within a
programmable time window.
8.30.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
•
•
•
•
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The WWDT is clocked by the dedicated watchdog oscillator (WDOsc) running at a
fixed frequency.
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8.31 Repetitive Interrupt (RI) timer
The repetitive interrupt timer provides a free-running 48-bit counter which is compared to
a selectable value, generating an interrupt when a match occurs. Any bits of the
timer/compare can be masked such that they do not contribute to the match detection.
The repetitive interrupt timer can be used to create an interrupt that repeats at
predetermined intervals.
8.31.1 Features
• 48-bit counter running from the main clock. Counter can be free-running or can be
reset when an RIT interrupt is generated.
• 48-bit compare value.
• 48-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
8.32 System tick timer
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
8.33 Real-Time Clock (RTC)
The RTC resides in a separate, always-on voltage domain with battery back-up. The RTC
uses an independent 32 kHz oscillator, also located in the always-on voltage domain.
8.33.1 Features
• 32-bit, 1 Hz RTC counter and associated match register for alarm generation.
• Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution
with a more that one minute maximum time-out period.
• RTC alarm and high-resolution/wake-up timer time-out each generate independent
interrupt requests. Either time-out can wake up the part from any of the low power
modes, including Deep power-down.
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8.34 Clock generation
IRC
system oscillator
watchdog oscillator
MAINCLKSELA
(main clock select A)
main clock
SYSTEM CLOCK
DIVIDER
system clock
CPU, system control,
PMU
n
memories,
peripheral clocks
RTC oscillator
32 kHz
SYSAHBCLKCTRLn
(AHB clock enable)
MAINCLKSELB
(main clock select B)
SYSTICK PERIPHERAL
CLOCK DIVIDER
IRC
SYSTEM PLL
system oscillator
USART PERIPHERAL
CLOCK DIVIDER
SYSPLLCLKSEL
(system PLL clock select)
FRACTIONAL RATE
GENERATOR
IOCONCLKDIV
CLOCK DIVIDER
ARM core
SYSTICK
USART[n:0]
IOCON digital
glitch filter
ARM TRACE CLOCK
CLOCK DIVIDER
ARM trace
USB 48 MHz CLOCK
DIVIDER
USB
IRC
system oscillator
IRC
USB PLL
system oscillator
USBPLLCLKSEL
(USB PLL clock select)
USBCLKSEL
(USB clock select)
IRC
SCT PLL
SCT
system oscillator
IRC
SCTPLLCLKSEL
(SCT PLL clock select)
ASYNC ADC CLOCK
DIVIDER
ADC
ADCASYNCCLKSEL
(clock select)
IRC
system oscillator
watchdog oscillator
CLKOUTSELA
(CLKOUT clock select A)
CLKOUT PIN CLOCK
DIVIDER
CLKOUT pin
RTC oscillator 32 kHz
CLKOUTSELB
(CLKOUT clock select B)
watchdog oscillator
WWDT
aaa-010875
Fig 14. Clock generation
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8.35 Power domains
The LPC15xx provide two independent power domains that allow the bulk of the device to
have power removed while maintaining operation of the RTC and the backup Registers.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. The device core power
(VDD) is used to operate the RTC whenever VDD is present. Therefore, there is no power
drain from the RTC battery when VDD is and VDD >= VBAT + 0.3 V.
LPC15xx
to I/O pads
to core
VSS
REGULATOR
to memories,
peripherals,
oscillators,
PLLs
VDD
MAIN POWER DOMAIN
WAKEUP
ULTRA LOW-POWER
REGULATOR
VBAT
WAKE-UP
CONTROL
BACKUP REGISTERS
RTCXIN
32 kHz
OSCILLATOR
RTCXOUT
REAL-TIME CLOCK
ALWAYS-ON/RTC POWER DOMAIN
ADC
VDDA
ACMP
TEMP SENSE
INTERNAL
VOLTAGE REF
VDD
VSSA
ADC POWER DOMAIN
DAC
aaa-010876
Fig 15. Power distribution
8.36 Integrated oscillators
The LPC15xx include the following independent oscillators: the system oscillator, the
Internal RC oscillator (IRC), the watchdog oscillator, and the 32 kHz RTC oscillator. Each
oscillator can be used for multiple purposes.
Following reset, the LPC15xx operates from the internal RC oscillator until software
switches to a different clock source. The IRC allows the system to operate without any
external crystal and the bootloader code to operate at a known frequency.
See Figure 14 for an overview of the LPC15xx clock generation.
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8.36.1 Internal RC oscillator
The IRC can be used as the clock that drives the system PLL and then the CPU. In
addition, the IRC can be selected as input to various clock dividers and as the clock
source for the USB PLL and the SCT PLL (see Figure 14). The nominal IRC frequency is
12 MHz.
Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC15xx
use the IRC as the clock source. Software can later switch to one of the other available
clock sources.
8.36.2 System oscillator
The system oscillator can be used as a stable and accurate clock source for the CPU, with
or without using the PLL. For USB applications, use the system oscillator to provide the
clock source to USB PLL.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
The system oscillator has a wake-up time of approximately 500 μs.
8.36.3 Watchdog oscillator
The low-power watchdog oscillator can be used as a clock source that directly drives the
CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency
is fixed at 503 kHz. The frequency spread over processing and temperature is 40 %.
8.36.4 RTC oscillator
The low-power RTC oscillator provides a 1 Hz clock and a 1 kHz clock to the RTC and a
32 kHz clock output that can be used to obtain the main clock (see Figure 14).The 32 kHz
oscillator output can be observed on the CLKOUT pin to allow trimming the RTC oscillator
without interference from a probe.
8.37 System PLL, USB PLL, and SCT PLL
The LPC15xx contain a three identical PLLs for generating the system clock, the 48 MHz
USB clock, and an asynchronous clock for the ADCs and SCTs. The system PLL is used
to create the main clock. The SCT and USB PLLs create dedicated clocks for the
asynchronous ADC, the asynchronous SCT clock input, and the USB.
Remark: The USB PLL is available on parts LPC1549/48/47 only.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the
CCO within its frequency range while the PLL is providing the desired output frequency.
The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The
PLL output frequency must be lower than 100 MHz. Since the minimum output divider
value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off
and bypassed following a chip reset. Software can enable the PLL later. The program
must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL
as a clock source. The PLL settling time is 100 s.
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8.38 Clock output
The LPC15xx feature a clock output function that routes the internal oscillator outputs, the
PLL outputs, or the main clock an output pin where they can be observed directly.
8.39 Wake-up process
The LPC15xx begin operation by using the 12 MHz IRC oscillator as the clock source at
power-up and when awakened from Deep power-down mode. This mechanism allows
chip operation to resume quickly. If the application uses the system oscillator or the PLL,
software must enable these components and wait for them to stabilize. Only then can the
system use the PLL and system oscillator as a clock source.
8.40 Power control
The LPC15xx support various power control features. There are four special modes of
processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate can also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This power control mechanism allows a trade-off of power versus processing speed
based on application requirements. In addition, a register is provided for shutting down the
clocks to individual on-chip peripherals. This register allows fine-tuning of power
consumption by eliminating all dynamic power use in any peripherals that are not required
for the application. Selected peripherals have their own clock divider which provides
additional power control.
8.40.1 Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC15xx for one of the following power modes:
• Default mode corresponding to power configuration after reset.
• CPU performance mode corresponding to optimized processing capability.
• Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock and to easily set the configuration options for
Deep-sleep and power-down modes.
Remark: When using the USB, configure the LPC15xx in Default mode.
8.40.2 Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and can generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, by memory systems and related controllers, and by
internal buses.
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8.40.3 Deep-sleep mode
In Deep-sleep mode, the LPC15xx is in Sleep-mode and all peripheral clocks and all clock
sources are off except for the IRC. The IRC output is disabled unless the IRC is selected
as input to the watchdog timer. In addition all analog blocks are shut down and the flash is
in stand-by mode. In Deep-sleep mode, the application can keep the watchdog oscillator
and the BOD circuit running for self-timed wake-up and BOD protection.
The LPC15xx can wake up from Deep-sleep mode via reset, selected GPIO pins, a
watchdog timer interrupt, an interrupt generating USB port activity, an RTC interrupt, or
any interrupts that the USART, SPI, or I2C interfaces can create in Deep-sleep mode. The
USART wake-up requires the 32 kHz mode, the synchronous mode, or the CTS interrupt
to be set up.
Deep-sleep mode saves power and allows for short wake-up times.
8.40.4 Power-down mode
In Power-down mode, the LPC15xx is in Sleep-mode and all peripheral clocks and all
clock sources are off except for watchdog oscillator if selected. In addition all analog
blocks and the flash are shut down. In Power-down mode, the application can keep the
BOD circuit running for BOD protection.
The LPC15xx can wake up from Power-down mode via reset, selected GPIO pins, a
watchdog timer interrupt, an interrupt generating USB port activity, an RTC interrupt, or
any interrupts that the USART, SPI, or I2C interfaces can create in Power-down mode.
The USART wake-up requires the 32 kHz mode, the synchronous mode, or the CTS
interrupt to be set up.
Power-down mode reduces power consumption compared to Deep-sleep mode at the
expense of longer wake-up times.
8.40.5 Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP
pin and the always-on RTC power-domain. The LPC15xx can wake up from Deep
power-down mode via the WAKEUP pin or a wake-up signal generated by the RTC
interrupt.
The LPC15xx can be blocked from entering Deep power-down mode by setting a lock bit
in the PMU block. Blocking the Deep power-down mode enables the application to keep
the watchdog timer or the BOD running at all times.
If the WAKEUP pin is used in the application, an external pull-up resistor is required on
the WAKEUP pin to hold it HIGH while the part is in deep power-down mode. Pulling the
WAKEUP pin LOW wakes up the part from deep power-down mode. In addition, pull the
RESET pin HIGH to prevent it from floating while in Deep power-down mode.
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8.41 System control
8.41.1 Reset
Reset has four sources on the LPC15xx: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
In Deep power-down mode, an external pull-up resistor is required on the RESET pin.
The RESET pin is operational in active, sleep, deep-sleep, and power-down modes if the
RESET function is selected through the switch matrix for pin PIO0_21 (this is the default).
A LOW-going pulse as short as 50 ns executes the reset and thereby wakes up the part to
its active state. The RESET pin is not functional in Deep power-down mode and must be
pulled HIGH externally while the part is in Deep power-down mode.
9''
9''
9''
5SX
UHVHW
(6'
QV5&
*/,7&+),/7(5
3,1
(6'
966
DDD
Fig 16. RESET pin configuration
8.41.2 Brownout detection
The LPC15xx includes brown-out detection (BOD) with two levels for monitoring the
voltage on the VDD pin. If this voltage falls below one of two selected levels, the BOD
asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the
Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can
monitor the signal by reading a dedicated status register. Two threshold levels can be
selected to cause a forced reset of the chip.
8.41.3 Code security (Code Read Protection - CRP)
CRP provides different levels of security in the system so that access to the on-chip flash
and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be
restricted. Programming a specific pattern into a dedicated flash location invokes CRP.
IAP commands are not affected by the CRP.
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In addition, ISP entry the external pins can be disabled without enabling CRP. For details,
see the LPC15xx user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot
be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected, fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using ISP
pin as well. If necessary, the application must provide a flash update mechanism
using IAP calls or using a call to the reinvoke ISP command to enable flash update via
the USART.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of the ISP pins for valid user code can be
disabled. For details, see the LPC15xx user manual.
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8.42 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M3. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M3 is
configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC15xx
is in reset.
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.
2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode, and release the RESET pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
9. Limiting values
Table 9.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
VDD
supply voltage (3.3 V)
VDDA
analog supply voltage
Vref
reference voltage
VBAT
battery supply voltage
VI
input voltage
Conditions
[2]
on pin VREFP_DAC_VDDCMP
Max
Unit
0.5
VDDA
V
0.5
+4.6
V
0.5
VDDA
V
0.5
VDDA
V
0.5
+4.6
V
[3][4]
0.5
+5.5
V
on I2C open-drain pins
PIO0_22, PIO0_23
[5]
0.5
+5.5
V
3 V tolerant I/O pin without
over-voltage protection. Applies
to PIO0_12.
[6]
0.5
VDDA
V
0.5
VDD + 0.5
V
0.5
+4.6
V
0.5
+2.5
V
on pin VREFP_ADC
5 V tolerant I/O pins; only valid
when the VDD(IO) supply voltage
is present
USB_DM, USB_DP pins
VIA
Min
[7][8]
analog input voltage
[9]
crystal input voltage
[2]
Vi(rtcx)
32 kHz oscillator input voltage
[2]
0.5
+4.6
V
IDD
supply current
per supply pin
-
100
mA
ISS
ground current
per ground pin
-
100
mA
Vi(xtal)
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Table 9.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
Unit
Ilatch
I/O latch-up current
(0.5VDD) < VI < (1.5VDD);
-
100
mA
Tstg
storage temperature
65
+150
C
Tj(max)
maximum junction temperature
-
+150
C
Ptot(pack)
total power dissipation (per
package)
based on package heat
transfer, not device power
consumption
-
1.5
W
Vesd
electrostatic discharge voltage
human body model; all pins
-
5
kV
Tj < 125 C
[1]
[10]
[11]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2]
Maximum/minimum voltage above the maximum operating voltage (see Table 11) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3]
Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_22 and PIO0_23 and except the 3 V tolerant pin PIO0_12.
[4]
Including the voltage on outputs in 3-state mode.
[5]
VDD(IO) present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD(IO) is powered down.
[6]
Applies to 3 V tolerant pin PIO0_12.
[7]
An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated
exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the
ADC inputs for a long time affects the reliability of the device and reduces its lifetime.
[8]
If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below
VDD without affecting the hysteresis range of the comparator function.
[9]
It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.
[10] Dependent on package type.
[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
10. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
T j = T amb + P D R th j – a
(1)
• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
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Table 10.
Symbol
Thermal resistance value (C/W): ±15 %
Parameter
Conditions
Typ
Unit
thermal resistance
junction-to-ambient
JEDEC (4.5 in 4 in)
0 m/s
64
C/W
1 m/s
55
C/W
2.5 m/s
50
C/W
0 m/s
96
C/W
1 m/s
76
C/W
LQFP48
ja
8-layer (4.5 in 3 in)
67
C/W
jc
thermal resistance
junction-to-case
13
C/W
jb
thermal resistance
junction-to-board
16
C/W
0 m/s
51
C/W
1 m/s
45
C/W
2.5 m/s
41
C/W
0 m/s
75
C/W
1 m/s
60
C/W
2.5 m/s
54
C/W
2.5 m/s
LQFP64
ja
thermal resistance
junction-to-ambient
JEDEC (4.5 in 4 in)
8-layer (4.5 in 3 in)
jc
thermal resistance
junction-to-case
13
C/W
jb
thermal resistance
junction-to-board
17
C/W
0 m/s
42
C/W
1 m/s
37
C/W
2.5 m/s
34
C/W
0 m/s
59
C/W
1 m/s
48
C/W
LQFP100
ja
thermal resistance
junction-to-ambient
JEDEC (4.5 in 4 in)
8-layer (4.5 in 3 in)
44
C/W
jc
thermal resistance
junction-to-case
12
C/W
jb
thermal resistance
junction-to-board
17
C/W
2.5 m/s
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The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
11. Static characteristics
Table 11. Static characteristics
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
VDD
supply voltage (core
and external rail)
VDDA
analog supply voltage
Vref
reference voltage
VBAT
battery supply voltage
IDD
supply current
Min
Typ[1]
Max
Unit
2.4
3.3
VDDA
V
2.4
3.3
3.6
V
on pin VREFP_DAC_VDDCMP
2.4
-
VDDA
V
on pin VREFP_ADC
-
-
VDDA
V
2.4
3.3
3.6
V
-
4.3
-
mA
-
2.7
-
mA
-
19.3
-
mA
-
18
-
mA
-
2.1
-
mA
-
1.5
-
mA
-
8.0
-
mA
-
7.3
-
mA
Conditions
[2]
Active mode; code
while(1){}
executed from flash;
system clock = 12 MHz; default
mode; VDD = 3.3 V
[3][4][5]
system clock = 12 MHz;
low-current mode; VDD = 3.3 V
[3][4][5]
system clock = 72 MHz; default
mode; VDD = 3.3 V
[3][4][7]
system clock = 72 MHz;
low-current mode; VDD = 3.3 V
[3][4][7]
[7][8]
[7][8]
[8][10]
[8][10]
Sleep mode;
IDD
supply current
system clock = 12 MHz; default
mode; VDD = 3.3 V
[3][4][5]
system clock = 12 MHz;
low-current mode; VDD = 3.3 V
[3][4][5]
system clock = 72 MHz; default
mode; VDD = 3.3 V
[3][4][10]
system clock = 72 MHz;
low-current mode; VDD = 3.3 V
[3][4][10]
Deep-sleep mode;
VDD = 3.3 V;
[7][8]
[7][8]
[7][8]
[7][8]
[3][4][11]
-
Tamb = 25 C
Tamb = 105 C
IDD
supply current
Power-down mode;
VDD = 3.3 V
[3][4][11]
LPC15XX
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 29 April 2015
380
A
620
A
3.8
15
A
-
163
A
-
Tamb = 25 C
Tamb = 105 C
310
-
-
© NXP Semiconductors N.V. 2015. All rights reserved.
55 of 107
LPC15xx
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Table 11. Static characteristics …continued
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
IDD
Parameter
supply current
Conditions
Deep power-down mode; VDD =
3.3 V; VBAT = 0 or VBAT = 3.0 V
Min
Typ[1]
Max
Unit
-
1.1
1.3[14]
A
-
-
15
A
-
560
-
nA
0
-
nA
1
-
A
[3][12][13]
RTC oscillator running
Tamb = 25 C
Tamb = 105 C
[3][12]
RTC oscillator input grounded;
Tamb = 25 C
IBAT
battery supply current
Deep power-down mode; VDD =
VDDA = 3.3 V; VBAT = 3.0 V
[13]
VDD and VDDA tied to ground;
VBAT = 3.0 V
[13]
Standard port pins configured as digital pins, RESET; see Figure 17
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
0.5
10[14]
nA
IIH
HIGH-level input
current
VI = VDD; on-chip pull-down
resistor disabled
-
0.5
10[14]
nA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD; on-chip
pull-up/down resistors disabled
-
0.5
10[14]
nA
VI
input voltage
VDD 2.4 V; 5 V tolerant pins
except PIO0_12
0
-
5
V
VDD 2.4 V; on 3 V tolerant pin
PIO0_12
0
-
VDDA
VDD = 0 V
0
-
3.6
V
output active
0
-
VDD
V
V
[16]
[18]
VO
output voltage
VIH
HIGH-level input
voltage
0.7VDD
-
-
VIL
LOW-level input voltage
-
-
0.3VDD V
Vhys
hysteresis voltage
2.4 V
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