ARCHIVE INFORMATION
Document Number: MC33389
Rev. 5.0, 3/2007
System Basis Chip with Low
Speed Fault Tolerant CAN
33389
The 33389 is a monolithic integrated circuit combining many
functions frequently used by automotive Engine Control Units (ECUs).
It incorporates a low speed fault tolerant CAN transceiver.
Features
• Dual Low Drop Voltage Regulators, with Respectively 100 mA and
200 mA Current Capabilities, Current Limitation, and Over
Temperature Detection with Pre-warning
• 5.0 V Output Voltage for V1 Regulator
• Three Operational Modes (Normal, Stand-by, and Sleep Modes)
Separated from the CAN Interface Operating Modes
• Low Speed 125 kBaud Fault Tolerant CAN Interface, Compatible
with 33388 Stand Alone Physical Interface
• V1 Regulator Monitoring and Reset Function
• Three External High Voltage Wake-Up Inputs, Associated with V3
VBAT Switch
• 100 mA Output Current Capability for V3 VBAT Switch Allowing Drive
of External Switches or Relays
• Low Stand-by and Sleep Current Consumption
• VBAT Monitoring and VBAT Failure Detection Capabilities
• DC Operating Voltage up to 27 V
• 40 V Maximum Transient Voltage
• Programmable Software Window Watchdog and Reset
• Wake-Up Capabilities (CAN Interface, Local Programmable
Cycle Wake
• INterface with the MCU through the SPI
• Pb-Free Packaging Designated by Suffix Codes VW and EG
SYSTEM BASIS CHIP
DH SUFFIX
VW SUFFIX (PB-FREE)
PLASTIC PACKAGE
98ASH70273A
20-PIN HSOP
ORDERING INFORMATION
Temperature
Range (TA)
Device
VPWR
MCU
CS
SCK
MOSI
MISO
5.0 V
SPI
V1
VBAT
V2
V3
L0
L1
L2
GND
RTH
CS
SCK
MOSI
MISO
INT
RST
TX
RX
CAN H
CAN L
Switched VBAT
Wake-Up Inputs
Twisted
CAN Bus
Pair
RTL
Figure 1. 33389 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
HSOP-20
MC33389CVW/R2
MC33389DDW/R2
5.0 V
Package
MC33389CDH/R2
MC33389CDW/R2
33389
DW SUFFIX
EG SUFFIX (PB-FREE)
PLASTIC PACKAGE
98ASB42345B
28-PIN SOICW
-40 to 125°C
SO-28
ARCHIVE INFORMATION
Freescale Semiconductor
Advance Information
ARCHIVE INFORMATION
DEVICE VARIATIONS
Table 1. Device Variations
Freescale Part No.
V1 Undervoltage
MC33389CDH
MC33389CVW
In V1 undervoltage condition, device remains in permanent reset state until V1 returns to normal
conditions. V1 is protected by overcurrent and overtemperature functions.
MC33389CDW
MC33389DDW
The sole difference between the C version and the D version is V1 Reset Threshold.
Reference V1 Reset Threshold on V1 on page 9.
33389
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ARCHIVE INFORMATION
DEVICE VARIATIONS
ARCHIVE INFORMATION
INTERNAL BLOCK DIAGRAM
Dual Voltage Regulator
VBAT
V2
5V
Voltage Control
Battery Voltage Failure Detect
Voltage Monitor
5V
VBAT Switch Supply
Mode Control
V1
V3
INT
Interrupt Control
Reset Control
Watchdog & Oscillator
L0
RST
Programmable
Wake-Up Inputs
L1
V2
L2
TX
RX
CS
SCLK
SPI
Interface
MOSI
Fault-Tolerant
CAN
Transceiver
RTH
MISO
CANH
CANL
GND
RTL
Figure 2. 33389 Simplified Internal Block Diagram
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Freescale Semiconductor
3
ARCHIVE INFORMATION
INTERNAL BLOCK DIAGRAM
ARCHIVE INFORMATION
PIN CONNECTIONS
TX
V1
RX
RST
INT
MISO
MOSI
SCLK
CS
L2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V3
VBAT
RTL
V2
CANH
GND
CANL
RTH
L0
L1
Figure 3. 33389 Pin Connections
Table 1. 33389 Pin Definitions: HSOSP 20-Lead
A functional description of each pin can be found in the Functional Pin Description section beginning on page 17.
Pin Number
Pin Name
Formal Name
Definition
1
TX
Transmitter Data
2
V1
3
RX
Receiver Data
4
RST
Reset
5
INT
Interrupt Output
6
MISO
Master In/Slave Out
This pin is the tri-state output from the shift register.
7
MOSI
Master Out/Slave In
This pin is for the input of serial instruction data.
8
SCLK
System Clock
9
CS
Chip Select
10 - 12
L0 - L2
Level 0 - 2 inputs
(L0: L2)
13
RTH
RTH
14
CANL
CAN Low
15
GND
Ground
16
CANH
CAN High
17
V2
18
RTL
RTL
19
VBAT
Voltage Battery
20
V3
Voltage Regulator
Three
Transmitter input of the LS CAN interface
Voltage Regulator One This 5.0 V pin is a 3% low drop voltage regulator dedicated to the microcontroller supply.
Receiver output of the LS CAN interface
This is an Input/Output pin.
This output is asserted LOW when an enabled interrupt condition occurs.
This pin clocks the internal shift registers.
This pin communicates with the system MCU and enables SPI communication.
Input interfaces to external circuitry. Levels at these pins can be read by SPI and input
can be used as programmable wake-up input in Sleep or Stop mode.
Pin for the connection of the bus termination to CANH
CAN low input/output
This pin is the ground of the integrated circuit.
CAN high input/output
Voltage Regulator Two This 5.0 V pin is a low drop voltage regulator dedicated to the peripherals supply.
Pin for the connection of the bus termination to CANL
This pin is voltage supply from the battery.
This pin is a 10 Ω switch to VBAT, used to supply external contacts or relays.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ARCHIVE INFORMATION
PIN CONNECTIONS
ARCHIVE INFORMATION
TX
V1
RX
RST
INT
GND
GND
GND
GND
MISO
MOSI
SCLK
CS
L2
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
V3
VBAT
RTL
V2
CANH
GND
GND
GND
GND
CANL
RTH
NC
L0
L1
Table 2. 33389 Pin Definitions: SOICW 28-Lead
A functional description of each pin can be found in the Functional Pin Description section beginning on page 17.
Pin Number
Pin
Name
1
TX
Transmitter Data
Transmitter input of the LS CAN interface
2
V1
Voltage Regulator
One
This 5.0 V pin is a 3% low drop voltage regulator dedicated to the microcontroller supply.
3
RX
Receiver Data
Receiver output of the LS CAN interface
4
RST
Reset
This is an Input/Output pin.
5
INT
Interrupt
This output is asserted LOW when an enabled interrupt condition occurs.
6 -9 20 - 23
GND
Ground
These device ground pins are internally connected to the package lead frame to provide
a 33389-to-PCB thermal path.
10
MISO
Master In/Slave Out
This pin is the tri-state output from the shift register.
11
MOSI
Master Out/Slave In
This pin is for the input of serial instruction data.
12
SCLK
System Clock
This pin clocks the internal shift registers.
13
CS
Chip Select
This pin communicates with the system MCU and enables SPI communication.
14, 15, 16
L0: L2
Wake-up Input
(L0: L2)
Input interfaces to external circuitry. Levels at these pins can be read by SPI and input
can be used as programmable wake-up input in Sleep or Stop mode.
17
NC
No Connect
This pin does not connect.
18
RTH
Thermal Resistance
High
Pin for the connection of the bus termination to CANH
19
CANL
CAN Low
CAN low input/output
24
CANH
CAN High
CAN high input/output
25
V2
Voltage Regulator
Two
This 5.0 V pin is a low drop voltage regulator dedicated to the peripherals supply.
26
RTL
Thermal Resistance
Low
Pin for the connection of the bus termination to CANL
27
VBAT
Voltage Battery
This pin is voltage supply from the battery.
28
V3
Voltage Regulator
Three
This pin is a 10 Ω switch to VBAT, used to supply external contacts or relays.
Formal Name
Definition
33389
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ARCHIVE INFORMATION
PIN CONNECTIONS
ARCHIVE INFORMATION
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
DC Voltage at VBAT Pin
VBAT
-0.3 to 27
V
Transient Voltage at VBAT Pin
VBAT
40
V
DC Voltage at Pins CANH and CANL
VBAT
-20 to 27
V
Transient Voltage at Pins CANH and CANL
VBAT
-40 to 40
V
VBAT
-100 to 100
V
DC Voltage at Pins V1 and V2
VBAT
-0.3 to 6.0
V
DC Current at Output Pins RX, MISO, RST, INT
VBAT
-20 to 20
mA
DC Voltage at Input Pins TX, MOSI, CS, RST
VBAT
-0.3 to 6.0
V
DC Voltage at Pins L0, L1, L2
VBAT
-0.3 to 40
V
Current at Pins L0, L1, L2
VBAT
-15
mA
Transient Current at Pin V3
VBAT
-30 to 20
mA
DC Voltage at pins RTH and RTL
VBAT
-0.3 to 40
V
ESD Voltage on any Pin (HBM 100 pF, 1.5 K)
VBAT
-2.0 to 2.0
kV
ESD Voltage on L0, L1, L2, CANH, CANL, VBAT
VBAT
-2.0 to 2.0
kV
ESD Voltage on any Pin (MM 200 pF, 0 Ω)
VBAT
-150 to 150
V
Operating Junction Temperature
TJ
-40 to 150
°C
Ambient Temperature
TA
-40 to 125
°C
Storage Temperature
TS
-55 to 165
°C
ELECTRICAL RATINGS
t < 500 ms (load dump)
0.0 < V2 < 5.5, VBAT > 0.0, t < 500 ms
Coupled Transient Voltage at Pins CANH and CANL
With 100 Ω Termination Resistors, Coupled Through 1.0 nF
(1)
0.0 < VBAT < 40 V
THERMAL RATINGS
Notes
1. Pulses 1, 2, 3a, and 3b according to ISO7637.
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Freescale Semiconductor
ARCHIVE INFORMATION
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ARCHIVE INFORMATION
Table 3. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
RRTHRTL
500 to 16 k
Ω
RAJC
3.1
°C/W
RAS/P
17
°C/W
TSD
165
°C
TPPRT
Note 5
°C
THERMAL RESISTANCE
RTH, RTL Termination Resistance
Junction to Heatsink Thermal Resistance for HSOP-20
33% Power on V1, 66% on V2 (including CAN) (2)
Junction to Pin Thermal Resistance for SO-28WD (3)
Thermal Shutdown Temperature
Peak Package Reflow Temperature During Reflow (4), (5)
Notes
2. Refer to thermal management in device description section.
3. Refer to thermal management in device section. Ground pins 6, 7, 8, 9, 20, 21, 22, and 23 of SO28WB package.
4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
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Freescale Semiconductor
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ARCHIVE INFORMATION
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ARCHIVE INFORMATION
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions VBAT, - 40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the
approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Nominal VBAT Operating Range
VBAT
5.5
—
18
V
Functional VBAT Operating Range
VBAT
5.5
—
27
V
POWER INPUT (VBAT)
VBAT Threshold for BATFAIL Flag
BATFAIL
2.0
—
4.0
V
Delay for Signalling BATFAIL
TFAIL
—
150
400
µs
Overvoltage VBAT Threshold
BATHIGH
18
20
22
V
THIGH
4.0
18
50
µs
ISLEEP1
—
75
125
Delay for Setting BATHIGH Flag
Supply Current in Sleep Mode
Forced Wake-Up and Cyclic Sense Disabled
µA
VBAT = 12 V, TJ = 25°C to 150°C
Supply Current in Sleep Mode
ISLEEP2
—
—
Forced Wake-Up and Cyclic Sense Disabled
µA
210
VBAT = 12 V, TJ = -40°C to 25°C
Supply Current in Sleep Mode
ISLEEP3
—
Forced Wake-Up and Cyclic Sense Enabled
µA
105
155
VBAT = 12 V, TJ = 25°C to 150°C
Supply Current in Sleep Mode
ISLEEP4
—
—
Forced Wake-Up and Cyclic Sense Enabled
µA
250
VBAT = 12 V, TJ = -40°C to 25°C
Supply Current in Sleep Mode
ISLEEP5
—
—
Forced Wake-Up and Cyclic Sense Disabled
µA
300
VBAT = 12 V, TJ = 25°C to 150°C
Supply Current in Stand-by Mode
ISTB2
—
0.5
1.0
mA
Supply Current in Normal Mode
INREC
—
3.5
7.0
mA
4.85
5.0
5.15
4.8
5.0
5.2
0.35
0.5
Normal Mode with I(V1) = 1 I(V2) = 0
Bus in Recessive State
POWER OUTPUT
V1 Output Voltage
V1NOM
0 mA < IOUT < 100 mA
V
5.5 V < VBAT < 27 V
V1 Output Voltage
V
V1
IOUT =< 100 mA
27 V < VBAT < 40 V
V1 Drop Voltage
IOUT =< 100 mA (6)
V1DROP
—
V
Notes
6. Measured when V1 has dropped 100mV below its nominal value
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Freescale Semiconductor
ARCHIVE INFORMATION
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
ARCHIVE INFORMATION
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions VBAT, - 40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the
approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
I1MAX
130
170
200
mA
TV1H
160
—
190
°C
TV1L
130
—
160
°C
TV1H-TV1L
20
—
40
°C
(C Version)
4.1
4.3
4.8
(D Version)
V2 - 0.4
V1 - 0.28
V1 - 0.1
POWER OUTPUT (CONTINUED)
V1 Output Current Limitation
V1NOM - 100 mV
V1 Overtemperature Shut OFF Threshold
Junction Temperature
V1 Pre-Warning Temperature Threshold
Junction Temperature
V1 Temperature Threshold Difference
V1 Reset Threshold on V1
V
VR1
5.5 V < VBAT < 27 V
V1 Reset Active V1 Range
V1R
1.0
VR1
—
V
V1 Reverse Current from V1 to VBAT and GND
IREV
—
—
1.0
mA
V2NOM
4.75
5.0
5.25
V
V2DROP
—
0.2
0.5
V
V2DROP
—
0.05
0.15
V
I1MAX
220
280
350
mA
VR2
4.1
4.55
4.75
V
VR2 Delay Time
VR2
20
—
70
µs
V2 Overtemperature Pre-Warning Threshold
TV2L
130
—
160
°C
TV2H
155
—
185
°C
V2LR1
-15
—
+15
mV
V2LR2
-75
—
+75
mV
V2LRR
30
55
—
dB
V1 = 4.9 V, 0 < VBAT < 4.9 V
V2 Output Voltage
0 mA < IOUT < 200 mA 5.5 V < VBAT < 40 V
V2 Drop Voltage
IOUT = 200 mA
(7)
V2 Drop Voltage
IOUT = 20 mA
(7)
V2 Output Current Limitation
V2NOM -100 mV
V2 Threshold on V2 to Report V2 OFF
V2 Nominal
V2 Junction Temperature
V2 Overtemperature Switch-OFF Threshold
V2 Junction Temperature
V2 Line Regulation
9.0 V < VBAT < 16.5
V2 Load Regulation
4.0 mA < ILOAD < 200 mA
V2 Line Ripple Rejection
100 Hz, 1.0 VPP on VBAT
(8)
Notes
7. Measured when V1 has dropped 100mV below its nominal value
8. Guaranteed by design; however, it is not production tested
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ARCHIVE INFORMATION
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
ARCHIVE INFORMATION
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions VBAT, - 40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the
approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
V2V2-V1
-3.0
—
3.0
%
V3DROP
—
0.4
1.0
V
V3DROP
—
—
1.5
V
I3LIM
100
150
250
mA
I3LEAK
—
—
15
µA
TV3
155
—
185
°C
VV3
0.3
—
0.5
V
VRC2
3.0
3.9
4.7
V
VCANTH
-3.2
—
-2.5
V
VCANDRTH
-3.2
—
-2.5
V
VCANH
—
—
0.2
V
VCANL
V2-0.2
—
—
V
VCANH
V2-1.4
—
—
V
VCANL
—
—
1.4
V
ICANH
50
75
100
mA
ICANL
50
95
130
mA
VCANH-VCANL
7.3
7.9
8.9
V
VCANH
VBAT/2+3
—
VBAT/2+5
V
ICANHF3
—
5.0
10
µA
ICANLF4
—
0.0
2.0
µA
POWER OUTPUT (CONTINUED)
V2 Percentage Difference V2-V1
VBAT > 9.0, IV1 = 20 mA, IV2 = 40 mA
V3 High Level Voltage Drop
IV3 = -50 mA, 9.0 V < VBAT < 40 V
V3 High Level Voltage Drop
IV3 = -50 mA, 6.0 V < VBAT < 9.0 V
V3 Leakage Output Limitation
5.5 V < VBAT < 27 V
V3 Leakage Current
V3 = 0 (V3 OFF)
V3 Overtemperature Detection
Junction Temperature
V3 Voltage with -30 mA (negative current for Relay Switch OFF)
No Functional Error Allowed for t < 100 ms
CAN Transceiver V2 for Forced Bus Stand-by Mode (Fail Safe)
CANH/L Differential Receiver, Threshold Voltage
CANH/L Differential Receiver, Dominant to Recessive Threshold
(Bus Failures 1, 2, and 5)
CANH Recessive Output Voltage
TX = High, R(RTH) < 4.0 k
CANL Recessive Output Voltage
TX = High, R(RTH) < 4.0 k
CANH Output Voltage, Dominant
TX = 0 V, BusNormal Mode, ICANH = - 40 mA
CANL Output Voltage, Dominant
TX = 0 V, Bus Normal Mode, ICANL = - 40 mA
CANH Output Current Limit
(VCANH = 0.0 V, TX = 0)
CANL Output Current Limit
(VCANL = 14 V, TX = 0)
Detection Threshold for Short Circuit to Battery Voltage
Bus Normal Mode
Detection Threshold for Short Circuit to Battery Voltage
Bus Stand-by Mode
CANH Output Current, Failure 3
Bus Stand-by Mode VCANH = 12 V
CANL Output Current, Failure 4
Bus Stand-by Mode, VCANL = 0.0 V, VBAT = 12 V
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ARCHIVE INFORMATION
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
ARCHIVE INFORMATION
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions VBAT, - 40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the
approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VWAKEL
2.5
3.3
3.9
V
VWAKEH
1.2
2.0
2.7
V
VWAKEL VWAKEH
0.2
—
—
V
VCANH
1.5
1.85
2.15
V
VCANL
2.8
3.05
3.4
V
ICANLPU
45
75
90
µA
ICANLPD
45
75
90
µA
Receiver Differential Input Impedance CANH/CANL
RDIFF
100
—
180
kΩ
Differential Receiver Common Mode Voltage Range
VCOM
-8.0
—
8.0
V
RTL to V2 Switch on Resistance
RRTL
10
25
70
Ω
RRTL
8.0
12.5
20
kΩ
RRTH
—
25
70
Ω
VIH
0.7 V1
—
V1 + 0.3 V
V
VCSTH
—
2.2
—
V
tCSFT
—
—
3.0
µs
VIL
-0.3
—
0.3 V1
V
ICSH
-100
—
-20
µA
ICSL
-100
—
-20
µA
ITXH
-200
-80
-25
µA
ITXL
-800
-320
-100
µA
ISISLK
-10
—
+10
µA
POWER OUTPUT (CONTINUED)
CANL Wake-Up Voltage Threshold
Bus Stand-by Mode
CANH Wake-Up Voltage Threshold
Bus Stand-by Mode
Wake-Up Threshold Difference
CANH Single Ended Receiver Threshold
Failures 4, 6, and 7
CANL Single Ended Receiver Threshold
Failures 3 and 8
CANL Pull-Up Current
Bus Normal Mode
CANH Pull Down Current
Bus Normal Mode
IOUT < -10 mA, Bus Normal Operating Mode
RTL to Battery Switch Series Resistance
Bus Stand-by Mode
RTH to Ground Switch on Resistance
IOUT < 10 mA, All Modes
CONTROL INTERFACE
High Level Input Voltage
CS Threshold for SPI Wake-Up
SBC in Sleep Mode, V1 < 1.5 V
CS Filter Time for SPI Wake-Up
SBC in Sleep Mode, V1 < 1.0 V
Low Level Input Voltage
High Level Input Current on CS
VI = 4.0 V
Low Level Input Current on CS
VI = 1.0 V
TX High Level Input Current
VI = 4.0 V
TX Low Level Input Current
VI = 1.0 V
SI, SCLK Input Current
0 < VIN < V1
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Freescale Semiconductor
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ARCHIVE INFORMATION
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
ARCHIVE INFORMATION
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions VBAT, - 40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the
approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VOH
V1 - 0.9
—
V1
V
VOL
0.0
—
0.9
V
IZ
-2.0
—
+2.0
µA
RST High Level Input Voltage
VIH
0.7 V1
—
V1 + 0.3 V
—
RST Low Level Input Voltage
VIL
-0.3
—
-0.3 V1
V
IRSTH1
-50
-30
-10
µA
IRSTH2
—
-300
—
µA
VRST
0.0
—
0.9
V
VWUP
3.0
3.7
4.5
V
VWUN
2.5
3.0
3.8
V
VHYS
—
700
—
mA
ILXWU
-5.0
—
+5.0
µA
VIN
—
350
600
µA
CONTROL INTERFACE (CONTINUED)
RX, INT, MISO High Level Output Voltage
I0 = -250 µA
RX, INT, MISO Low Level Output Voltage
I0 = -1.5 mA
RX, INT, MISO Tri-Stated SO Output Current
0 V < VSO < V1
RST High Level Output Current 1
0.0 < VOUT < 0.5 V1
RST High Level Output Current 2
0.5 < VOUT < V1
RST Low Level Output Voltage (I0 = 1.5 mA)
1.0 V < VBAT < 27 V
LX/Wake-Up Positive Switching Threshold
6.0 V VDD1 under voltage occurred (RSR2 = 1 in this case), 0 = > no over voltage on V occurred
RSR1: 1 = > Software watchdog reset occurred (RSR 2 = 1 in this case), 0 = > no SW watchdog reset occurred
RSR2: 1 = > External reset occurred (RSR0 = RSR1= 0 in this case), 0 = > no external reset occurred
Events related to the bits in register RSR are latched. All bits can be reset by a Read operation of the register. After a power-ON reset, RSR2
and RSR0 are set to 1. Therefore, the first read out of the register after power-ON delivers RSR[2:0] = [101].
Table 40. Voltage Supply Status Register (VSSR)
Address
VSSR
$01B
Bit 7
Bit 6
Bit 5
Bit 4
R
Bit 3
Bit 2
Bit 1
Bit 0
V3SR
V2SR
VBSR1
VBSR0
W
RESET
—
—
—
—
0
0
—
—
POR
—
—
—
—
0
0
0
1
This register monitors the status of the V2, V3, and VBAT voltage level.
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LOGIC COMMANDS AND REGISTERS
ARCHIVE INFORMATION
Table 41. VBSR1 VBSR0
VBSR1
VBSR0
Description
0
0
No Failure on VBAT
x
1
Under Voltage (BATFail)
1
x
Over Voltage (BATHigh)
V2SR: 1 = V2 ON, 0 = V2 OFF
V3SR: 1 = V3 over temperature, 0 = V3 no over temperature
VBSR1 is real time information. It cannot be reset. Bits V3SR, V2SR, and VBSR0 are latched and can be reset by a Read operation of the
register.
The next two registers (IMR1 and IMR2) mask the interrupt function.
Table 42. Interrupt Mask Control Register 1 (IMR1)
Address
IMR1
$01D
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HV
HTPW
MTPW
BATU
—
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BUSF
SPIE
WU
0
0
0
R
W
RESET
—
—
—
Table 43. Interrupt Mask Control Register 2 (IMR2)
Address
IMR2
$01E
Bit 7
Bit 6
Bit 5
R
W
RESET
—
—
—
—
—
To enable the appropriate interrupt, the mask bit has to be set to 1. To disable the interrupt the bit, it must be cleared to 0. After a power-ON
reset or RST = Low, the bits are cleared to 0. All interrupts are disabled. Explanation for the abbreviations:
HV = VBAT High voltage
HT = High temperature on V1 or V2
MTPW = Medium temperature pre-warning on V1 or V2
BATU = Battery under voltage (BATFail)
BUSF = CAN bus failure
SPIE = SPI error
WU = Wake-up
The next two registers (ISR1 and ISR2) read the interrupt source. All bits in registers ISR1 and ISR2 are copies of the
appropriate bits in different SPI registers. For a faster read-out, these bits are merged in ISR1 and ISR2. A reset cannot be
completed for registers ISR1 and ISR2.
Table 44. Interrupt Source Register 1 (ISR1)
Address
ISR
$021
Bit 7
Bit 6
Bit 5
Bit 4
R
Bit 3
Bit 2
Bit 1
Bit 0
HV
HTPW
MTPW
BATU
W
RESET
—
—
—
—
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BUSF
SPIE
WU
0
0
0
Table 45. Interrupt Source Register 2 (ISR2)
Address
ISR
$022
RESET
Bit 7
Bit 6
R
W
—
—
—
—
—
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Table 46. Transceiver Control/Status Register (TCR)
Address
TCR
$024
Bit 7
Bit 6
Bit 5
Bit 4
R
Bit 3
Bit 2
Bit 1
Bit 0
TOT
TSR2
TSR1
TSR0
TCR2
TCR1
TCR0
0
0
0
W
RESET
—
—
—
—
0
This register controls the state of the CAN transceiver (CAN transceiver is also dependent upon the SBC mode). When it is
read, this register reports the CAN transceiver state and a CAN over temperature condition.
Table 47. TCR / TSR Data
TCR2
TCR1
TCR0
Description
TSR2
TSR1
TSR0
0
0
0
Standard/Term VBAT
0
0
0
0
1
0
Standard/Rx Only
0
1
0
0
1
1
Standard/RxTx
0
1
1
TOT
1 = > Transceiver over temperature
0 = > Normal temperature
The MODE bit selects between the standard and extended physical layer mode. Any conditions forcing the transceiver to Term VBAT lead to
reset of TCR0 and TCRO1 bits. After power-ON reset all bits of the register are set to 0. The information TOT is latched. Reset TOT by reading the TCR. In case of RST = Low, the register content remains unchanged.
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TYPICAL APPLICATIONS
Auxiliary 5V
33389
C1
Ignition
C2
S0
S1
S2
VDD
C3
C4
RST
Rs0
RL
CANH
CANL
RTH
INT
CS
MISO
MOSI
SCK
RTL
RH
Rs1
RESET
INT
L0
L1
L2
CL1
Rp2
V2
VBAT
V3
CL0
Rp1
C6
V1
Auxiliary 12V
Rp0
C5
GND
SPI
TX
RX
CAN
GND
Rs2
CL2
CAN bus
Figure 22. Typical Application Schematic 1
33389
C1
Ignition
switch
C2
V3
Rp0
S0
Rs0
CL0
Rp1 Rs1
S1
CL1
Rp2
S2
V1
VBAT
L0
L1
L2 GND
Vdd
C3
33389
C4
Micro
reset
RST
Cr
Figure 24. Reset Duration Extension
Auxiliary
local 12V
Rs2
CL2
Figure 23. Typical Application: V3 Used as Auxiliary
ECU Supply
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TYPICAL APPLICATIONS
ARCHIVE INFORMATION
Auxiliary 5V
33389
C1
C2
C5
V2
VBAT
V1
Ignition
Auxiliary 12V
Rp0
S0
VDD
V3
RST
Rs0
CS
MISO
MOSI
SCK
RTL
RH
CAN bus # 1
RL
CANH
CANL
RTH
RESET
INT
INT
L0
L1
L2
CL0
C6
GND
SPI bus
TX
RX
SPI
CAN 1
CAN 2
VBAT INH VDD
RTL
RH
CAN bus # 2
RL
CANH MC33388
CANL
SCI
Tx/Rx
RTH GND
GND
+12V
INH
VSUP
LIN bus
1k
LIN
MC33399
Tx/Rx
GND
(Wake-up input linked to peripheral circuits: (ex: low speed CAN or LIN transceivers).
Figure 25. Typical Application Schematic 2
done at nominal voltage and temperature. By doing this, 5.0
The SBC offers several capabilities to help users debug
V is provided to the MCU VDD and reset lines.
their application.
• External bias of V1 and reset pin
Under this condition the SBC is not operational. However,
the reset pin is pulled low and is sinking 5 mA to ground. This
• Turn OFF software watchdog in the Stand-by mode
means, the external circuitry driving reset must have a
• Special debug samples with software watchdog disable at
current capability higher than 5 mA in order to drive the reset
power-up (contact local Motorola representative)
in the high-state.
DEBUG AND PROGRAM DOWNLOAD INTO FLASH
MEMORY
While the SBC is powered, it enters Normal Request mode
and expects during the 75 ms time period in the NR mode, an
SPI trigger word (to enter Normal mode and select the
watchdog time period). If this does not occur, the SBC enters
the Sleep mode and turns off V1.
When the software is debugged, and when using
development tools, it is not always easy to make sure these
events happen properly. It is thus possible to externally
power the V1 line with an external 5.0 V supply, and to force
the Reset pin to V1 or to and external 5.0 V. These can be
DISABLE OF SOFTWARE WATCHDOG IN STANDBY MODE
The software watchdog can be disable in Stand-by mode
only. In order to disable it the following operation must be
done:
• Write to MCR register–data 011 (bit 2, bit 1, bit 0)
• Write to MCVR register–data 011 (bit 2, bit 1, bit 0)
Then the SBC enters the Stand-by mode without software
watchdog. However the V2 can not be turn on, and the CAN
cell can not be used.
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PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ASH70273A listed below.
DH SUFFIX
VW SUFFIX (Pb-FREE)
20 PIN
PLASTIC PACKAGE
98ASH70273A
ISSUE E
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PACKAGING
PACKAGE DIMENSIONS
ARCHIVE INFORMATION
DH SUFFIX
VW SUFFIX (Pb-FREE)
20 PIN
PLASTIC PACKAGE
98ASH70273A
ISSUE E
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Freescale Semiconductor
45
ARCHIVE INFORMATION
PACKAGING
PACKAGE DIMENSIONS
ARCHIVE INFORMATION
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PACKAGING
PACKAGE DIMENSIONS
DW SUFFIX
EG SUFFIX (Pb-FREE)
28 PIN
PLASTIC PACKAGE
98ASB42345B
ISSUE G
33389
46
Analog Integrated Circuit Device Data
Freescale Semiconductor
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DW SUFFIX
EG SUFFIX (Pb-FREE)
28 PIN
PLASTIC PACKAGE
98ASB42345B
ISSUE G
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Analog Integrated Circuit Device Data
Freescale Semiconductor
47
ARCHIVE INFORMATION
PACKAGING
PACKAGE DIMENSIONS
ARCHIVE INFORMATION
REVISION HISTORY
DATE
5.0
3/2007
DESCRIPTION OF CHANGES
•
•
•
•
•
•
•
•
Added Revision History
Converted to the prevailing Freescale form and style
Entire document was edited for wording, labels, and technical accuracy.
Added the Pb-FREE package types VW and EG to the ordering information
Updated the package drawings
Added Peak Package Reflow Temperature During Reflow (4), (5) on page 7
Added notes (4) and (5)
Removed all references to MC33389ADW/R2, MC33389ADH/R2, MC33389CEG/R2,
and MC33389DEG/R2 from the data sheet.
• Restated MC33389DDW in the Device Variations on page 2
33389
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MC33389
Rev. 5.0
3/2007
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free
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