NXP Semiconductors
Data Sheet: Technical Data
MC56F847XX
Document Number MC56F847XX
Rev. 4.1, 01/2022
MC56F847XX
Supports the 56F84789VLL,
56F84786VLK, 56F84783VLH,
56F84769VLL, 56F84766VLK,
56F84763VLH
Features
• This family of digital signal controllers (DSCs) is
based on the 32-bit 56800EX core. Each device
combines, on a single chip, the processing power of a
DSP and the functionality of an MCU with a flexible
set of peripherals to support many target applications:
– Industrial control
– Home appliances
– Smart sensors
– Fire and security systems
– Switched-mode power supply and power
management
– Uninterruptible Power Supply (UPS)
– Solar and wind power generator
– Power metering
– Motor control (ACIM, BLDC, PMSM, SR, stepper)
– Handheld power tools
– Circuit breaker
– Medical device/equipment
– Instrumentation
– Lighting
• DSC based on 32-bit 56800EX core
– Up to 100 MIPS at 100 MHz core frequency
– DSP and MCU functionality in a unified, C-efficient
architecture
• On-chip memory
– Up to 288 KB (256 KB + 32 KB) flash memory,
including up to 32 KB FlexNVM
– Up to 32 KB RAM
– Up to 2 KB FlexRAM with EEE capability
– 100 MHz program execution from both internal
flash memory and RAM
– On-chip flash memory and RAM can be mapped
into both program and data memory spaces
• Analog
– Two high-speed, 8-channel, 12-bit ADCs with
dynamic x2, x4 programmable amplifier
– One 20-channel, 16-bit ADC
– Four analog comparators with integrated 6-bit DAC
references
– One 12-bit DAC
• PWMs and timers
– Two eFlexPWM modules with up to 24 PWM
outputs, one including 8 channels with high
resolution NanoEdge placement
– Two 16-bit quad timer (2 x 4 16-bit timers)
– Two Periodic Interval Timers (PITs)
– One Quadrature Decoder
– Two Programmable Delay Blocks (PDBs)
• Communication interfaces
– Three high-speed queued SCI (QSCI) modules with
LIN slave functionality
– Up to three queued SPI (QSPI) modules
– Two SMBus-compatible I2C ports
– One flexible controller area network (FlexCAN)
module
• Security and integrity
– Cyclic Redundancy Check (CRC) generator
– Computer operating properly (COP) watchdog
– External Watchdog Monitor (EWM)
• Clocks
– Two on-chip relaxation oscillators: 8 MHz (400 kHz
at standby mode) and 32 kHz
– Crystal / resonator oscillator
• System
– DMA controller
– Integrated power-on reset (POR) and low-voltage
interrupt (LVI) and brown-out reset module
– Inter-module crossbar connection
– JTAG/enhanced on-chip emulation (EOnCE) for
unobtrusive, real-time debugging
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Operating characteristics
– Single supply: 3.0 V to 3.6 V
– 5 V–tolerant I/O (except RESETB pin)
• LQFP packages:
– 64-pin
– 80-pin
– 100-pin
MC56F847XX, Rev. 4.1, 01/2022
2
NXP Semiconductors
Table of Contents
1
Overview................................................................................................. 4
7.1
Thermal handling ratings........................................................... 41
1.1
MC56F844xx/5xx/7xx product family.........................................4
7.2
Moisture handling ratings...........................................................41
1.2
56800EX 32-bit Digital Signal Controller (DSC) core................6
7.3
ESD handling ratings................................................................. 41
1.3
Operation parameters................................................................... 7
7.4
Voltage and current operating ratings........................................ 42
1.4
On-chip memory and memory protection.................................... 7
1.5
Interrupt Controller...................................................................... 8
8.1
General characteristics............................................................... 43
1.6
Peripheral highlights.................................................................... 8
8.2
AC electrical characteristics.......................................................44
1.7
Block diagrams...........................................................................15
8.3
Nonswitching electrical specifications.......................................45
2
MC56F847xx signal and pin descriptions.............................................18
8.4
Switching specifications.............................................................51
3
Signal groups.........................................................................................34
8.5
Thermal specifications............................................................... 52
4
Ordering parts........................................................................................35
4.1
5
6
7
8
9
General.................................................................................................. 43
Peripheral operating requirements and behaviors................................. 53
Determining valid orderable parts..............................................35
9.1
Core modules..............................................................................53
Part identification.................................................................................. 35
9.2
System modules..........................................................................54
5.1
Description................................................................................. 35
9.3
Clock modules............................................................................55
5.2
Format........................................................................................ 36
9.4
Memories and memory interfaces.............................................. 57
5.3
Fields.......................................................................................... 36
9.5
Analog........................................................................................ 60
5.4
Example......................................................................................36
9.6
PWMs and timers....................................................................... 69
Terminology and guidelines..................................................................36
9.7
Communication interfaces..........................................................70
6.1
Definition: Operating requirement............................................. 36
10 Design Considerations.......................................................................... 76
6.2
Definition: Operating behavior.................................................. 37
10.1 Thermal design considerations...................................................76
6.3
Definition: Attribute...................................................................37
10.2 Electrical design considerations................................................. 78
6.4
Definition: Rating.......................................................................38
10.3 Power-on Reset design considerations.......................................79
6.5
Result of exceeding a rating....................................................... 38
11 Obtaining package dimensions............................................................. 81
6.6
Relationship between ratings and operating requirements.........38
12 Pinout.................................................................................................... 81
6.7
Guidelines for ratings and operating requirements.................... 39
12.1 Signal Multiplexing and Pin Assignments................................. 81
6.8
Definition: Typical value........................................................... 39
12.2 Pinout diagrams..........................................................................85
6.9
Typical value conditions............................................................ 40
13 Product documentation..........................................................................88
Ratings...................................................................................................41
14 Revision history.................................................................................... 88
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
3
Overview
1 Overview
1.1 MC56F844xx/5xx/7xx product family
The following table lists major features, including features that differ among members of
the family. Features not listed are shared by all members of the family.
Table 1. 56F844xx/5xx/7xx family
Part
Number
MC56F84
789 786 783 769 766 763 553 550 543 540 587 585 567 565 462 452 451 442 441
Core freq. 100 100 100 100 100 100
(MHz)
Flash
memory
(KB)
256 256 256 128 128 128
80
80
80
80
80
80
80
80
60
60
60
60
60
96
96
64
64
256 256 128 128 128
96
96
64
64
FlevNVM/ 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2
FlexRAM
(KB)
Total flash 288 288 288 160 160 160 128 128
memory
(KB)1
96
96
288 288 160 160 160 128 128
96
96
RAM (KB)
8
8
32
8
8
32
32
32
24
24
24
16
16
32
24
24
24
16
16
Memory Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
resource
protection
Interrupt Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Controller
Windowed
Computer
Operating
Properly
(WCOP)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
External
Watchdog
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Periodic
Interrupt
Timer
(PIT)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Programm
able Delay
Block
(PDB)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Quad
Timer
(TMR)
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
2x4
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
4
NXP Semiconductors
Overview
Table 1. 56F844xx/5xx/7xx family (continued)
Part
Number
12-bit
Cyclic
ADC
Channels
(ADCA
and
ADCB)
MC56F84
789 786 783 769 766 763 553 550 543 540 587 585 567 565 462 452 451 442 441
2x8
2x8
2x8
2x8
2x8
2x8
2x8
2x5
2x8
2x5
2x8
2x8
2x8
2x8
2x8
2x8
2x5
2x8
2x5
12-bit
300 300 300 300 300 300 300 300 300 300 600 600 600 600 600 600 600 600 600
Cyclic
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADC
Conversio
n time
(ADCA
and
ADCB)
16
10
8
16
10
8
8
̶
8
̶
16
10
16
10
̶
8
̶
8
̶
High-res
channels
8
8
8
8
8
8
8
6
8
6
0
0
0
0
0
0
0
0
0
Standard
channels
4
1
1
4
1
1
1
0
1
0
12
12
12
12
9
9
6
9
6
Input
capture
channels2
12
9
9
12
9
9
9
6
9
6
12
12
12
12
9
9
6
9
6
Standard
channels
12
9
-
12
94
̶
̶
̶
̶
̶
12
94
12
94
̶
̶
̶
̶
̶
Input
capture
channels
12
7
-
12
7
̶
̶
̶
̶
̶
12
7
12
7
̶
̶
̶
̶
̶
12-bit
DAC
1
1
1
1
1
1
1
1
1
1
1
1
̶
̶
1
̶
̶
̶
̶
Quad
Decoder
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16-bit
SAR ADC
(with
Temperat
ure
Sensor)
channels
(ADCC)
PWMA
module:
PWMB
Module:3
DMA
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Analog
Comparat
ors (CMP)
4
4
4
4
4
4
4
3
4
3
4
4
4
4
4
4
3
4
3
QSCI
3
3
2
3
3
2
2
2
2
2
3
3
3
3
2
2
2
2
2
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
5
Overview
Table 1. 56F844xx/5xx/7xx family (continued)
Part
Number
MC56F84
789 786 783 769 766 763 553 550 543 540 587 585 567 565 462 452 451 442 441
QSPI
3
2
1
3
2
1
1
1
1
1
3
2
3
2
1
1
1
1
1
I2C/
SMBus
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
FlexCAN
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
GPIO
86
68
54
86
68
54
54
39
54
39
86
68
86
68
54
54
39
54
39
LQFP
package
pin count
100
80
64
100
80
64
64
48
64
48
100
80
100
80
64
64
48
64
48
1.
2.
3.
4.
Total flash memory includes FlexNVM, but assumes no FlexNVM is used with FlexRAM for EEPROM.
Input capture shares the pin with corresponding PWM channels.
PWMB is only available in 100-pin and 80-pin packages.
PWMB_3A and PWMB_3B outputs are available through the on-chip inter-module crossbar.
1.2 56800EX 32-bit Digital Signal Controller (DSC) core
• Efficient 32-bit 56800EX Digital Signal Processor (DSP) engine with modified dual
Harvard architecture:
• Three internal address buses
• Four internal data buses: two 32-bit primary buses, one 16-bit secondary data
bus, and one 16-bit instruction bus
• 32-bit data accesses
• Supports concurrent instruction fetches in the same cycle, and dual data accesses
in the same cycle
• 20 addressing modes
• As many as 100 million instructions per second (MIPS) at 100 MHz core frequency
• 162 basic instructions
• Instruction set supports both fractional arithmetic and integer arithmetic
• 32-bit internal primary data buses support 8-bit, 16-bit, and 32-bit data movement,
plus addition, subtraction, and logical operations
• Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator
(MAC) with dual parallel moves
• 32-bit arithmetic and logic multi-bit shifter
• Four 36-bit accumulators, including extension bits
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Bit reverse address mode, which effectively supports DSP and Fast Fourier
Transform algorithms
MC56F847XX, Rev. 4.1, 01/2022
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NXP Semiconductors
Overview
• Full shadowing of the register stack for zero-overhead context saves and restores:
nine shadow registers correspond to nine address registers (R0, R1, R2, R3, R4, R5,
N, N3, M01)
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions enable compact code
• Enhanced bit manipulation instruction set
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack, with the stack's depth limited only by
memory
• Priority level setting for interrupt levels
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging
that is independent of processor speed
1.3 Operation parameters
• Up to 100 MHz operation at -40 °C to 105 °C ambient temperature
• Single 3.3 V power supply
• Supply range: VDD - VSS = 2.7 V to 3.6 V, VDDA - VSSA = 2.7 V to 3.6 V
1.4 On-chip memory and memory protection
• Modified dual Harvard architecture permits as many as three simultaneous accesses
to program and data memory
• Internal flash memory with security and protection to prevent unauthorized access
• Memory resource protection (MRP) unit to protect supervisor programs and
resources from user programs
• Programming code can reside in flash memory during flash programming
• The dual-ported RAM controller supports concurrent instruction fetches and data
accesses, or dual data accesses, by the DSC core.
• Concurrent accesses provide increased performance.
• The data and instruction arrive at the core in the same cycle, reducing latency.
• On-chip memory
• Up to 144 KW program/data flash memory, including FlexNVM
• Up to 16 KW dual port data/program RAM
• Up to 16 KW FlexNVM, which can be used as additional program or data flash
memory
• Up to 1 KW FlexRAM, which can be configured as enhanced EEPROM (used in
conjunction with FlexNVM) or used as additional RAM
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
7
Peripheral highlights
1.5 Interrupt Controller
• Five interrupt priority levels
• Three user-programmable priority levels for each interrupt source: level 0, level
1, level 2
• Unmaskable level 3 interrupts include illegal instruction, hardware stack
overflow, misaligned data access, SWI3 instruction
• Interrupt level 3 is highest priority and non-maskable. Its sources include:
• Illegal instructions
• Hardware stack overflow
• SWI instruction
• EOnce interrupts
• Misaligned data accesses
• Lowest-priority software interrupt: level LP
• Support for nested interrupts, so that a higher priority level interrupt request can
interrupt lower priority interrupt subroutine
• Masking of interrupt priority level is managed by the 56800EX core
• Two programmable fast interrupts that can be assigned to any interrupt source
• Notification to System Integration Module (SIM) to restart clock when in wait and
stop states
• Ability to relocate interrupt vector table
1.6 Peripheral highlights
1.6.1 Enhanced Flex Pulse Width Modulator (eFlexPWM)
• Two PWM modules contain 4 identical submodules, each with up to 3 outputs per
submodule, and up to 100 MHz PWM operating clock
• 16 bits of resolution for center, edge-aligned, and asymmetrical PWMs
• PWMA with NanoEdge high resolution
• Fractional delay for enhanced resolution of the PWM period and edge placement
• Arbitrary PWM edge placement
• 390 ps PWM frequency and duty-cycle resolution when NanoEdge functionality
is enabled.
• Fractional clock digital dithering: 5-bit digital fractional clock accumulation for
enhanced resolution of PWM period and edge placement, which is effectively
equivalent to 390 ps resolution in the overall accumulative period.
• PWM outputs can be configured as complementary output pairs or independent
outputs
MC56F847XX, Rev. 4.1, 01/2022
8
NXP Semiconductors
Peripheral highlights
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PWMB with 10 ns resolution at 100 MHz PWM operation clock
Dedicated time-base counter with period and frequency control per submodule
Independent top and bottom deadtime insertion for each complementary pair
Independent control of both edges of each PWM output
Enhanced input capture and output compare functionality on each input:
• Channels not used for PWM generation can be used for buffered output compare
functions.
• Channels not used for PWM generation can be used for input capture functions.
• Enhanced dual edge capture functionality
Synchronization of submodule to external hardware (or other PWM) is supported.
Double-buffered PWM registers
• Integral reload rates from 1 to 16
• Half-cycle reload capability
Multiple output trigger events can be generated per PWM cycle via hardware.
Support for double-switching PWM outputs
Up to eight fault inputs can be assigned to control multiple PWM outputs
• Programmable filters for fault inputs
Independently programmable PWM output polarity
Individual software control of each PWM output
All outputs can be programmed to change simultaneously via a FORCE_OUT event.
PWMX pin can optionally output a third PWM signal from each submodule
Option to supply the source for each complementary PWM signal pair from any of
the following:
• Crossbar module outputs
• External ADC input, taking into account values set in ADC high and low limit
registers
1.6.2 12-bit Analog-to-Digital Converter (Cyclic type)
• Two independent 12-bit analog-to-digital converters (ADCs):
• 2 x 8-channel external inputs
• Built-in x1, x2, x4 programmable gain pre-amplifier
• Maximum ADC clock frequency up to 20 MHz, having period as low as 50 ns
• Single conversion time of 8.5 ADC clock cycles
• Additional conversion time of 6 ADC clock cycles
• Support of analog inputs for single-ended and differential conversions
• Sequential and parallel scan modes. Parallel mode includes simultaneous and
independent scan modes.
• First 8 samples of each ADC have offset, limit and zero-crossing calculation
supported
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
9
Peripheral highlights
• ADC conversions can be synchronized by any module connected to the internal
crossbar module, such as PWM, timer, GPIO, and comparator modules.
• Support for hardware-triggering and software-triggering conversions
• Support for a multi-triggering mode with a programmable number of conversions on
each trigger
• Each ADC has ability to scan and store up to 8 conversion results.
• Current injection protection
1.6.3 Inter-Module Crossbar and AND-OR-INVERT logic
• Provides generalized connections between and among on-chip peripherals: ADCs,
12-bit DAC, comparators, quad-timers, eFlexPWMs, PDBs, EWM, quadrature
decoder, and select I/O pins
• User-defined input/output pins for all modules connected to the crossbar
• DMA request and interrupt generation from the crossbar
• Write-once protection for all registers
• AND-OR-INVERT function provides a universal Boolean function generator that
uses a four-term sum-of-products expression, with each product term containing true
or complement values of the four selected inputs (A, B, C, D).
1.6.4 Comparator
•
•
•
•
•
•
•
Full rail-to-rail comparison range
Support for high and low speed modes
Selectable input source includes external pins and internal DACs
Programmable output polarity
6-bit programmable DAC as a voltage reference per comparator
Three programmable hysteresis levels
Selectable interrupt on rising-edge, falling-edge, or toggle of a comparator output
1.6.5 12-bit Digital-to-Analog Converter
• 12-bit resolution
• Powerdown mode
• Automatic mode allows the DAC to automatically generate pre-programmed output
waveforms, including square, triangle, and sawtooth waveforms (for applications like
slope compensation)
• Programmable period, update rate, and range
• Output can be routed to an internal comparator, or optionally to an off-chip
destination
MC56F847XX, Rev. 4.1, 01/2022
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NXP Semiconductors
Peripheral highlights
1.6.6 Periodic Interrupt Timer (PIT) Modules
• 16-bit counter with programmable count modulo
• PIT0 is master and PIT1 is slave (if synchronizing both PITs)
• The output signals of both PIT0 and PIT1 are internally connected to a peripheral
crossbar module
• Can run when the CPU is in Wait/Stop modes. Can also wake up the CPU from
Wait/Stop modes.
• In addition to its existing bus clock (up to 100 MHz), 3 alternate clock sources for
the counter clock are available:
• Crystal oscillator output
• 8 MHz / 400 kHz ROSC (relaxation oscillator output)
• On-chip low-power 32 kHz oscillator
1.6.7 Programmable Delay Block (PDB) Modules
•
•
•
•
16-bit counter with programmable count modulo and delay time
Counter is initiated by positive transition of internal or external trigger pulse
Support for synchronizing PWM and ADC conversions
Two PDB outputs can be ORed together to schedule two conversions from one input
trigger event
• PDB outputs can be used to schedule precise edge placement for a pulsed output that
generates the control signal for the CMP windowing comparison
• Support for continuous mode or single shot mode
• Bypass mode supported
1.6.8 Quad Timer
• Four 16-bit up/down counters, with a programmable prescaler for each counter
• Operation modes: edge count, gated count, signed count, capture, compare, PWM,
signal shot, single pulse, pulse string, cascaded, quadrature decode
• Programmable input filter
• Counting start can be synchronized across counters
1.6.9 Queued Serial Communications Interface (QSCI) modules
• Operating clock can be up to two times the CPU operating frequency
• Four-word-deep FIFOs available on both transmit and receive buffers
• Standard mark/space non-return-to-zero (NRZ) format
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
11
Peripheral highlights
•
•
•
•
•
13-bit integer and 3-bit fractional baud rate selection
Full-duplex or single-wire operation
Programmable 8-bit or 9-bit data format
Error detection capability
Two receiver wakeup methods:
• Idle line
• Address mark
• 1/16 bit-time noise detection
1.6.10 Queued Serial Peripheral Interface (QSPI) modules
•
•
•
•
•
•
•
•
•
Maximum 25 Mbit/s baud rate
Selectable baud rate clock sources for low baud rate communication
Baud rate as low as the maximum Baud rate / 4096
Full-duplex operation
Master and slave modes
Double-buffered operation with separate transmit and receive registers
Four-word-deep FIFOs available on transmit and receive buffers
Programmable length transmissions (2 bits to 16 bits)
Programmable transmit and receive shift order (MSB as first bit transmitted)
1.6.11 Inter-Integrated Circuit (I2C)/System Management Bus
(SMBus) modules
•
•
•
•
•
•
•
•
Compatible with I2C bus standard
Support for System Management Bus (SMBus) specification, version 2
Multi-master operation
General call recognition
10-bit address extension
Start/Repeat and Stop indication flags
Support for dual slave addresses or configuration of a range of slave addresses
Programmable glitch input filter
1.6.12 Flex Controller Area Network (FlexCAN) module
•
•
•
•
•
Clock source from PLL or XOSC/CLKIN
Implementation of CAN protocol Version 2.0 A/B
Standard and extended data frames
Data length of 0 to 8 bytes
Programmable bit rate up to 1 Mbps
MC56F847XX, Rev. 4.1, 01/2022
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NXP Semiconductors
Peripheral highlights
• Support for remote frames
• Sixteen Message Buffers: each Message Buffer can be configured as receive or
transmit, and supports standard and extended messages
• Individual Rx Mask Registers per Message Buffer
• Internal timer for time-stamping of received and transmitted messages
• Listen-only mode capability
• Programmable loopback mode, supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number, or
highest priority
• Global network time, synchronized by a specific message
• Low power modes, with programmable wakeup on bus activity
1.6.13 Computer Operating Properly (COP) watchdog
• Programmable timeout period
• Support for operation in all power modes: run mode, wait mode, stop mode
• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is
detected
• Selectable reference clock source in support of EN60730 and IEC61508
• Selectable clock sources:
• External crystal oscillator / External clock source
• On-chip low-power 32 kHz oscillator
• System bus (IPBus up to 100 MHz)
• 8 MHz / 400 kHz ROSC
• Support for interrupt triggered when the counter reaches the timeout value
1.6.14 External Watchdog Monitor (EWM)
•
•
•
•
Monitors external circuit as well as the software flow
Programmable timeout period
Interrupt capability prior to timeout
Independent output (EWM_OUT_b) that places external circuit (but not CPU and
peripheral) in a safe mode when EWM timeout occurs
• Selectable reference clock source in support of EN60730 and IEC61508
• Wait mode and Stop mode operation is not supported.
• Selectable clock sources:
• External crystal oscillator / External clock source
• On-chip low-power 32 kHz oscillator
• System bus (IPBus up to 100 MHz)
• 8 MHz / 400 kHz ROSC
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NXP Semiconductors
13
Clock sources
1.6.15 Power supervisor
• Power-on reset (POR) is released after VDD > 2.7 V during supply is ramped up;
CPU, peripherals, and JTAG/EOnCE controllers exit RESET state
• Brownout reset (VDD < 2.0 V)
• Critical warn low-voltage interrupt (LVI 2.2 V)
• Peripheral low-voltage warning interrupt (LVI 2.7 V)
1.6.16 Phase-locked loop
•
•
•
•
Wide programmable output frequency: 240 MHz to 400 MHz
Input reference clock frequency: 8 MHz to 16 MHz
Detection of loss of lock and loss of reference clock
Ability to power down
1.6.17 Clock sources
1.6.17.1 On-chip oscillators
• Tunable 8 MHz relaxation oscillator with 400 kHz at standby mode (divide-by-two
output)
• 32 kHz low frequency clock as secondary clock source for COP, EWM, PIT
1.6.17.2 Crystal oscillator
• Support for both high ESR crystal oscillator (ESR greater than 100 Ω) and ceramic
resonator
• Operating frequency: 4–16 MHz
1.6.18 Cyclic Redundancy Check (CRC) generator
•
•
•
•
•
Hardware 16/32-bit CRC generator
High-speed hardware CRC calculation
Programmable initial seed value
Programmable 16/32-bit polynomial
Error detection for all single, double, odd, and most multi-bit errors
MC56F847XX, Rev. 4.1, 01/2022
14
NXP Semiconductors
Clock sources
• Option to transpose input data or output data (CRC result) bitwise or bytewise,1
which is required for certain CRC standards
• Option for inversion of final CRC result
1.6.19 General Purpose I/O (GPIO)
•
•
•
•
•
•
•
5 V tolerance (except RESET_B )
Individual control of peripheral mode or GPIO mode for each pin
Programmable push-pull or open drain output
Configurable pullup or pulldown on all input pins
All pins (except JTAG, RESET_B ) default to be GPIO inputs
2 mA / 9 mA capability
Controllable output slew rate
1.7 Block diagrams
The 56800EX core is based on a modified dual Harvard-style architecture, consisting of
three execution units operating in parallel, and allowing as many as six operations per
instruction cycle. The MCU-style programming model and optimized instruction set
enable straightforward generation of efficient and compact code for the DSP and control
functions. The instruction set is also efficient for C compilers, to enable rapid
development of optimized control applications.
The device's basic architecture appears in Figure 1 and Figure 2. Figure 1 shows how the
56800EX system buses communicate with internal memories, and the IPBus interface
and the internal connections among the units of the 56800EX core. Figure 2 shows the
peripherals and control blocks connected to the IPBus bridge. See the specific device’s
Reference Manual for details.
1.
A bytewise transposition is not possible when accessing the CRC data register via 8-bit accesses. In this case, user
software must perform the bytewise transposition.
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
15
Clock sources
DSP56800EX Core
Program Control Unit
PC
LA
LA2
HWS0
HWS1
FIRA
OMR
SR
LC
LC2
FISR
Address
Generation
Unit
(AGU)
Instruction
Decoder
Interrupt
Unit
ALU1
ALU2
R0
R1
R2
R2
R3
R3
R4
R4
R5
R5
N
M01
N3
Looping
Unit
Program
Memory
SP
XAB1
XAB2
PAB
PDB
Data/
Program
RAM
CDBW
CDBR
XDB2
A2
B2
C2
D2
BitManipulation
Unit
Enhanced
OnCE™
JTAG TAP
Y
A1
B1
C1
D1
Y1
Y0
X0
MAC and ALU
A0
B0
C0
D0
IPBus
Interface
Data
Arithmetic
Logic Unit
(ALU)
Multi-Bit Shifter
Figure 1. 56800EX basic block diagram
MC56F847XX, Rev. 4.1, 01/2022
16
NXP Semiconductors
Clock sources
56800EX CPU
Address
Generation
Unit (AGU)
Bit
Manipulation
Unit
Arithmetic
Logic Unit
(ALU)
Core Data Bus
Secondary Data Bus
Crystal OSC
Internal 32 kHz
CRC
Clock MUX
Internal 8 MHz
PLL
Platform Bus
Crossbar Swirch
Program
Controller
(PC)
Program Bus
Memory Resource
Protection Unit
4
EOnCE
Flash Controller
and Cache
JTAG
Program/Data Flash
Up to 256KB
Data Flash
32KB
FlexRAM
2KB
Data/Program RAM
Up to 32KB
DMA Controller
Interrupt Controller
Watchdog (COP)
Power Management
Controller (PMC)
Periodic Interrupt
Timer (PIT) 0, 1
System Integration
Module (SIM)
Peripheral Bus
FlexCAN
I2C
0, 1
QSPI
0, 1, 2
QSCI
0, 1, 2
Quad Timer eFlexPWM A eFlexPWM B Quadrature
A&B
NanoEdge
Decoder
Inter Module Crossbar
Inputs
Inter Module
connection
Inter Module Crossbar Outputs
Inter-Module
Crossbar B
Peripheral Bus
AND-OR-INV
Logic
GPIO & Peripheral MUX
Inter-Module
Crossbar A
Inter Module Crossbar Outputs
Inter Module Crossbar Inputs
Package
Pins
EWM
ADC A ADC B
12-bit 12-bit
ADC C
16-bit
Comparators with
6-bit DAC A,B,C,D
DAC
12-bit
PDB
0, 1
Peripheral Bus
Figure 2. System diagram
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
17
MC56F847xx signal and pin descriptions
2 MC56F847xx signal and pin descriptions
After reset, each pin is configured for its primary function (listed first). Any alternative
functionality, shown in parentheses, must be programmed through the GPIO module
peripheral enable registers (GPIO_x_PER) and the SIM module GPIO peripheral select
(GPSx) registers. All GPIO ports can be individually programmed as an input or output
(using bit manipulation).
• There are 2 PWM modules: PWMA, PWMB. Each PWM module has 4 submodules:
PWMA has PWMA_0, PWMA_1, PWMA_2, PWMA_3; PWMB has PWMB_0,
PWMB_1, PWMB_2, PWMB_3. Each PWM module's submodules have 3 pins (A,
B, X) each, with the syntax for the pins being PWMA_0A, PWMA_0B, PWMA_0X,
and PWMA_1A, PWMA_1B, PWMA_1X, and so on. Each submodule pin can be
configured as a PWM output or as a capture input.
• PWMA_FAULT0, PWMA_FAULT1, and similar signals are inputs used to disable
selected PWMA (or PWMB) outputs, in cases where the fault conditions originate
off-chip.
• EWM_OUT_B is the output of the External Watchdog Module (EWM), and is active
low (denoted by the "_B" part of the syntax).
For the MC56F847XX products, which use 64-pin LQFP, 80-pin LQFP, and 100-pin
LQFP packages:
Table 2. Signal descriptions
Signal Name
100
LQFP
80
LQFP
64
LQFP
VDD
7
-
-
VDD
43
35
29
VDD
67
54
44
VDD
96
76
60
VSS
8
-
-
VSS
15
11
-
VSS
44
36
30
VSS
66
53
43
VSS
97
77
61
VDDA
31
26
VSSA
32
27
Type
State
During
Reset
Signal Description
Supply
Supply
I/O Power — Supplies 3.3 V power to the
chip I/O interface.
Supply
Supply
I/O Ground — Provide ground for the
device I/O interface.
22
Supply
Supply
Analog Power — Supplies 3.3 V power to
the analog modules. It must be connected
to a clean analog power supply.
23
Supply
Supply
Analog Ground — Supplies an analog
ground to the analog modules. It must be
connected to a clean power supply.
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
18
NXP Semiconductors
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
100
LQFP
80
LQFP
64
LQFP
VCAP
16
12
-
VCAP
35
30
26
VCAP
93
73
TDI
100
80
98
78
1
1
57
Connect a 2.2uF or greater bypass
capacitor between this pin and VSS to
stabilize the core voltage regulator output
required for proper device operation.
VCAP is used to observe core
voltage.
64
Input
Input,
internal
pullup
enabled
Test Data Input — Provides a serial input
data stream to the JTAG/EOnCE port. It is
sampled on the rising edge of TCK and has
an internal pullup resistor. After reset, the
default state is TDI.
Input/
Output
Input,
internal
pullup
enabled
GPIO Port D0
Output
Output
Test Data Output — This tri-stateable pin
provides a serial output data stream from
the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and it
changes on the falling edge of TCK. After
reset, the default state is TDO.
Input/
Output
Input,
internal
pullup
enabled
GPIO Port D1
Input
Input,
internal
pullup
enabled
Test Clock Input — This input pin provides
a gated clock to synchronize the test logic
and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a
pullup resistor. A Schmitt-trigger input is
used for noise immunity. After reset, the
default state is TCK.
Input/
Output
Input,
internal
pullup
enabled
GPIO Port D2
Input
Input,
internal
pullup
enabled
Test Mode Select Input — Used to
sequence the JTAG TAP controller state
machine. It is sampled on the rising edge of
TCK and has an internal pullup resistor.
After reset, the default state is TMS.
62
1
(GPIOD2)
TMS
99
79
Signal Description
On-chip
regulator
output
voltage
(GPIOD1)
TCK
State
During
Reset
On-chip
regulator
output
voltage
(GPIOD0)
TDO
Type
63
NOTE: Always tie the TMS pin to VDD
through a 2.2K resistor, if needed
to keep an on-board debug
capability. Otherwise, tie the TMS
pin directly to VDD.
(GPIOD3)
Input/
Output
Input,
internal
GPIO Port D3
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
19
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
100
LQFP
80
LQFP
64
LQFP
Type
State
During
Reset
Signal Description
pullup
enabled
RESETor RESETB
2
2
2
(GPIOD4)
GPIOA0
22
17
13
Input
Input,
internal
pullup
enabled
(This pin is
3.3V only.)
Reset — A direct hardware reset on the
processor. When RESET is asserted low,
the device is initialized and placed in the
reset state. A Schmitt-trigger input is used
for noise immunity. The internal reset signal
is deasserted synchronously with the
internal clocks after a fixed number of
internal clocks. After reset, the default state
is RESET. To filter noise on the RESETB
pin, install a capacitor (up to 0.1 uF) on it.
Input/
Input,
Open-drain internal
Output
pullup
enabled
GPIO Port D4 — Can be individually
programmed as an input or open-drain
output pin. RESET functionality is disabled
in this mode and the device can be reset
only through Power-On Reset (POR), COP
reset, or software reset.
Input/
Output
GPIO Port A0; after reset, the default state
is GPIOA0.
Input
(ANA0&CMPA_IN3)
Input
ANA0 is input to channel 0 of ADCA;
CMPA_IN3 is input 3 of analog comparator
A. When used as an analog input, the
signal goes to both places (ANA0 and
CMPA_IN3), but the glitch on this pin
during ADC sampling may interfere with
other analog inputs shared on this pin.
(CMPC_O)
Output
Analog comparator C output
GPIOA1
23
18
14
(ANA1&CMPA_IN0)
GPIOA2
(ANA2&VREFHA&CMPA_I
N1)
Input/
Output
Input
Input
24
19
15
Input/
Output
GPIO Port A1: After reset, the default state
is GPIOA1.
ANA1 is input to channel 1 of ADCA;
CMPA_IN0 is input 0 of analog comparator
A. When used as an analog input, the
signal goes to both places (ANA1 and
CMPA_IN0), but the glitch on this pin
during ADC sampling may interfere with
other analog inputs shared on this pin.
Input
Input
GPIO Port A2: After reset, the default state
is GPIOA2.
ANA2 is input to channel 2 of ADCA;
VREFHA is the reference high of ADCA;
CMPA_IN1 is input 1 of analog comparator
A. When used as an analog input, the
signal goes to both places (ANA2 and
CMPA_IN1), but the glitch on this pin
during ADC sampling may interfere with
other analog inputs shared on this pin. This
input can be configured as either ANA2 or
VREFHA using the ADCA control register.
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
20
NXP Semiconductors
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
GPIOA3
100
LQFP
25
80
LQFP
20
64
LQFP
16
(ANA3&VREFLA&CMPA_I
N2)
GPIOA4
21
16
12
20
15
11
(ANA7&ANC11)
Input/
Output
Input/
Output
19
14
10
Input/
Output
Input
13
9
Input/
Output
GPIO Port A3: After reset, the default state
is GPIOA3.
GPIO Port A4: After reset, the default state
is GPIOA4.
ANA4 is input to channel 4 of ADCA; ANC8
is input to channel 8 of ADCC; CMPD_IN0
is input 0 of analog comparator D. When
used as an analog input, the signal goes to
all three places (ANA4 and ANC8 and
CMPA_IN0), but the glitch on this pin
during ADC sampling may interfere with
other analog inputs shared on this pin.
Input
GPIO Port A5: After reset, the default state
is GPIOA5.
ANA5 is input to channel 5 of ADCA; ANC9
is input to channel 9 of ADCC. When used
as an analog input, the signal goes to both
places (ANA5 and ANC9), but the glitch on
this pin during ADC sampling may interfere
with other analog inputs shared on this pin.
Input
Input
17
Signal Description
ANA3 is input to channel 3 of ADCA;
VREFLA is the reference low of ADCA;
CMPA_IN2 is input 2 of analog comparator
A. When used as an analog input, the
signal goes to both places (ANA3 and
CMPA_IN2), but the glitch on this pin
during ADC sampling may interfere with
other analog inputs shared on this pin. This
input can be configured as either ANA3 or
VREFLA using the ADCA control register.
Input
(ANA6&ANC10)
GPIOA7
Input
Input
(ANA5&ANC9)
GPIOA6
Input/
Output
State
During
Reset
Input
(ANA4&ANC8&CMPD_IN0
)
GPIOA5
Type
GPIO Port A6: After reset, the default state
is GPIOA6.
ANA6 is input to channel 6 of ADCA;
ANC10 is input to channel 10 of ADCC.
When used as an analog input, the signal
goes to both places (ANA6 and ANC10),
but the glitch on this pin during ADC
sampling may interfere with other analog
inputs shared on this pin.
Input
Input
GPIO Port A7: After reset, the default state
is GPIOA7.
ANA7 is input to channel 7 of ADCA;
ANC11 is input to channel 11 of ADCC.
When used as an analog input, the signal
goes to both places (ANA7 and ANC11),
but the glitch on this pin during ADC
sampling may interfere with other analog
inputs shared on this pin.
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
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21
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
GPIOA8
100
LQFP
18
80
LQFP
-
64
LQFP
-
(ANC16&CMPD_IN1)
GPIOA9
14
-
-
13
-
-
37
32
-
(ANB1&CMPB_IN0)
Input
Input/
Output
Input/
Output
33
28
24
Input/
Output
Input
29
25
Input/
Output
GPIO Port A9: After reset, the default state
is GPIOA9.
GPIO Port A10: After reset, the default
state is GPIOA10.
ANC18 is input to channel 18 of ADCC;
CMPD_IN3 is input 3 of analog comparator
D. When used as an analog input, the
signal goes to both places (ANC18 and
CMPD_IN3), but the glitch on this pin
during ADC sampling may interfere with
other analog inputs shared on this pin.
Input
GPIO Port A11: After reset, the default
state is GPIOA11.
ANC19 is input to channel 19 of ADCC.
VREFHC is the analog reference high of
ADCC.
Input
Input
34
GPIO Port A8: After reset, the default state
is GPIOA8.
ANC17 is input to channel 17 of ADCC;
CMPD_IN2 is input 2 of analog comparator
D. When used as an analog input, the
signal goes to both places (ANC17 and
CMPD_IN2), but the glitch on this pin
during ADC sampling may interfere with
other analog inputs shared on this pin.
Input
(ANB0&CMPB_IN3)
GPIOB1
Input/
Output
Signal Description
ANC16 is input to channel 16 of ADCC;
CMPD_IN1 is input 1 of analog comparator
D. When used as an analog input, the
signal goes to both places (ANC16 and
CMPD_IN1), but the glitch on this pin
during ADC sampling may interfere with
other analog inputs shared on this pin.
Input
(ANC19&VREFHC)
GPIOB0
Input
Input
(ANC18&CMPD_IN3)
GPIOA11
Input/
Output
State
During
Reset
Input
(ANC17&CMPD_IN2)
GPIOA10
Type
GPIO Port B0: After reset, the default state
is GPIOB0.
ANB0 is input to channel 0 of ADCB;
CMPB_IN3 is input 3 of analog comparator
B. When used as an analog input, the
signal goes to both places (ANB0 and
CMPB_IN3), but the glitch on this pin
during ADC sampling may interfere with
other analog inputs shared on this pin.
Input
Input
GPIO Port B1: After reset, the default state
is GPIOB1.
ANB1 is input to channel 1 of ADCB;
CMPB_IN0 is input 0 of analog comparator
B. When used as an analog input, the
signal goes to both places (ANB1 and
CMPB_IN0), but the glitch on this pin
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
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NXP Semiconductors
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
100
LQFP
80
LQFP
64
LQFP
Type
State
During
Reset
Signal Description
during ADC sampling may interfere with
other analog inputs shared on this pin.
GPIOB2
36
31
27
(ANB2&VREFHB&CMPC_I
N3)
GPIOB3
42
34
28
30
25
21
Input
Input/
Output
29
24
20
Input/
Output
Input
23
19
Input/
Output
GPIO Port B4: After reset, the default state
is GPIOB4.
ANB4 is input to channel 4 of ADCB;
ANC12 is input to channel 12 of ADCC;
CMPC_IN1 is input 1 of analog comparator
C. When used as an analog input, the
signal goes to all three places (ANB4 and
ANC12 and CMPC_IN1), but the glitch
during ADC sampling on this pin may
interfere with other analog inputs shared on
this pin.
Input
Input
28
GPIO Port B3: After reset, the default state
is GPIOB3.
ANB3 is input to channel 3 of ADCB;
VREFLB is the reference low of ADCB;
CMPC_IN0 is input 0 of analog comparator
C. When used as an analog input, the
signal goes to both places (ANB3 and
CMPC_IN0), but the glitch during ADC
sampling on this pin may interfere with
other analog inputs shared on this pin. This
input can be configured as either ANB3 or
VREFLB using the ADCB control register.
Input
(ANB5&ANC13&CMPC_IN
2)
GPIOB6
Input/
Output
GPIO Port B2: After reset, the default state
is GPIOB2.
ANB2 is input to channel 2 of ADCB;
VREFHB is the reference high of ADCB;
CMPC_IN3 is input 3 of analog comparator
C. When used as an analog input, the
signal goes to both places (ANB2 and
CMPC_IN3), but the glitch during ADC
sampling on this pin may interfere with
other analog inputs shared on this pin. This
input can be configured as either ANB2 or
VREFHB using the ADCB control register.
Input
(ANB4&ANC12&CMPC_IN
1)
GPIOB5
Input
Input
(ANB3&VREFLB&CMPC_I
N0)
GPIOB4
Input/
Output
GPIO Port B5: After reset, the default state
is GPIOB5.
ANB5 is input to channel 5 of ADCB;
ANC13 is input to channel 13 of ADCC;
CMPC_IN2 is input 2 of analog comparator
C. When used as an analog input, the
signal goes to all three places (ANB5 and
ANC13 and CMPC_IN2), but the glitch
during ADC sampling on this pin may
interfere with other analog inputs shared on
this pin.
Input
GPIO Port B6: After reset, the default state
is GPIOB6.
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
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23
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
100
LQFP
80
LQFP
64
LQFP
(ANB6&ANC14&CMPB_IN
1)
GPIOB7
26
21
17
Input/
Output
38
33
33
Input/
Output
Input
-
-
Input/
Output
GPIO Port B7: After reset, the default state
is GPIOB7.
ANB7 is input to channel 7 of ADCB;
ANC15 is input to channel 14 of ADCC;
CMPB_IN2 is input 2 of analog comparator
B. When used as an analog input, the
signal goes to all three places (ANB7 and
ANC15 and CMPB_IN2), but the glitch
during ADC sampling on this pin may
interfere with other analog inputs shared on
this pin.
Input
Input
39
Signal Description
ANB6 is input to channel 6 of ADCB;
ANC14 is input to channel 14 of ADCC;
CMPB_IN1 is input 1 of analog comparator
B. When used as an analog input, the
signal goes to all three places (ANB6 and
ANC14 and CMPB_IN1), but the glitch
during ADC sampling on this pin may
interfere with other analog inputs shared on
this pin.
Input
(ANC20&VREFLC)
GPIOB9
State
During
Reset
Input
(ANB7&ANC15&CMPB_IN
2)
GPIOB8
Type
GPIO Port B8: After reset, the default state
is GPIOB8.
ANC20 is input to channel 20 of ADCC;
VREFLC is the reference low of ADCC .
Input
GPIO Port B9: After reset, the default state
is GPIOB9.
(ANC21)
Input
Input to channel 21 of ADCC
(XB_IN9)
Input
Crossbar module input 9
(MISO2)
Input/
Output
Master in/slave out for SPI2 —In master
mode, MISO2 pin is the data input. In slave
mode, MISO2 pin is the data output. The
MISO line of a slave device is placed in the
high-impedance state if the slave device is
not selected.
GPIOB10
40
-
-
Input/
Output
Input
GPIO Port B10: After reset, the default
state is GPIOB10.
(ANC22)
Input
Input to channel 22 of ADCC
(XB_IN8)
Input
Crossbar module input 8
(MOSI2)
Input/
Output
Master out/slave in for SPI2— In master
mode, MOSI2 pin is the data output. In
slave mode, MOSI2 pin is the data input.
GPIOB11
41
-
-
Input/
Output
Input
GPIO Port B11: After reset, the default
state is GPIOB11.
(ANC23)
Input
Input to channel 23 of ADCC
(XB_IN7)
Input
Crossbar module input 7
(SCLK2)
Input/
Output
SPI2 serial clock — In master mode,
SCLK2 pin is an output, clocking slaved
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
24
NXP Semiconductors
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
100
LQFP
80
LQFP
64
LQFP
Type
State
During
Reset
Signal Description
listeners. In slave mode, SCLK2 pin is the
data clock input.
GPIOC0
3
3
3
Input/
Output
Input
GPIO Port C0: After reset, the default state
is GPIOC0.
(EXTAL)
Analog
Input
The external crystal oscillator input
(EXTAL) connects the internal crystal
oscillator input to an external crystal or
ceramic resonator.
(CLKIN0)
Input
External clock input.1
GPIOC1
4
4
4
(XTAL)
GPIOC2
Input/
Output
Input
Analog
Output
5
5
5
Input/
Output
GPIO Port C1: After reset, the default state
is GPIOC1.
The external crystal oscillator output
(XTAL) connects the internal crystal
oscillator output to an external crystal or
ceramic resonator.
Input
GPIO Port C2: After reset, the default state
is GPIOC2.
(TXD0)
Output
SCI0 transmit data output or transmit/
receive in single-wire operation
(TB0)
Input/
Output
Quad timer module B channel 0 input/
output
(XB_IN2)
Input
Crossbar module input 2
(CLKO0)
Output
Buffered clock output 0: the clock source is
selected by clockout select (CLKOSEL) bits
in the clock output select register
(CLKOUT) of the SIM.
GPIOC3
11
9
7
Input/
Output
Input
GPIO Port C3: After reset, the default state
is GPIOC3.
(TA0)
Input/
Output
Quad timer module A channel 0 input/
output
(CMPA_O)
Output
Analog comparator A output
(RXD0)
Input
SCI0 receive data input
(CLKIN1)
Input
External clock input 1
GPIOC4
12
10
8
Input/
Output
Input
GPIO Port C4: After reset, the default state
is GPIOC4.
(TA1)
Input/
Output
Quad timer module A channel 1 input/
output
(CMPB_O)
Output
Analog comparator B output
(XB_IN8)
Input
Crossbar module input 8
(EWM_OUT_B)
Output
External Watchdog Module output
GPIOC5
(DACO)
27
22
18
Input/
Output
Input
Analog
Output
GPIO Port C5: After reset, the default state
is GPIOC5.
12-bit digital-to-analog output
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
25
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
100
LQFP
80
LQFP
64
LQFP
(XB_IN7)
GPIOC6
Type
State
During
Reset
Input
49
39
31
Input/
Output
Signal Description
Crossbar module input 7
Input
GPIO Port C6: After reset, the default state
is GPIOC6
(TA2)
Input/
Output
Quad timer module A channel 2 input/
output
(XB_IN3)
Input
Crossbar module input 3
(CMP_REF)
Analog
Input
Input 5 of analog comparator A and B and
C and D.
GPIOC7
50
40
32
Input/
Output
Input
GPIO Port C7: After reset, the default state
is GPIOC7.
(SS0_B)
Input/
Output
In slave mode, SS0_B indicates to the SPI
module that the current transfer is to be
received.
(TXD0)
Output
SCI0 transmit data output or transmit/
receive in single-wire operation
GPIOC8
52
41
33
Input/
Output
Input
GPIO Port C8: After reset, the default state
is GPIOC8.
(MISO0)
Input/
Output
Master in/slave out —In master mode,
MISO0 pin is the data input. In slave mode,
MISO0 pin is the data output. The MISO0
line of a slave device is placed in the highimpedance state if the slave device is not
selected.
(RXD0)
Input
SCI0 receive data input.
(XB_IN9)
Input
Crossbar module input 9
GPIOC9
53
42
34
Input/
Output
Input
GPIO Port C9: After reset, the default state
is GPIOC9.
(SCLK0)
Input/
Output
SPI0 serial clock — In master mode,
SCLK0 pin is an output, clocking slaved
listeners. In slave mode, SCLK0 pin is the
data clock input.
(XB_IN4)
Input
Crossbar module input 4
GPIOC10
54
43
35
Input/
Output
Input
GPIO Port C10: After reset, the default
state is GPIOC10.
(MOSI0)
Input/
Output
Master out/slave in — In master mode,
MOSI0 pin is the data output. In slave
mode, MOSI0 pin is the data input.
(XB_IN5)
Input
Crossbar module input 5
(MISO0)
Input/
Output
Master in/slave out — In master mode,
MISO0 pin is the data input. In slave mode,
MISO0 pin is the data output. The MISO0
line of a slave device is placed in the highimpedance state if the slave device is not
selected.
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
26
NXP Semiconductors
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
GPIOC11
100
LQFP
58
80
LQFP
47
64
LQFP
37
Type
Input/
Output
State
During
Reset
Input
Signal Description
GPIO Port C11: After reset, the default
state is GPIOC11.
(CANTX)
Open-drain
Output
CAN transmit data output
(SCL1)
Input/
Open-drain
Output
I2C1 serial clock
(TXD1)
Output
SCI1 transmit data output or transmit/
receive in single wire operation
GPIOC12
59
48
38
Input/
Output
Input
GPIO Port C12: After reset, the default
state is GPIOC12.
(CANRX)
Input
CAN receive data input
(SDA1)
Input/
Open-drain
Output
I2C1 serial data line
(RXD1)
Input
SCI1 receive data input
GPIOC13
76
61
49
Input/
Output
Input
GPIO Port C13: After reset, the default
state is GPIOC13.
(TA3)
Input/
Output
Quad timer module A channel 3 input/
output
(XB_IN6)
Input
Crossbar module input 6
(EWM_OUT_B)
Output
External Watchdog Module output
GPIOC14
87
70
55
Input/
Output
Input
GPIO Port C14: After reset, the default
state is GPIOC14.
2
(SDA0)
Input/
Open-drain
Output
I C0 serial data line
(XB_OUT4)
Output
Crossbar module output 4
GPIOC15
88
71
56
Input/
Output
Input
GPIO Port C15: After reset, the default
state is GPIOC15.
(SCL0)
Input/
Open-drain
Output
I2C0 serial clock
(XB_OUT5)
Input
Crossbar module output 5
GPIOD5
10
8
-
Input/
Output
Input
GPIO Port D5: After reset, the default state
is GPIOD5.
(RXD2)
Input
SCI2 receive data input
(XB_IN5)
Input
Crossbar module input 5
(XB_OUT9)
Output
Crossbar module output 9
GPIOD6
(TXD2)
9
7
-
Input/
Output
Input
Output
GPIO Port D6: After reset, the default state
is GPIOD6.
SCI2 transmit data output or transmit/
receive in single-wire operation
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
27
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
100
LQFP
80
LQFP
64
LQFP
Type
State
During
Reset
Signal Description
(XB_IN4)
Input
Crossbar module input 4
(XB_OUT8)
Output
Crossbar module output 8
GPIOD7
47
37
-
Input/
Output
Input
GPIO Port D7: After reset, the default state
is GPIOD7.
(XB_OUT11)
Output
Crossbar module output 11
(XB_IN7)
Input
Crossbar module input 7
(MISO1)
Input/
Output
Master in/slave out for SPI1 —In master
mode, MISO1 pin is the data input. In slave
mode, MISO1 pin is the data output. The
MISO line of a slave device is placed in the
high-impedance state if the slave device is
not selected.
GPIOE0
68
55
45
PWMA_0B
GPIOE1
69
56
46
74
59
47
Input
Input/
Output
75
60
48
Input/
Output
Input
65
51
Input/
Output
GPIO Port E2: After reset, the default state
is GPIOE2.
PWM module A (NanoEdge), submodule 1,
output B or input capture B
Input
Input/
Output
82
GPIO Port E1: After reset, the default state
is GPIOE1.
PWM module A (NanoEdge), submodule 0,
output A or input capture A
Input/
Output
(PWMA_1A)
GPIOE4
Input/
Output
GPIO Port E0: After reset, the default state
is GPIOE0.
PWM module A (NanoEdge), submodule 0,
output B or input capture B
Input/
Output
(PWMA_1B)
GPIOE3
Input
Input/
Output
(PWMA_0A)
GPIOE2
Input/
Output
GPIO Port E3: After reset, the default state
is GPIOE3.
PWM module A (NanoEdge), submodule 1,
output A or input capture A
Input
GPIO Port E4: After reset, the default state
is GPIOE4.
(PWMA_2B)
Input/
Output
PWM module A (NanoEdge), submodule 2,
output B or input capture B
(XB_IN2)
Input
Crossbar module input 2
GPIOE5
83
66
52
Input/
Output
Input
GPIO Port E5: After reset, the default state
is GPIOE5.
(PWMA_2A)
Input/
Output
PWM module A (NanoEdge), submodule 2,
output A or input capture A
(XB_IN3)
Input
Crossbar module input 3
GPIOE6
84
67
53
Input/
Output
Input
GPIO Port E6: After reset, the default state
is GPIOE6.
(PWMA_3B)
Input/
Output
PWM module A (NanoEdge), submodule 3,
output B or input capture B
(XB_IN4)
Input
Crossbar module input 4
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
28
NXP Semiconductors
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
100
LQFP
80
LQFP
64
LQFP
(PWMB_2B)
GPIOE7
Type
State
During
Reset
Input/
Output
85
68
54
Input/
Output
Signal Description
Note: PWMB_2B is not available on
64LQFP devices.
Input
GPIO Port E7: After reset, the default state
is GPIOE7.
(PWMA_3A)
Input/
Output
PWM module A (NanoEdge), submodule 3,
output A or input capture A
(XB_IN5)
Input
Crossbar module input 5
(PWMB_2A)
Input/
Output
PWM module B, submodule 2, output A or
input capture A. Note: PWMB_2A is not
available on 64LQFP devices.
GPIOE8
72
-
-
Input/
Output
Input
GPIO Port E8: After reset, the default state
is GPIOE8.
(PWMB_2B)
Input/
Output
PWM module B, submodule 2, output B or
input capture B
(PWMA_FAULT0)
Input
PWM module A fault input 0 is used for
disabling selected PWM module A outputs
in cases where fault conditions originate
off-chip
GPIOE9
73
-
-
Input/
Output
Input
GPIO Port E9: After reset, the default state
is GPIOE9.
(PWMB_2A)
Input/
Output
PWM module B, submodule 2, output A or
input capture A
(PWMA_FAULT1)
Input
PWM module A fault input 1 is used for
disabling selected PWM module A outputs
in cases where fault conditions originate
off-chip
GPIOF0
55
44
36
Input/
Output
Input
GPIO Port F0: After reset, the default state
is GPIOF0.
(XB_IN6)
Input
Crossbar module input 6
(TB2)
Input/
Output
Quad timer module B channel 2 input/
output
(SCLK1)
Input/
Output
SPI1 serial clock — In master mode,
SCLK1 pin is an output, clocking slaved
listeners. In slave mode, SCLK1 pin is the
data clock input. Note: SCLK1 is not
available on 64LQFP and 48LQFP devices.
GPIOF1
77
62
50
Input/
Output
Input
GPIO Port F1: After reset, the default state
is GPIOF1.
(CLKO1)
Output
Buffered clock output 1: the clock source is
selected by clockout select (CLKOSEL) bits
in the clock output select register
(CLKOUT) of the SIM.
(XB_IN7)
Input
Crossbar module input 6
(CMPD_O)
Output
Analog comparator D output
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
29
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
GPIOF2
100
LQFP
60
80
LQFP
49
64
LQFP
39
Type
Input/
Output
State
During
Reset
Input
Signal Description
GPIO Port F2: After reset, the default state
is GPIOF2.
(SCL1)
Input/
Open-drain
Output
I2C1 serial clock
(XB_OUT6)
Output
Crossbar module output 6
GPIOF3
61
50
40
Input/
Output
Input
GPIO Port F3: After reset, the default state
is GPIOF3.
(SDA1)
Input/
Open-drain
Output
I2C1 serial data line
(XB_OUT7)
Output
Crossbar module output 7
GPIOF4
62
51
41
Input/
Output
Input
GPIO Port F4: After reset, the default state
is GPIOF4.
(TXD1)
Output
SCI1 transmit data output or transmit/
receive in single wire operation
(XB_OUT8)
Output
Crossbar module output 8
GPIOF5
63
52
42
Input/
Output
Input
GPIO Port F5: After reset, the default state
is GPIOF5.
(RXD1)
Input
SCI1 receive data input
(XB_OUT9)
Output
Crossbar module output 9
GPIOF6
94
74
58
Input/
Output
Input
GPIO Port F6: After reset, the default state
is GPIOF6.
(TB2)
Input/
Output
Quad timer module B Channel 2 input/
output
(PWMA_3X)
Input/
Output
PWM module A, submodule 3, output X or
input capture X
(PWMB_3X)
Input/
Output
PWM module B, submodule 3, output X or
input capture X. Note: PWMB_3X is not
available on 64LQFP devices.
(XB_IN2)
Input
Crossbar module input 2
GPIOF7
95
75
59
Input/
Output
Input
GPIO Port F7: After reset, the default state
is GPIOF7.
(TB3)
Input/
Output
Quad timer module B Channel 3 input/
output
(CMPC_O)
Output
Analog comparator C output
(SS1_B)
Input/
Output
In slave mode, SS1_B indicates to the SPI1
module that the current transfer is to be
received. Note: SS1_B is not available on
64LQFP devices.
(XB_IN3)
Input
Crossbar module input 3
GPIOF8
(RXD0)
6
6
6
Input/
Output
Input
Input
GPIO Port F8: After reset, the default state
is GPIOF8.
SCI0 receive data input
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
30
NXP Semiconductors
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
100
LQFP
80
LQFP
64
LQFP
Type
State
During
Reset
Signal Description
(TB1)
Input/
Output
Quad timer module B channel 1 input/
output
(CMPD_O)
Output
Analog comparator D output
GPIOF9
57
46
-
Input/
Output
Input
GPIO Port F9: After reset, the default state
is GPIOF9.
(RXD2)
Input
SCI2 receive data input
(PWMA_FAULT7)
Input
PWM module A fault input 7 is used for
disabling selected PWM module A outputs
in cases where fault conditions originate
off-chip
(PWMB_FAULT7)
Input
PWM module B fault input 7 is used for
disabling selected PWM module B outputs
in cases where fault conditions originate
off-chip
(XB_OUT11)
Output
Crossbar module output 11
GPIOF10
56
45
-
Input/
Output
Input
GPIO Port F10: After reset, the default
state is GPIOF10.
(TXD2)
Input/
Output
SCI2 transmit data output or transmit/
receive in single-wire operation
(PWMA_FAULT6)
Input
PWM module A fault input 6 is used for
disabling selected PWM module A outputs
in cases where fault conditions originate
off-chip
(PWMB_FAULT6)
Input
PWM module B fault input 6 is used for
disabling selected PWM module B outputs
in cases where fault conditions originate
off-chip
(XB_OUT10)
Output
Crossbar module output 10
GPIOF11
45
-
-
(TXD0)
Input
Output
(XB_IN11)
GPIOF12
Input/
Output
SCI0 transmit data output or transmit/
receive in single-wire operation
Input
89
-
-
Input/
Output
GPIO Port F11: After reset, the default
state is GPIOF11.
Crossbar module input 11
Input
GPIO Port F12: After reset, the default
state is GPIOF12.
(MISO1)
Input/
Output
Master in/slave out for SPI1 —In master
mode, MISO1 pin is the data input. In slave
mode, MISO1 pin is the data output. The
MISO line of a slave device is placed in the
high-impedance state if the slave device is
not selected.
(PWMB_FAULT2)
Input
PWM module B fault input 2 is used for
disabling selected PWM module B outputs
in cases where fault conditions originate
off-chip
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
31
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
GPIOF13
100
LQFP
90
80
LQFP
-
64
LQFP
-
Type
Input/
Output
State
During
Reset
Input
Signal Description
GPIO Port F13: After reset, the default
state is GPIOF13.
(MOSI1)
(PWMB_FAULT1)
GPIOF14
Input
91
-
-
Input/
Output
PWM module B fault input 1 is used for
disabling selected PWM module B outputs
in cases where fault conditions originate
off-chip
Input
GPIO Port F14: After reset, the default
state is GPIOF14.
(SCLK1)
Input/
Output
SPI1 serial clock — In master mode,
SCLK1 pin is an output, clocking slaved
listeners. In slave mode, SCLK1 pin is the
data clock input. Note: SCLK1 is not
available on 48LQFP and 64LQFP devices.
(PWMB_FAULT0)
Input
PWM module B fault input 0 is used for
disabling selected PWM module B outputs
in cases where fault conditions originate
off-chip
GPIOF15
46
-
-
(RXD0)
Input
Input
(XB_IN10)
GPIOG0
Input/
Output
SCI0 receive data input
Input
78
63
-
Input/
Output
GPIO Port F15: After reset, the default
state is GPIOF15.
Crossbar module input 10
Input
GPIO Port G0: After reset, the default state
is GPIOG0.
(PWMB_1B)
Input/
Output
PWM module B, submodule 1, output B or
input capture B
(XB_OUT6)
Output
Crossbar module output 6
GPIOG1
79
64
-
Input/
Output
Input
GPIO Port G1: After reset, the default state
is GPIOG1.
(PWMB_1A)
Input/
Output
PWM module B, submodule 1, output A or
input capture A
(XB_OUT7)
Output
Crossbar module output 7
GPIOG2
70
57
-
Input/
Output
Input
GPIO Port G2: After reset, the default state
is GPIOG2.
(PWMB_0B)
Input/
Output
PWM module B, submodule 0, output B or
input capture B
(XB_OUT4)
Output
Crossbar module output 4
GPIOG3
71
58
-
Input/
Output
Input
GPIO Port G3: After reset, the default state
is GPIOG3.
(PWMB_0A)
Input/
Output
PWM module B, submodule 0, output A or
input capture A
(XB_OUT5)
Output
Crossbar module output 5
GPIOG4
80
-
-
Input/
Output
Input
GPIO Port G4: After reset, the default state
is GPIOG4.
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
32
NXP Semiconductors
MC56F847xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
100
LQFP
80
LQFP
64
LQFP
Type
State
During
Reset
Signal Description
(PWMB_3B)
Input/
Output
PWM module B, submodule 3, output B or
input capture B
(PWMA_FAULT2)
Input
PWM module A fault input 2 is used for
disabling selected PWM module A outputs
in cases where fault conditions originate
off-chip
GPIOG5
81
-
-
Input/
Output
Input
GPIO Port G5: After reset, the default state
is GPIOG5.
(PWMB_3A)
Input/
Output
PWM module B, submodule 3, output A or
input capture A
(PWMA_FAULT3)
Input
PWM module A fault input 3 is used for
disabling selected PWM module A outputs
in cases where fault conditions originate
off-chip
GPIOG6
86
69
-
Input/
Output
Input
GPIO Port G6: After reset, the default state
is GPIOG6.
(PWMA_FAULT4)
Input
PWM module A fault input 4 is used for
disabling selected PWM module A outputs
in cases where fault conditions originate
off-chip
(PWMB_FAULT4)
Input
PWM module B fault input 4 is used for
disabling selected PWM module B outputs
in cases where fault conditions originate
off-chip
(TB2)
Input/
Output
Quad timer module B channel 2 input/
output
(XB_OUT8)
Output
Crossbar module output 8
GPIOG7
92
72
-
Input/
Output
Input
GPIO Port G7: After reset, the default state
is GPIOG7.
(PWMA_FAULT5)
Input
PWM module A fault input 5 is used for
disabling selected PWM module A outputs
in cases where fault conditions originate
off-chip
(PWMB_FAULT5)
Input
PWM module B fault input 5 is used for
disabling selected PWM module B outputs
in cases where fault conditions originate
off-chip
(XB_OUT9)
Output
Crossbar module output 9
GPIOG8
64
-
-
Input/
Output
Input
GPIO Port G8: After reset, the default state
is GPIOG8.
(PWMB_0X)
Input/
Output
PWM module B, submodule 0, output X or
input capture X
(PWMA_0X)
Input/
Output
PWM module A, submodule 0, output X or
input capture X
(TA2)
Input/
Output
Quad timer module A channel 2 input/
output
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
33
Signal groups
Table 2. Signal descriptions (continued)
Signal Name
100
LQFP
80
LQFP
64
LQFP
(XB_OUT10)
GPIOG9
Type
State
During
Reset
Output
65
-
-
Input/
Output
Signal Description
Crossbar module output 10
Input
GPIO Port G9: After reset, the default state
is GPIOG9.
(PWMB_1X)
Input/
Output
PWM module B, submodule 1, output X or
input capture X
(PWMA_1X)
Input/
Output
PWM module A, submodule 1, output X or
input capture X
(TA3)
Input/
Output
Quad timer module A channel 3 input/
output
(XB_OUT11)
Output
Crossbar module output 11
GPIOG10
51
-
-
Input/
Output
Input
GPIO Port G10: After reset, the default
state is GPIOG10.
(PWMB_2X)
Input/
Output
PWM module B, submodule 2, output X or
input capture X
(PWMA_2X)
Input/
Output
PWM module A, submodule 2, output X or
input capture X
(XB_IN8)
Input
Crossbar module input 8
(SS2_B)
Input/
Output
In slave mode, SS2_B indicates to the SPI2
module that the current transfer is to be
received.
GPIOG11
48
38
-
Input/
Output
Input
GPIO Port G11: After reset, the default
state is GPIOG11.
(TB3)
Input/
Output
Quad timer module B channel 3 input/
output
(CLKO0)
Output
Buffered clock output 0: the clock source is
selected by clockout select (CLKOSEL) bits
in the clock output select register
(CLKOUT) of the SIM.
(MOSI1)
Input/
Output
Master out/slave in for SPI1— In master
mode, MOSI1 pin is the data output. In
slave mode, MOSI1 pin is the data input.
1. If CLKIN is selected as the device’s external clock input, then both the GPS_C0 bit (in GPS1) and the EXT_SEL bit (in the
OCCS oscillator control register (OSCTL)) must be set. Also, the crystal oscillator should be powered down.
3 Signal groups
The input and output signals of the MC56F84xxx are organized into functional groups, as
listed in Table 3. Note that some package sizes may not be available for your specific
product. See MC56F844xx/5xx/7xx product family.
MC56F847XX, Rev. 4.1, 01/2022
34
NXP Semiconductors
Ordering parts
Table 3. Functional Group Pin Allocations
Functional Group
Number of Pins
48 LQFP
64 LQFP
80 LQFP
100 LQFP
Power Inputs (VDD, VDDA), Power Outputs (VCAP)
5
6
7
8
Ground (VSS, VSSA)
4
4
5
6
Reset
1
1
1
1
eFlexPWM with NanoEdge ports, not including fault pins
6
8
8
8
eFlexPWM without NanoEdge ports, not including fault pins
0
1
8
16
Queued Serial Peripheral Interface (QSPI) ports
4
4
8
15
Queued Serial Communications Interface (QSCI) ports
6
9
9
15
Inter-Integrated Circuit
(I2C)
4
6
6
6
12-bit Analog-to-Digital Converter (Cyclic ADC) inputs
interface ports
10
16
16
16
16-bit Analog-to-Digital Converter (SAR ADC) inputs
2
8
10
16
Analog Comparator inputs/outputs
10/4
13/6
13/6
16/6
12-bit Digital-to-Analog output
1
1
1
1
Quad Timer Module (TMR) ports
6
9
11
13
Controller Area Network (FlexCAN)
2
2
2
2
Inter-Module Crossbar inputs/outputs
12/2
16/6
19/17
25/19
Clock inputs/outputs
2/2
2/2
2/3
2/3
JTAG / Enhanced On-Chip Emulation (EOnCE)
4
4
4
4
4 Ordering parts
4.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: MC56F84
5 Part identification
5.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
35
Terminology and guidelines
5.2 Format
Part numbers for this device have the following format: Q 56F8 4 C F P T PP N
5.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• MC = Fully qualified, general market flow
• PC = Prequalification
56F8
DSC family with flash memory and DSP56800/
DSP56800E/DSP56800EX core
• 56F8
4
DSC subfamily
• 4
C
Maximum CPU frequency (MHz)
• 4 = 60 MHz
• 5 = 80 MHz
F
Primary program flash memory size
•
•
•
•
4 = 64 KB
5 = 96 KB
6 = 128 KB
8 = 256 KB
P
Pin count
•
•
•
•
0 and 1 = 48
2 and 3 = 64
4, 5, and 6 = 80
7, 8, and 9 = 100
T
Temperature range (°C)
• V = –40 to 105
PP
Package identifier
• LH = 64LQFP
• LK = 80LQFP
• LL = 100LQFP
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
5.4 Example
This is an example part number: MC56F84789VLL
6 Terminology and guidelines
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NXP Semiconductors
Terminology and guidelines
6.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
6.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
Min.
1.0 V core supply
voltage
0.9
Max.
1.1
Unit
V
6.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values
for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
6.2.1 Example
This is an example of an operating behavior:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
6.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
6.3.1 Example
This is an example of an attribute:
MC56F847XX, Rev. 4.1, 01/2022
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37
Terminology and guidelines
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
6.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
6.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
–0.3
Max.
1.2
Unit
V
6.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
MC56F847XX, Rev. 4.1, 01/2022
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NXP Semiconductors
Terminology and guidelines
6.6 Relationship between ratings and operating requirements
e
Op
ing
rat
r
(
ng
ati
n.
mi
)
ing
rat
e
Op
e
re
ir
qu
)
in.
t (m
n
me
ing
rat
e
Op
e
ir
qu
re
t (m
n
me
ax
.)
ing
rat
e
Op
(m
ng
ati
.)
ax
r
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
ng
dli
n
Ha
n.)
mi
g(
in
rat
ma
g(
ng
dli
n
Ha
in
rat
x.)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
Handling (power off)
∞
6.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
6.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
39
Terminology and guidelines
6.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
IWP
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
6.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
6.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
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Ratings
7 Ratings
7.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
7.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
7.3 ESD handling ratings
Although damage from electrostatic discharge (ESD) is much less common on these
devices than on early CMOS circuits, use normal handling precautions to avoid exposure
to static discharge. Qualification tests are performed to ensure that these devices can
withstand exposure to reasonable levels of static without suffering any permanent
damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification. During the
device qualification ESD stresses were performed for the human body model (HBM), the
machine model (MM), and the charge device model (CDM).
All latch-up testing is in conformity with AEC-Q100 Stress Test Qualification.
A device is defined as a failure if after exposure to ESD pulses, the device no longer
meets the device specification. Complete DC parametric and functional testing is
performed as per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
MC56F847XX, Rev. 4.1, 01/2022
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41
Ratings
Table 4. ESD/Latch-up Protection
Characteristic1
Min
Max
Unit
ESD for Human Body Model (HBM)
–2000
+2000
V
ESD for Machine Model (MM)
–200
+200
V
ESD for Charge Device Model (CDM)
–500
+500
V
Latch-up current at TA= 85°C (ILAT)
–100
+100
mA
1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions
unless otherwise noted.
7.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in Table 5 may affect device
reliability or cause permanent damage to the device.
NOTE
If the voltage difference between VDD and VDDA or VSS and
VSSA is too large, then the device can malfunction or be
permanently damaged. The restrictions are:
• At all times, it is recommended that the voltage
difference of VDD - VSS be within +/-200 mV of the
voltage difference of VDDA - VSSA, including power
ramp up and ramp down; see additional requirements in
Table 6. Failure to do this recommendation may result in a
harmful leakage current through the substrate, between the
VDD/VSS and VDDA/VSSA pad cells. This harmful
leakage current could prevent the device from operating
after power up.
• At all times, to avoid permanent damage to the part, the
voltage difference between VDD and VDDA must
absolutely be limited to 0.3 V; see Table 5.
• At all times, to avoid permanent damage to the part, the
voltage difference between VSS and VSSA must
absolutely be limited to 0.3 V; see Table 5.
Table 5. Absolute Maximum Ratings (VSS = 0 V, VSSA = 0 V)
Characteristic
Symbol
Notes
Min
Max
Unit
Supply Voltage Range
VDD
-0.3
4.0
V
Analog Supply Voltage Range
VDDA
-0.3
4.0
V
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
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NXP Semiconductors
General
Table 5. Absolute Maximum Ratings (VSS = 0 V, VSSA = 0 V) (continued)
Characteristic
Symbol
Min
Max
Unit
VREFHx
-0.3
4.0
V
Voltage difference VDD to VDDA
ΔVDD
-0.3
0.3
V
Voltage difference VSS to VSSA
ΔVSS
-0.3
0.3
V
ADC High Voltage Reference
Notes
Digital Input Voltage Range
VIN
Pin Group 1
-0.3
5.5
V
RESET Input Voltage Range
VIN_RESET
Pin Group 2
-0.3
4.0
V
Oscillator Input Voltage Range
VOSC
Pin Group 4
-0.4
4.0
V
Analog Input Voltage Range
VINA
Pin Group 3
-0.3
4.0
V
Input clamp current, per pin (VIN < VSS - 0.3 V),
VIC
—
-5.0
mA
Output clamp current, per pin
VOC
—
±20.0
mA
Contiguous pin DC injection current—regional limit sum
of 16 contiguous pins
IICont
-25
25
mA
Output Voltage Range (normal push-pull mode)
VOUT
Pin Group 1, 2
-0.3
4.0
V
VOUTOD
Pin Group 1
-0.3
5.5
V
VOUTOD_RE
Pin Group 2
-0.3
4.0
V
Pin Group 5
-0.3
4.0
V
-55
150
°C
Output Voltage Range (open drain mode)
RESET Output Voltage Range
SET
DAC Output Voltage Range
VOUT_DAC
Storage Temperature Range (Extended Industrial)
TSTG
8 General
8.1 General characteristics
The device is fabricated in high-density, low-power CMOS with 5 V–tolerant TTLcompatible digital inputs, except 3.3 V for RESET . The term “5 V–tolerant” refers to the
capability of an I/O pin, built on a 3.3 V–compatible process technology, to withstand a
voltage up to 5.5 V without damaging the device.
5 V–tolerant I/O is desirable because many systems have a mixture of devices designed
for 3.3 V and 5 V power supplies. In such systems, a bus may carry both 3.3 V– and 5 V–
compatible I/O voltage levels . This 5 V–tolerant capability therefore offers the power
savings of 3.3 V I/O levels combined with the ability to receive 5 V levels without
damage.
Absolute maximum ratings in the table of "Voltage and current operating ratings" section
are stress ratings only, and functional operation at the maximum is not guaranteed. Stress
beyond these ratings may affect device reliability or cause permanent damage to the
device.
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
43
General
Unless otherwise stated, all specifications within this chapter apply to the temperature
range specified in the table of "Voltage and current operating ratings" section over the
following supply ranges: VSS = VSSA = 0 V, VDD = VDDA = 3.0 V to 3.6 V, CL ≤ 50 pF,
fOP = 100 MHz.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
normal precautions are advised to avoid application of any
voltages higher than maximum-rated voltages to this highimpedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate voltage level.
8.2 AC electrical characteristics
Tests are conducted using the input levels specified in the section "Voltage and current
operating behaviors". Unless otherwise specified, propagation delays are measured from
the 50% to the 50% point, and rise and fall times are measured between the 10% and 90%
points, as shown in Figure 3.
Low
VIH
Input Signal
High
90%
50%
10%
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH – VIL)/2.
Figure 3. Input signal measurement references
Figure 4 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid
Data2 Valid
Data1
Data3 Valid
Data2
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 4. Signal states
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NXP Semiconductors
General
8.3 Nonswitching electrical specifications
8.3.1 Voltage and current operating requirements
This section includes information about recommended operating conditions.
NOTE
Recommended VDD ramp rate is between 1 ms and 200 ms.
Table 6. Recommended Operating Conditions (VREFLx=0V, VSSA=0V, VSS=0V)
Characteristic
Symbol
Supply voltage
Notes1
Min
Typ
3.3
Max
Unit
VDD, VDDA
2.7
3.6
V
ADC (Cyclic) Reference Voltage High
VREFHA
3.0
VDDA
V
ADC (SAR) Reference Voltage High
VREFHC
2.0
VDDA
V
Voltage difference VDD to VDDA
ΔVDD
-0.1
0
0.1
V
Voltage difference VSS to VSSA
ΔVSS
-0.1
0
0.1
V
5.5
V
VDD
V
0.3 x VDD
V
VREFHB
Input Voltage High (digital inputs)
RESET Input Voltage High
Input Voltage Low (digital inputs)
Oscillator Input Voltage High
VIH
Pin Group 1
0.7 x VDD
VIH_RESET
Pin Group 2
0.7 x VDD
VIL
Pin Groups 1, 2
VIHOSC
Pin Group 4
2.0
VDD + 0.3
V
VILOSC
Pin Group 4
-0.3
0.8
V
IOH
Pin Group 1
—
-2
mA
Pin Group 1
—
-9
Pin Groups 1, 2
—
2
Pin Groups 1, 2
—
9
—
XTAL driven by an external clock source
Oscillator Input Voltage Low
Output Source Current High (at VOH min.)
• Programmed for low drive strength
• Programmed for high drive strength
Output Source Current Low (at VOL max.)2, 3
• Programmed for low drive strength
• Programmed for high drive strength
IOL
mA
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
2. Total IO sink current and total IO source current are limited to 75 mA each
3. Contiguous pin DC injection current of regional limit—including sum of negative injection currents or sum of positive
injection currents of 16 contiguous pins—is 25 mA.
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
45
General
8.3.2 LVD and POR operating requirements
Table 7. PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters
Characteristic
POR Assert
Symbol
Voltage1
Min
Typ
Max
Unit
POR
2.0
V
POR
2.7
V
Low-Voltage Warning Interrupt
LVI_2p7
2.73
V
Low-Voltage Alarm Interrupt
LVI_2p2
2.23
V
POR Release
Voltage2
1. During 3.3-volt VDD power supply ramp down
2. During 3.3-volt VDD power supply ramp up (gated by LVI_2p7)
8.3.3 Voltage and current operating behaviors
The following table provides information about power supply requirements and I/O pin
characteristics.
Table 8. DC Electrical Characteristics at Recommended Operating Conditions
Symbol
Notes 1
Min
Typ
Max
Unit
Test Conditions
Output Voltage High
VOH
Pin Group 1
VDD - 0.5
—
—
V
IOH = IOHmax
Output Voltage Low
VOL
Pin Groups
1, 2
—
—
0.5
V
IOL = IOLmax
IIH
Pin Group 1
—
0
+/- 2.5
µA
VIN = 2.4 V to 5.5 V
Characteristic
Digital Input Current High
Pin Group 2
pull-up enabled or
disabled
Comparator Input Current
High
Oscillator Input Current
High
Digital Input Current Low
2, 3
VIN = 2.4 V to VDD
IIHC
Pin Group 3
—
0
+/- 2
µA
VIN = VDDA
IIHOSC
Pin Group 3
—
0
+/- 2
µA
VIN = VDDA
IIL
Pin Groups
1, 2
—
0
+/- 0.5
µA
VIN = 0V
RPull-Up
20
—
50
kΩ
—
RPull-Down
20
—
50
kΩ
—
pull-up disabled
Internal Pull-Up
Resistance
Internal Pull-Down
Resistance
Comparator Input Current
Low
IILC
Pin Group 3
—
0
+/- 2
µA
VIN = 0V
Oscillator Input Current
Low
IILOSC
Pin Group 3
—
0
+/- 2
µA
VIN = 0V
DAC Output Voltage
Range
VDAC
Pin Group 5
Typically
VSSA +
40mV
—
Typically
VDDA 40mV
V
RLD = 3 kΩ || CLD = 400 pF
IOZ
Pin Groups
1, 2
—
0
+/- 1
µA
—
Output Current 2, 3
High Impedance State
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
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NXP Semiconductors
General
Table 8. DC Electrical Characteristics at Recommended Operating Conditions (continued)
Characteristic
Schmitt Trigger Input
Hysteresis
Symbol
Notes 1
Min
Typ
Max
Unit
Test Conditions
VHYS
Pin Groups
1, 2
0.06 × VDD
—
—
V
—
I (uA)
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC
2. See the following figure "IIN/IOZ vs. VIN (typical; pull-up disabled) (design simulation)" .
3. To minimize the excessive leakage ( > 1 μA) current from digital pin, input signal should NOT stay between 1.1 V and 0.9
× VDD for prolonged time.
V (volt)
Figure 5. IIN/IOZ vs. VIN (typical; pull-up disabled) (design simulation)
8.3.4 Power mode operating behaviors
Parameters listed are guaranteed by design.
NOTE
To filter noise on the RESETB pin, install a capacitor (up to 0.1
uF) on it.
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
47
General
Table 9. Reset, stop, wait, and interrupt timing
Characteristic
Symbol
Typical Min
Typical
Max
Unit
See
Figure
Minimum RESET Assertion Duration
tRA
161
—
ns
—
RESET deassertion to First Address Fetch
tRDA
865 x TOSC + 8 x T
ns
—
tIF
361.3
ns
—
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
570.9
1. If the RESET pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion
must be greater than 21 ns.
NOTE
In the Table 9, T = system clock cycle and TOSC = oscillator
clock cycle. For an operating frequency of 100MHz, T=10ns.
At 4MHz (used coming out of reset and stop modes), T=250ns.
Table 10. Power-On-Reset mode transition times
Symbol
TPOR
Description
Min
Max
Unit
Notes
After a POR event, the amount of delay from when VDD
reaches 2.7V to when the first instruction executes (over the
operating temperature range).
199
225
us
LPS mode to LPRUN mode
240
551
us
4
VLPS mode to VLPRUN mode
1424
1500
us
5
STOP mode to RUN mode
6.79
7.29
us
3
WAIT mode to RUN mode
0.570
0.620
us
2
VLPWAIT mode to VLPRUN mode
1413
1500
us
5
LPWAIT mode to LPRUN mode
237.2
554
us
4
1. Normal boot (FTFL_OPT[LPBOOT]=1)
2. Clock configuration: CPU clock = 100 MHz, bus clock = 100 MHz, flash clock = 25
MHz
3. Clock configuration: CPU clock = 4 MHz, system clock source is 8 MHz IRC
4. CPU Clock = 200 kHz and 8 Mhz IRC in standby mode
5. Clock configuration: Using 64 kHz external clock source, CPU Clock = 32 kHz
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NXP Semiconductors
General
8.3.5 Power consumption operating behaviors
Table 11. Current Consumption
Mode
Maximum
Frequency
Conditions
Typical at 3.3 V,
25°C
IDD
RUN
100 MHz
•
•
•
•
•
IDDA
Maximum at 3.6
V, 105°C
IDD1
IDDA
63.7 mA 16.7 mA 101 mA
32 mA
•
•
•
•
•
100 MHz Device Clock
Regulators are in full regulation
Relaxation Oscillator on
PLL powered on
Continuous MAC instructions with fetches from
Program Flash
All peripheral modules enabled.
TMRs and SCIs using 1X Clock
NanoEdge within PWMA using 1X clock
ADC/DAC powered on and clocked at 5 MHz2
Comparator powered on
WAIT
100 MHz
•
•
•
•
•
•
•
•
•
100 MHz Device Clock
Regulators are in full regulation
Relaxation Oscillator on
PLL powered on
Processor Core in WAIT state
All Peripheral modules enabled.
TMRs and SCIs using 1X Clock
NanoEdge within PWMA using 2X clock
ADC/DAC/Comparator powered off
43.5 mA
13.58
μA
80 mA
47.55
μA
STOP
4 MHz
•
•
•
•
•
•
•
4 MHz Device Clock
Regulators are in full regulation
Relaxation Oscillator on
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC/DAC/Comparator powered off
9.19 mA
13.20
μA
30.14
mA
45.00
μA
LPRUN
(LsRUN)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator
1.86 mA 3.33 mA
(ROSC)
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• Repeat NOP instructions
• All peripheral modules enabled, except NanoEdge
and cyclic ADCs
• Simple loop with running from platform instruction
buffer
16.69
mA
5.37 mA
LPWAIT
(LsWAIT)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator
1.83 mA 2.67 mA
(ROSC)
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• All peripheral modules enabled, except NanoEdge
and cyclic ADCs3
• Processor core in wait mode
16.48
mA
5.37 mA
LPSTOP
(LsSTOP)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator
(ROSC)
• ROSC in standby mode
• Regulators are in standby
15.76
mA
45 μA
1.07 mA
13.13
μA
Table continues on the next page...
MC56F847XX, Rev. 4.1, 01/2022
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49
General
Table 11. Current Consumption (continued)
Mode
Maximum
Frequency
Conditions
Typical at 3.3 V,
25°C
Maximum at 3.6
V, 105°C
IDD
IDDA
IDD1
IDDA
• PLL disabled
• Only PITs and COP enabled; other peripheral
modules disabled and clocks gated off3
• Processor core in stop mode
VLPRUN
200 kHz
•
•
•
•
•
•
•
•
•
32 kHz Device Clock
Clocked by a 32 kHz external clock source
Oscillator in power down
All ROSCs disabled
Large regulator is in standby
Small regulator is disabled
PLL disabled
Repeat NOP instructions
All peripheral modules, except COP and EWM,
disabled and clocks gated off
• Simple loop running from platform instruction
buffer
0.57 mA
13.04
μA
8.64 mA
18.15
μA
VLPWAIT
200 kHz
•
•
•
•
•
•
•
•
32 kHz Device Clock
Clocked by a 32 kHz external clock source
Oscillator in power down
All ROSCs disabled
Large regulator is in standby
Small regulator is disabled
PLL disabled
All peripheral modules, except COP, disabled and
clocks gated off
• Processor core in wait mode
0.56 mA
12.02
μA
8.53 mA
16.50
μA
VLPSTOP
200 kHz
•
•
•
•
•
•
•
•
0.56 mA
10.58
μA
8.50 mA
15.00
μA
32 kHz Device Clock
Clocked by a 32 kHz external clock source
Oscillator in power down
All ROSCs disabled
Large regulator is in standby
Small regulator is disabled
PLL disabled
All peripheral modules, except COP, disabled and
clocks gated off
• Processor core in stop mode
1. No output switching, all ports configured as inputs, all inputs low, no DC loads
2. ADC power consumption at higher frequency can be found in Table 1
3. In all chip LP modes and flash memory VLP modes, the maximum frequency for flash memory operation is 250 kHz,
because of the fixed frequency ratio of 1:4 between the CPU clock and the flash clock (when using a 2 MHz external input
clock and the CPU is operating at 1 MHz).
8.3.6 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
MC56F847XX, Rev. 4.1, 01/2022
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NXP Semiconductors
General
2. Perform a keyword search for “EMC design.”
8.3.7 Capacitance attributes
Table 12. Capacitance attributes
Description
Symbol
Min.
Typ.
Max.
Unit
CIN
—
10
—
pF
COUT
—
10
—
pF
Input capacitance
Output capacitance
8.4 Switching specifications
8.4.1 Device clock specifications
Table 13. Device clock specifications
Symbol
Description
Min.
Max.
Unit
0.001
100
MHz
0
100
—
100
Notes
Normal run mode
fSYSCLK
fIPBUS
Device (system and core) clock frequency
• using relaxation oscillator
• using external clock source
IP bus clock
MHz
8.4.2 General switching timing
Table 14. Switching timing
Symbol
Description
Min
GPIO pin interrupt pulse width1
1.5
Max
Synchronous path
Unit
Notes
IP Bus
Clock
Cycles
2
Port rise and fall time (high drive strength), slew disabled,
2.7V ≤ VDD ≤ 3.6V
5.5
15.1
ns
3
Port rise and fall time (high drive strength), slew enabled,
2.7V ≤ VDD ≤ 3.6V
1.5
6.8
ns
4
Port rise and fall time (low drive strength), slew disabled, 2.7V
≤ VDD ≤ 3.6V
8.2
17.8
ns
3
Port rise and fall time (low drive strength), slew enabled, 2.7V
≤ VDD ≤ 3.6V
3.2
9.2
ns
4
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General
1. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming
GPIOn_IPOLR and GPIOn_IENR.
2. The greater synchronous and asynchronous timing must be met.
3. 75 pF load
4. 15 pF load
8.5 Thermal specifications
8.5.1 Thermal operating requirements
Table 15. Thermal operating requirements
Symbol
Description
Min
Max
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
8.5.2 Thermal attributes
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is userdetermined rather than being controlled by the MCU design. To account for PI/O in power
calculations, determine the difference between actual pin voltage and VSS or VDD and
multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD is very small.
See Thermal design considerations for more detail on thermal design considerations.
Board type
Symbol
Description
64 LQFP
80 LQFP
100 LQFP
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
ambient
(natural
convection)
64
55
62
°C/W
,
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
ambient
(natural
convection)
46
40
49
°C/W
1,
Single-layer
(1s)
RθJMA
Thermal
resistance,
junction to
52
44
52
°C/W
1,2
Table continues on the next page...
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Peripheral operating requirements and behaviors
Board type
Symbol
Description
64 LQFP
80 LQFP
100 LQFP
Unit
Notes
ambient (200
ft./min. air
speed)
Four-layer
(2s2p)
RθJMA
Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
39
34
43
°C/W
—
RθJB
Thermal
resistance,
junction to
board
28
24
35
°C/W
—
RθJC
Thermal
resistance,
junction to
case
15
12
17
°C/W
—
ΨJT
Thermal
3
characterizati
on parameter,
junction to
package top
outside
center
(natural
convection)
3
3
°C/W
1,2
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions
—Forced Convection (Moving Air) with the board horizontal.
9 Peripheral operating requirements and behaviors
9.1 Core modules
9.1.1 JTAG timing
Table 16. JTAG timing
Characteristic
Symbol
Min
Max
Unit
See
Figure
TCK frequency of operation
fOP
DC
SYS_CLK/16
MHz
Figure 6
TCK clock pulse width
tPW
50
—
ns
Figure 6
TMS, TDI data set-up time
tDS
5
—
ns
Figure 7
TMS, TDI data hold time
tDH
5
—
ns
Figure 7
Table continues on the next page...
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System modules
Table 16. JTAG timing (continued)
Characteristic
Symbol
Min
Max
Unit
See
Figure
TCK low to TDO data valid
tDV
—
30
ns
Figure 7
TCK low to TDO tri-state
tTS
—
30
ns
Figure 7
1/fOP
VIH
TCK
(Input)
tPW
tPW
VM
VM
VIL
VM = VIL + (VIH – VIL)/2
Figure 6. Test clock input timing diagram
TCK
(Input)
tDS
TDI
TMS
(Input)
tDH
Input Data Valid
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
Figure 7. Test access port timing diagram
9.2 System modules
9.2.1 Voltage regulator specifications
The voltage regulator supplies approximately 1.2 V to the device's core logic. For proper
operations, the voltage regulator requires a minimum external 2.2 µF capacitor on each
VCAP pin with total capacitors on all VCAP pins at a minimum of 4.4 µF. Ceramic and
tantalum capacitors tend to provide better performance tolerances. The output voltage can
be measured directly on the VCAP pin. The specifications for this regulator are shown in
Table 17.
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Table 17. Regulator 1.2 V parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage 1
VCAP
—
1.22
—
V
Short Circuit Current 2
ISS
—
600
—
mA
Short Circuit Tolerance (VCAP shorted to ground)
TRSC
—
—
30
minute
1. Value is after trim
2. Guaranteed by design
Table 18. Bandgap electrical specifications
Characteristic
Symbol
Min
Typ
Max
Unit
Reference Voltage (after trim)
VREF
—
1.211
—
V
1. Typical value is trimmed at 25℃. There could be ±50 mV variation due to temperature change.
9.3 Clock modules
9.3.1 External clock operation timing
Parameters listed are guaranteed by design.
Table 19. External clock operation timing requirements
Characteristic
Symbol
Min
Typ
Max
Unit
fosc
—
—
50
MHz
tPW
8
trise
—
1.9
2.5
ns
tfall
—
1.9
2.5
ns
Input high voltage overdrive by an external clock
Vih
0.85×VDD
—
—
V
Input low voltage overdrive by an external clock
Vil
—
—
0.3×VDD
V
Frequency of operation (external clock
Clock pulse
width2
External clock input rise
External clock input fall
1.
2.
3.
4.
driver)1
time3
time4
ns
See the "External clock timing" figure for details on using the recommended connection of an external clock driver.
The chip may not function if the high or low pulse width is smaller than 6.25 ns.
External clock input rise time is measured from 10% to 90%.
External clock input fall time is measured from 90% to 10%.
External
Clock
90%
50%
10%
tPW
tPW
tfall
trise
VIH
90%
50%
10%
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 8. External clock timing
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System modules
9.3.2 Phase-Locked Loop timing
Table 20. Phase-Locked Loop timing
Characteristic
PLL input reference
PLL output
frequency1
frequency2
PLL lock
time3
Allowed Duty Cycle of input reference
Symbol
Min
Typ
Max
Unit
fref
8
8
16
MHz
fop
240
—
400
MHz
tplls
35.5
73.2
µs
tdc
40
60
%
50
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8 MHz input.
2. The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must
be set to 400 MHz.
3. This is the time required after the PLL is enabled to ensure reliable operation.
9.3.3 External crystal or resonator requirement
Table 21. Crystal or resonator requirement
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation
fXOSC
4
8
16
MHz
9.3.4 Relaxation oscillator timing
Table 22. Relaxation oscillator electrical specifications
Characteristic
Symbol
Min
Typ
Max
Unit
7.84
8
8.16
MHz
7.76
8
8.24
266.8
402
554.3
RUN Mode
+/- 1.5
+/-2
Due to temperature
• 0°C to 105°C
+/- 1.5
+/-3
32
33.9
8 MHz Output Frequency
RUN Mode
• 0°C to 105°C
• -40°C to 105°C
Standby Mode (IRC trimmed @ 8 MHz)
• -40°C to 105°C
kHz
8 MHz Frequency Variation
%
• -40°C to 105°C
32 kHz Output Frequency
RUN Mode
• -40°C to 105°C
30.1
kHz
Table continues on the next page...
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System modules
Table 22. Relaxation oscillator electrical specifications (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
+/-2.5
+/-4
%
0.12
0.4
µs
14.4
16.2
50
52
32 kHz Output Frequency Variation
RUN Mode
Due to temperature
• -40°C to 105°C
Stabilization Time
• 8 MHz output
• 32 kHz output
tstab
Output Duty Cycle
48
%
Figure 9. Relaxation oscillator temperature variation (typical) after trim (preliminary)
9.4 Memories and memory interfaces
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57
System modules
9.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
9.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
thversblk32k Erase Block high-voltage time for 32 KB
—
52
452
ms
1
thversblk256k Erase Block high-voltage time for 256 KB
—
104
904
ms
1
Unit
Notes
1. Maximum time based on expectations at cycling end-of-life.
9.4.1.2
Symbol
Flash timing specifications — commands
Table 24. Flash command timing specifications
Description
Min.
Typ.
Max.
Read 1s Block execution time
1
trd1blk32k
• 32 KB data flash
—
—
0.5
ms
trd1blk256k
• 256 KB program flash
—
—
1.7
ms
trd1sec1k
Read 1s Section execution time (data flash
sector)
—
—
60
μs
1
trd1sec2k
Read 1s Section execution time (program flash
sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
tpgm4
Program Longword execution time
—
65
145
μs
Erase Flash Block execution time
2
tersblk32k
• 32 KB data flash
—
55
465
ms
tersblk256k
• 256 KB program flash
—
122
985
ms
—
14
114
ms
tersscr
Erase Flash Sector execution time
—
Program Section execution time
—
tpgmsec512p
• 512 B program flash
—
2.4
—
ms
tpgmsec512d
• 512 B data flash
—
4.7
—
ms
tpgmsec1kp
• 1 KB program flash
—
4.7
—
ms
tpgmsec1kd
• 1 KB data flash
—
9.3
—
ms
Table continues on the next page...
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System modules
Table 24. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
1
trdonce
Read Once execution time
—
—
25
μs
1
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
175
1500
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
Program Partition for EEPROM execution time
tpgmpart32k
• 32 KB FlexNVM
—
—
70
—
ms
Set FlexRAM Function execution time:
—
tsetramff
• Control Code 0xFF
—
50
—
μs
tsetram8k
• 8 KB EEPROM backup
—
0.3
0.5
ms
tsetram32k
• 32 KB EEPROM backup
—
0.7
1.0
ms
260
μs
Byte-write to FlexRAM for EEPROM operation
teewr8bers
Byte-write to erased FlexRAM location execution
time
—
175
Byte-write to FlexRAM execution time:
3
—
teewr8b8k
• 8 KB EEPROM backup
—
340
1700
μs
teewr8b16k
• 16 KB EEPROM backup
—
385
1800
μs
teewr8b32k
• 32 KB EEPROM backup
—
475
2000
μs
260
μs
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
Word-write to FlexRAM execution time:
—
—
teewr16b8k
• 8 KB EEPROM backup
—
340
1700
μs
teewr16b16k
• 16 KB EEPROM backup
—
385
1800
μs
teewr16b32k
• 32 KB EEPROM backup
—
475
2000
μs
540
μs
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
Longword-write to FlexRAM execution time:
—
—
teewr32b8k
• 8 KB EEPROM backup
—
545
1950
μs
teewr32b16k
• 16 KB EEPROM backup
—
630
2050
μs
teewr32b32k
• 32 KB EEPROM backup
—
810
2250
μs
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
MC56F847XX, Rev. 4.1, 01/2022
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59
System modules
9.4.1.3
Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
9.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 26. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretd1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycd
Cycling endurance
10 K
50 K
—
cycles
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
50
—
years
—
tnvmretee10 Data retention up to 10% of write endurance
20
100
—
years
—
Write endurance
nnvmwree16
• EEPROM backup to FlexRAM ratio = 16
35 K
175 K
—
writes
nnvmwree128
• EEPROM backup to FlexRAM ratio = 128
315 K
1.6 M
—
writes
nnvmwree512
• EEPROM backup to FlexRAM ratio = 512
1.27 M
6.4 M
—
writes
nnvmwree4k
• EEPROM backup to FlexRAM ratio = 4096
10 M
50 M
—
writes
nnvmwree8k
• EEPROM backup to FlexRAM ratio = 8192
20 M
100 M
—
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
9.5 Analog
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9.5.1 12-bit cyclic Analog-to-Digital Converter (ADC) parameters
Table 27. 12-bit ADC electrical specifications
Characteristic
Symbol
Min
Typ
Max
Unit
VDDA
2.7
3.3
3.6
V
Vrefh Supply Voltage
Vrefhx
3.0
VDDA
V
ADC Conversion Clock
fADCCLK
0.6
20
MHz
RAD
VREFL
VREFH
V
VREFL
VREFH
VSSA
VDDA
Recommended Operating Conditions
Supply Voltage
Conversion Range
Input Voltage Range
VADIN
External Reference
Internal Reference
V
Timing and Power
Conversion Time
tADC
Sample Time
tADS
ADC Power-Up Time (from adc_pdn)
tADPU
ADC RUN Current (per ADC block)
IADRUN
6
1
5
13
ADC Clock Cycles
ADC Clock Cycles
mA
1
• at 600 kHz ADC Clock, LP mode
5.7
• ≤ 8.33 MHz ADC Clock, 00 mode
10.5
• ≤ 12.5 MHz ADC Clock, 01 mode
17.7
• ≤ 16.67 MHz ADC Clock, 10 mode
22.6
• ≤ 20 MHz ADC Clock, 11 mode
ADC Powerdown Current (adc_pdn enabled)
VREFH Current
ADC Clock Cycles
IADPWRDWN
0.02
µA
IVREFH
0.001
µA
INL
+/- 3
+/- 5
LSB
DNL
+/- 0.6
+/- 0.9
LSB2
Accuracy (DC or Absolute)
Integral non-Linearity
Differential
non-Linearity1
Monotonicity
Offset
VOFFSET
+/- 17
• 1x gain mode
• 2x gain mode
• 4x gain mode
Gain Error (normalized)
LSB 1
+/- 20
+/- 25
EGAIN
0.994 to
1.004
0.990 to
1.010
Signal to Noise Ratio
SNR
59
dB
Total Harmonic Distortion
THD
64
dB
Spurious Free Dynamic Range
SFDR
65
dB
Signal to Noise plus Distortion
SINAD
59
dB
Effective Number of Bits
ENOB
9.5
bits
IIN
0
AC Specifications
ADC Inputs
Input Leakage Current
+/-2
µA
Table continues on the next page...
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System modules
Table 27. 12-bit ADC electrical specifications (continued)
Characteristic
Symbol
Input Injection Current
IINJ
Input Capacitance
CADI
Min
Typ
Max
Unit
+/-3
mA
-
Sampling Capacitor
-
• 1x mode
1.4
• 2x mode
2.8
• 4x mode
5.6
pF
1. INL measured from VIN = VREFL to VIN = VREFH.
2. LSB = Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 Gain Setting
9.5.1.1
Equivalent circuit for ADC inputs
The following figure shows the ADC input circuit during sample and hold. S1 and S2 are
always opened/closed at non-overlapping phases, and
both S1 and S2 operate at the ADC
clock frequency. The following equation gives equivalent input impedance when the
input is selected.
1
-12
(ADC ClockRate) x
1.4x10
+ 100ohm + 125ohm
C1: Single Ended Mode
2XC1: Differential Mode
Analog Input
1
125 ESD
Resistor
2
Channel Mux
equivalent resistance
100Ohms
S1
C1
S1
S/H
S1
3
C1
S2
S2
S1
(VREFHx - VREFLx ) / 2
C1: Single Ended Mode
2XC1: Differential Mode
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling =
1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal
routing = 2.04pF
3. 8 pF noise damping capacitor
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 (4.8pF) is normally
disconnected from the input, and is only connected to the input at sampling time.
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5. S1 and S2 switch phases are non-overlapping and operate at the ADC clock
frequency
S1
S2
Figure 10. Equivalent circuit for A/D loading
9.5.2 16-bit SAR ADC electrical specifications
9.5.2.1
16-bit ADC operating conditions
Table 28. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
2.7
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
–100
0
+100
mV
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
–100
0
+100
mV
2
VREFH
ADC reference
voltage high
Absolute
VDDA
VDDA
VDDA
V
3
VREFL
ADC reference
voltage low
Absolute
VSSA
VSSA
VSSA
V
4
VADIN
Input voltage
VSSA
—
VDDA
V
CADIN
Input capacitance
• 16-bit mode
—
8
10
pF
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
RADIN
RAS
Input series
resistance
kΩ
Analog source
resistance
(external)
12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 12-bit mode
1.0
—
18.0
MHz
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
Crate
ADC conversion
rate
≤ 12-bit modes
20.000
—
818.330
kS/s
No ADC hardware averaging
Notes
5
6
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
7
No ADC hardware averaging
37.037
—
461.467
kS/s
Continuous conversions
enabled, subsequent
conversion time
MC56F847XX, Rev. 4.1, 01/2022
NXP Semiconductors
63
System modules
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. VREFH is internally tied to VDDA.
4. VREFL is internally tied to VSSA.
5. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
6. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
7. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
RAS
RADIN
ADC SAR
ENGINE
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 11. ADC input impedance equivalency diagram
9.5.2.2
16-bit ADC electrical characteristics
Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
fADACK
ADC
asynchronous
clock source
Sample Time
TUE
Total unadjusted
error
Conditions1
Min.
Typ.
Max.
Unit
Notes
—
1.7
mA
2
• ADLPC=1, ADHSC=0
1.2
2.4
3.9
MHz
• ADLPC=1, ADHSC=1
3.0
4.0
7.3
MHz
tADACK =
1/fADACK
• ADLPC=0, ADHSC=0
2.4
5.2
6.1
MHz
• ADLPC=0, ADHSC=1
4.4
6.2
9.5
MHz
LSB
See Reference Manual chapter for sample times
• 12-bit modes
—
±4
±6.8
•
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