Freescale Semiconductor
Data Sheet: Technical Data
MC9S08MP16 Series Data
Sheet
Features
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 51.34 MHz CPU at 2.7V to 5.5V across temperature
range of –40°C to 105°C
– Up to 40 MHz CPU at 2.7V to 5.5V across temperature range
of –40°C to 125°C
– HC08 instruction set with added BGND instruction and
additional addressing modes for LDHX and STHX
– Support for up to 48 interrupt/reset sources
• On-Chip Memory
– Up to 16 KB flash memory; read/program/erase over full
operating voltage and temperature
– Up to 1 KB random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and
flash memory contents
• Power-Saving Modes
– Two low power stop modes; reduced power wait mode
– Peripheral clock gating can disable clocks to unused modules
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal
or ceramic resonator range of 31.25–38.4 kHz or 1–16 MHz
– Internal Clock Source (ICS) — Containing a
frequency-locked-loop (FLL) controlled by internal or
external reference; precision trimming of internal reference
allows 0.2% resolutions and 2% deviation over temperature
and voltage; supports CPU frequencies up to 51.34 MHz
• System Protection
– Watchdog computer operating properly (COP) reset running
from dedicated 1-kHz internal clock source or bus clock
– Low-voltage detection with reset or interrupt; selectable trip
points
– Illegal opcode and illegal address detection with reset
– Flash memory block protection
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus three more breakpoints in on-chip
debug module)
– On-chip in-circuit emulator (ICE) debug module containing
three comparators and nine trigger modes. Eight deep FIFO for
storing change-of-flow addresses and event-only data. Debug
module supports both tag and force breakpoints
• Peripherals
– IPC — Interrupt Priority Controller with 4 programmable
interrupt priority levels
– ADC — 13-channel, 12-bit resolution; 2.5 s conversion time;
automatic compare function; 1.7 mV/C temperature sensor;
internal bandgap reference channel; operation in stop3
Document Number: MC9S08MP16
Rev. 2, 08/2011
48-LQFP
Case 932-03
28-SOIC
Case 751F-05
– PGA — Differential programmable gain amplifier with
programmable gain (x1, x2, x4, x8, x16, or x32)
– HSCMP — Three fast analog comparators with positive and
negative inputs; separately selectable interrupt on rising and
falling comparator output; filtering; windowing; HSCMP1 and
HSCMP2 outputs can be optionally routed to FTM1 module;
runs in stop3
– DAC — Three 5-bit digital to analog convertor used as a
32-tap voltage reference for each comparator
– PDB — Two programmable delay blocks: PDB1 synchronizes
PWM with samples of ADC; PDB2 synchronizes PWM with
comparing window of analog comparators
– SCI — Full duplex non-return to zero (NRZ); LIN master
extended break generation; LIN slave extended break
detection; wake up on active edge
– SPI — Full-duplex or single-wire bidirectional;
Double-buffered transmit and receive; Master or Slave mode;
MSB-first or LSB-first shifting
– IIC/SMBus — Up to 400 kbps; Multi-master operation;
Programmable slave address; Interrupt driven byte-by-byte
data transfer; supports broadcast mode and 10-bit addressing;
SMBus compatible
– FTM — Two Flextimers with total of 8 channels; One
2-channel (FTM1) and one 6-channel (FTM2); supports
operation up to 2x bus clock; selectable input capture, output
compare, edge- or center-aligned PWM; dead time insertion;
fault inputs
– MTIM — 8-bit modulo counter with 8-bit prescaler
– RTC — (Real-time counter) 8-bit modulus counter with
binary or decimal based prescaler; External clock source for
precise time base, time-of-day, calendar or task scheduling;
Free running on-chip low power oscillator (1 kHz) for cyclic
wake-up without external components, runs in all MCU modes
– CRC — Cyclic redundancy check generator
– KBI — Three 8 channel keyboard interrupt module with
software selectable polarity on edge or edge/level modes
• Input/Output
– 40 GPIOs, 2 output-only pins.
– Hysteresis and configurable pull up device on input pins;
Configurable slew rate and drive strength on output pins;
Sink/Source current up to 20mA
• Package Options
– 48-LQFP, 32-LQFP, 28-SOIC
– 48-LQFP qualified for automotive usage
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009-2011. All rights reserved.
32-LQFP
Case 873A-03
Table of Contents
1
2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .9
2.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .9
2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .10
2.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .11
2.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15
2.8 External Oscillator (XOSC) Characteristics . . . . . . . . .20
2.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .21
2.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.11 Digital to Analog (DAC) Characteristics . . . . . . . . . . . .26
2.12 High Speed Comparator (HSCMP) Characteristics . . .26
3
4
5
6
2.13 Programmable Gain Amplifier (PGA) Characteristics .
2.14 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
2.14.2 FTM Module Timing . . . . . . . . . . . . . . . . . . . . .
2.14.3 MTIM Module Timing . . . . . . . . . . . . . . . . . . . .
2.14.4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15 Flash Memory Specifications. . . . . . . . . . . . . . . . . . . .
2.16 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.16.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Device Numbering Scheme. . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
27
27
28
29
30
33
33
33
34
35
35
35
35
MC9S08MP16 Series Data Sheet, Rev. 2
2
Freescale Semiconductor
ON-CHIP ICE
DEBUG MODULE (DBG)
Interrupt Priority Controller
(IPC)
BKGD/MS
KBI1P[7:0]
8-BIT KEYBOARD
INTERRUPT (KBI2)
KBI2P[7:0]
8-BIT KEYBOARD
INTERRUPT (KBI3)
KBI3P[7:0]
COP
RESET
IIC MODULE (IIC)
LVD
(Only on MC9S08MP16)
USER FLASH
2-CHANNEL FLEXTIMER
(FTM1)
USER RAM
(FTM2)
(MC9S08MP16 = 1024 BYTES)
(MC9S08MP12 = 512 BYTES)
8-BIT MODULO TIMER
(MTIM)
50.33 MHz INTERNAL CLOCK
SOURCE (ICS)
REAL TIME
COUNTER (RTC)
VREFH
VREFL
VDDA/VREFH
VSSA/VREFL
VDD1
VSS1
VDD2
VSS2
VOLTAGE
REGULATOR
TCLK
FTM1FAULT
PTC7/KBI2P7/TCLK
PTC6/KBI2P6/FTM2FAULT
PTC5/KBI2P5/FTM2CH5
PTC4/KBI2P4/FTM2CH4
PTC3/KBI2P3/FTM2CH3
PTC2/KBI2P2/FTM2CH2
PTC1/KBI2P1/FTM2CH1
PTC0/KBI2P0/FTM2CH0
SERIAL COMMUNICATIONS
INTERFACE (SCI)
XTAL
EXTAL
SERIAL PERIPHERAL
INTERFACE (SPI)
PTD7/KBI3P7/CMP3OUT
PTD6/KBI3P6/CMP2OUT
PTD5/KBI3P5/CMP1OUT
PTD4/KBI3P4/PDB2OUT
PTD3/KBI3P3/FTM1FAULT
PTD2/KBI3P2/PDB1OUT
PTD1/KBI3P1/SCL
PTD0/KBI3P0/SDA
PTE6/EXTAL
PTE5/XTAL
PTE4/ADP12/C1IN4
PTE3/ADP11/C1IN3
PTE2/ADP10
PTE1/ADP9
PTE0/ADP8
PTF2
PTF1/RESET
PTF0/BKGD/MS
TCLK
FTM2FAULT
TCLK
TxD
RxD
SS
SPSCK
MISO
MOSI
PROGRAMMABLE DELAY
BLOCK (PDB1)
PDB1OUT
PROGRAMMABLE DELAY
BLOCK (PDB2)
PDB2OUT
12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
PROGRAMMABLE
GAIN AMPLIFIER (PGA)
(Only on MC9S08MP16)
ADP12–ADP0
PGA+
PGA–
CIN1
C1IN2
C1IN3
C1IN4
CMP1OUT
DIGITAL-TO-ANALOG
CONVERTER (DAC1)
HIGH SPEED ANALOG
COMPARATOR (HSCMP1)
DIGITAL-TO-ANALOG
CONVERTER (DAC2)
HIGH SPEED ANALOG
COMPARATOR (HSCMP2)
C2IN2
C2IN3
C2IN4
CMP2OUT
HIGH SPEED ANALOG
COMPARATOR (HSCMP3)
C3IN2
C3IN3
C3IN4
CMP3OUT
DIGITAL-TO-ANALOG
CONVERTER (DAC3)
PTB7/KBI1P7/ADP7/C3IN4
PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3
PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4
PTB4/KBI1P4/ADP4/C2IN3
PTB3/KBI1P3/ADP3/C3IN2/PGAPTB2/KBI1P2/ADP2/C1IN2/PGA+
PTB1/KBI1P1/ADP1/C2IN2
PTB0/KBI1P0/ADP0/CIN1
SCL
FTM2CH[5:0]
6-CHANNEL FLEXTIMER
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
PTA7/SPSCK
PTA6/MOSI
PTA5/SCL/MISO
PTA4/TCLK/SDA/SS
PTA3/SCL/FTM1CH1
PTA2/SDA/FTM1CH0
PTA1/SCL/RxD
PTA0/SDA/TxD
SDA
FTM1CH[1:0]
(MC9S08MP16 = 16384 BYTES)
(MC9S08MP12 = 12288 BYTES)
PORT A
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
8-BIT KEYBOARD
INTERRUPT (KBI1)
PORT B
BKP
PORT C
BKGD
PORT D
INT
PORT E
CPU
PORT F
CYCLIC REDUNDANCY
CHECK (CRC)
HCS08 CORE
pins not available on 28-pin packages
pins not available on 32-pin or 28-pin packages
Notes: When PTF1 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pull-up device.
When PTF0 is configured as BKGD, pin becomes bi-directional.
VDD2 pad is tied internally on 32-pin and 28-pin packages,
VSS2 pad is tied internally on 28-pin packages
Figure 1. MC9S08MP16 Series Block Diagram
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
3
Pin Assignments
1
Pin Assignments
PTC3/KBI2P3/FTM2CH3
PTC2/KBI2P2/FTM2CH2
PTC1/KBI2P1/FTM2CH1
PTC0/KBI2P0/FTM2CH0
PTF0/BKGD/MS
VDD2
VSS2
PTE6/EXTAL
PTE5/XTAL
PTB7/KBI1P7/ADP7/C3IN4
PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3
PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4
48
47
46
45
44
43
42
41
40
39
38
37
This section shows the pin assignments for the MC9S08MP16 Series devices.
PTB2/KBI1P2/ADP2/C1IN2/PGA+
PTD3/KBI3P3/FTM1FAULT
8
29
PTB1/KBI1P1/ADP1/C2IN2
VSS1
9
28
PTB0/KBI1P0/ADP0/CIN1
VDD1
10
27
PTE2/ADP10
PTA0/SDA/TxD
11
26
PTE1/ADP9
PTA1/SCL/RxD
12
25
PTE0/ADP8
24
30
PTA7/SPSCK
7
23
PTD2/KBI3P2/PDB1OUT
PTA6/MOSI
PTB3/KBI1P3/ADP3/C3IN2/PGA–
22
31
PTA5/SCL/MISO
6
PTA4/TCLK/SDA/SS
PTD1/KBI3P1/SCL
21
VDDA/VREFH
PTF2
32
20
5
PTF1/RESET
PTD0/KBI3P0/SDA
19
VSSA/VREFL
PTD7/KBI3P7/CMP3OUT
33
18
4
PTD6/KBI3P6/CMP2OUT
PTE3/ADP11/C1IN3
PTC7/KBI2P7/TCLK
17
34
PTD5/KBI3P5/CMP1OUT
3
16
PTE4/ADP12/C1IN4
PTC6/KBI2P6/FTM2FAULT
PTD4/KBI3P4/PDB2OUT
35
15
2
PTA3/SCL/FTM1CH1
PTB4/KBI1P4/ADP4/C2IN3
PTC5/KBI2P5/FTM2CH5
14
36
13
1
PTA2/SDA/FTM1CH0
PTC4/KBI2P4/FTM2CH4
Note: Pins in bold are lost in the next
lower pin count package.
Figure 2. MC9S08MP16 Series in 48-LQFP
MC9S08MP16 Series Data Sheet, Rev. 2
4
Freescale Semiconductor
PTC1/KBI2P1/FTM2CH1
PTC0/KBI2P0/FTM2CH0
PTF0/BKGD/MS
VSS2
PTE6/EXTAL
PTE5/XTAL
PTB7/KBI1P7/ADP7/C3IN4
PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3
Pin Assignments
32
31
30
29
28
27
26
25
PTB4/KBI1P4/ADP4/C2IN3
PTC4/KBI2P4/FTM2CH4
3
22
VSSA/VREFL
PTC5/KBI2P5/FTM2CH5
4
21
VDDA/VREFH
PTC6/KBI2P6/FTM2FAULT
5
20
PTB3/KBI1P3/ADP3/C3IN2/PGA–
VSS1
6
19
PTB2/KBI1P2/ADP2/C1IN2/PGA+
VDD1
7
18
PTB1/KBI1P1/ADP1/C2IN2
PTA0/SDA/TxD
8
17
PTB0/KBI1P0/ADP0/CIN1
10
11
12
13
PTA4/TCL:K/SDA/SS
9
14
15
16
PTA7/SPSCK
23
PTA6/MOSI
2
PTA5/SCL/MISO
PTC3/KBI2P3/FTM2CH3
PTF1/RESET
PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4
PTA3/SCL/FTM1CH1
24
PTA2/SDA/FTM1CH0
1
PTA1/SCL/RxD
PTC2/KBI2P2/FTM2CH2
Note: Pins in bold are lost in the next
lower pin count package.
Figure 3. MC9S08MP16 Series in 32-Pin LQFP Package
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
5
Pin Assignments
PTC0/KBI2P0/FTM2CH0
1
28
PTF0/BKGD/MS
PTC1/KBI2P1/FTM2CH1
2
27
PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3
PTC2/KBI2P2/FTM2CH2
3
26
PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4
PTC3/KBI2P3/FTM2CH3
4
25
PTB4/KBI1P4/ADP4/C2IN3
PTC4/KBI2P4/FTM2CH4
5
24
VSSA/VREFL
PTC5/KBI2P5/FTM2CH5
6
23
VDDA/VREFH
PTC6/KBI2P6/FTM2FAULT
7
22
PTB3/KBI1P3/ADP3/C3IN2/PGA–
VSS1
8
21
PTB2/KBI1P2/ADP2/C1IN2/PGA+
VDD1
9
20
PTB1/KBI1P1/ADP1/C2IN2
PTA0/SDA/TxD
10
19
PTB0/KBI1P0/ADP0/CIN1
PTA1/SCL/RxD
11
18
PTA7/SPSCK
PTA2/SDA/FTM1CH0
12
17
PTA6/MOSI
PTA3/SCL/FTM1CH1
13
16
PTA5/SCL/MISO
PTF1/RESET
14
15
PTA4/TCLK/SDA/SS
Figure 4. MC9S08MP16 Series in 28-Pin SOIC Package
MC9S08MP16 Series Data Sheet, Rev. 2
6
Freescale Semiconductor
Pin Assignments
Table 1. Pin Availability by Package Pin-Count
Pin Number
Highest
48
32
LQFP
28
1
3
5
PTC4
KBI2P4
FTM2CH4
2
4
6
PTC5
KBI2P5
FTM2CH5
3
5
7
PTC6
KBI2P6
FTM2FAULT
4
—
—
PTC7
KBI2P7
TCLK1
5
—
—
PTD0
KBI3P0
SDA5
6
—
—
PTD1
KBI3P1
SCL5
7
—
—
PTD2
KBI3P2
PDB1OUT
8
—
—
PTD3
KBI3P3
FTM1FAULT
9
6
8
VSS1
10
7
9
VDD1
11
8
10
PTA0
SDA5
TxD
12
9
11
PTA1
SCL5
RxD
13
10
12
PTA2
SDA5
FTM1CH0
14
11
13
PTA3
SCL5
FTM1CH1
15
—
—
PTD4
KBI3P4
PDB2OUT
16
—
—
PTD5
KBI3P5
CMP1OUT
17
—
—
PTD6
KBI3P6
CMP2OUT2
18
—
—
PTD7
KBI3P7
CMP3OUT3
19
12
14
PTF1
20
—
—
PTF2
21
13
15
PTA4
Port Pin
Alt3
Alt4
RESET4
TCLK1
SDA5
SS
SCL5
MISO
22
14
16
PTA5
23
15
17
PTA6
MOSI
24
16
18
PTA7
SPSCK
25
—
—
PTE0
ADP8
26
—
—
PTE1
ADP9
27
—
—
PTE2
ADP10
28
17
19
PTB0
KBI1P0
ADP06
CIN16
29
18
20
PTB1
KBI1P1
ADP16
C2IN26
30
19
21
PTB2
KBI1P2
ADP26
C1IN26
PGA+6
31
20
22
PTB3
KBI1P3
ADP36
C3IN26
PGA–6
32
21
23
33
22
24
34
—
—
VDDA/VREFH
VSSA/VREFL
PTE3
ADP116
C1IN36
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
7
Electrical Characteristics
Table 1. Pin Availability by Package Pin-Count (continued)
Pin Number
1
2
3
4
5
6
Highest
48
32
LQFP
28
35
—
—
PTE4
36
23
25
PTB4
KBI1P4
37
24
26
PTB5
KBI1P5
38
25
27
PTB6
KBI1P6
39
26
—
PTB7
KBI1P7
40
27
—
PTE5
XTAL
41
28
—
PTE6
EXTAL
42
29
—
VSS2
43
—
—
VDD2
44
30
28
PTF0
BKGD
MS
45
31
1
PTC0
KBI2P0
FTM2CH0
46
32
2
PTC1
KBI2P1
FTM2CH1
47
1
3
PTC2
KBI2P2
FTM2CH2
48
2
4
PTC3
KBI2P3
FTM2CH3
Port Pin
ADP126
Alt3
Alt4
C1IN46
ADP46
C2IN36
CMP2OUT2
ADP56
C2IN46
CMP3OUT3
ADP66
C3IN36
ADP76
C3IN46
TCLK pin can be repositioned using TCLKPS in SOPT2. Default reset location is PTC7.
HSCMP2 output CMP2OUT can be repositioned using the CMP2OPS in the SOPT2 register.
Default reset location is PTD6.
HSCMP3 output CMP3OUT can be repositioned using the CMP3OPS in the SOPT2 register.
Default reset location is PTD7.
Pin is open drain with an internal pullup that is always enabled. Pin does not contain a clamp
diode to VDD and should not be driven above VDD. The voltage measured on the internally
pulled up RESET will not be pulled to VDD. The internal gates connected to this pin are pulled
to VDD.
IIC pins SDA and SCL can be repositioned using IICPS in SOPT2. Default reset locations are
PTD0 and PTD1.
If ADC, HSCMP, or PGA is enabling a shared analog input pin, each has access to the pin.
2
Electrical Characteristics
2.1
Introduction
This section contains electrical and timing specifications for the MC9S08MP16 Series of microcontrollers available at the time
of publication.
MC9S08MP16 Series Data Sheet, Rev. 2
8
Freescale Semiconductor
Electrical Characteristics
2.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P
Those parameters that are guaranteed during production testing on each individual device.
C
Those parameters that are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters that are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column are within
this category.
D
Those parameters that are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
2.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +5.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
25
mA
Tstg
–55 to 150
C
Storage temperature range
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2 All functional non-supply pins, except for PTF1/RESET are internally clamped to V
SS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
9
Electrical Characteristics
2.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine
the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 4. Thermal Characteristics
Num
C
Rating
Symbol
Consumer &
Industrial
Automotive
Unit
1
—
Operating temperature range (packaged)
TA
–40 to 105
–40 to 125
C
2
D
Maximum junction temperature
TJ
115
135
C
80
80
85
—
71
—
56
56
57
—
48
—
3
D
Thermal resistance
single-layer board
1,2
48-pin LQFP
JA
32-pin LQFP
28-pin SOIC
4
D
Thermal resistance
four-layer board
C/W
1,2
48-pin LQFP
JA
32-pin LQFP
28-pin SOIC
C/W
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2 Junction-to-ambient natural convection
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD JA)
Eqn. 1
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K (TJ + 273C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD (TA + 273C) + JA (PD)2
Eqn. 3
MC9S08MP16 Series Data Sheet, Rev. 2
10
Freescale Semiconductor
Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
2.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
Table 5. ESD and Latch-up Test Conditions
Model
Description
Human
Body
Latch-up
Symbol
Value
Unit
Series resistance
R1
1500
Storage capacitance
C
100
pF
Number of pulses per pin
—
3
Minimum input voltage limit
– 2.5
V
Maximum input voltage limit
7.5
V
Table 6. ESD and Latch-Up Protection Characteristics
Rating1
No.
1
2.6
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
2000
—
V
2
Charge device model (CDM)
VCDM
500
—
V
3
Latch-up current at TA = 125C
ILAT
100
—
mA
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 7. DC Characteristics
Num C
1
2
3
Characteristic
Symbol
— Operating Voltage
Min
Typ1
Max
Unit
VDD
2.7
—
5.5
V
(2)
VDDA
—
0
100
mV
VSSA)(2)
VSSA
—
0
100
mV
— Analog Supply voltage delta to VDD (VDD – VDDA)
— Analog Ground voltage delta to VSS (VSS –
Condition
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
11
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C
Characteristic
Symbol
Min
Typ1
Max
C
All I/O pins (except PTF1/RESET)
5 V, ILoad = –4 mA
VDD – 1.5
—
—
P
low-drive strength
5 V, ILoad = –2 mA
VDD – 0.8
—
—
3 V, ILoad = –1 mA
VDD – 0.8
—
—
5 V, ILoad = –20 mA VDD – 1.5
—
—
5 V, ILoad = –10 mA VDD – 0.8
—
—
3 V, ILoad = –5 mA
VDD – 0.8
—
—
VOUT < VDD
0
—
–100
C Output high
VOH
4
C voltage
P
high-drive strength
C
5
Condition
Max total IOH for all ports
D Output high current
IOHT
C
All I/O pins
5 V, ILoad = 4 mA
—
—
1.5
P
(except PTF1/RESET)
5 V, ILoad = 2 mA
—
—
0.8
C
low-drive strength
3 V, ILoad = 1 mA
—
—
0.8
C
All I/O pins
5 V, ILoad = 20 mA
—
—
1.5
(Except PTF1/RESET)
5 V, ILoad = 10 mA
—
—
0.8
3 V, ILoad = 5 mA
—
—
0.8
5 V, ILoad = 3.2 mA
—
—
1.5
6
P Output low
C voltage
VOL
high-drive strength
PTF1/RESET
Unit
V
mA
V
7
C
8
P
5 V, ILoad = 1.6 mA
—
—
0.8
9
C
3 V, ILoad = 0.8 mA
—
—
0.8
10
D Output low current
IOLT
VOUT > VSS
0
—
100
mA
VIH
5V
0.65 x VDD
—
—
V
3V
0.7 x VDD
—
—
5V
—
—
0.35 x VDD
3V
—
—
0.35 x VDD
Max total IOL for all ports
P Input high voltage; all digital inputs
11
C
P Input low voltage; all digital inputs
VIL
12
C
13
C Input hysteresis
14
P Input leakage current (per pin)
P
Vhys
V
0.06 x VDD
V
IIn
VIn = VDD or VSS
—
—
1
A
IOZ
VIn = VDD or VSS
—
—
1
A
VIn = VDD or VSS
—
—
2
A
17
37
52
k
17
37
52
k
VIN > VDD
0
—
2
mA
VIN < VSS
0
—
–0.2
mA
VIN > VDD
0
—
25
mA
VIN < VSS
0
—
–5
mA
Hi-Z (off-state) leakage current (per pin)
input/output port pins
15
PTF1/RESET,
PTE5/XTAL pins
Pullup or Pulldown3 resistors; when enabled
P
16
I/O pins RPU,RPD
PTF1/RESET4
C
D DC injection current
RPU
5, 6, 7, 8
Single pin limit
17
IIC
Total MCU limit, includes
sum of all stressed pins
MC9S08MP16 Series Data Sheet, Rev. 2
12
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C
Characteristic
13
C Input Capacitance, all pins
14
C RAM retention voltage
voltage9
15
C POR re-arm
16
D POR re-arm time
17
18
19
20
21
22
P Low-voltage detection threshold —
high range
3
4
5
6
Max
Unit
CIn
—
—
8
pF
VRAM
—
0.6
1.0
V
VPOR
0.9
1.4
2.0
V
tPOR
10
—
—
s
3.9
4.0
4.0
4.1
4.1
4.2
V
2.48
2.54
2.56
2.62
2.64
2.70
V
4.5
4.6
4.6
4.7
4.7
4.8
V
4.2
4.3
4.3
4.4
4.4
4.5
V
2.84
2.90
2.92
2.98
3.00
3.06
V
2.66
2.72
2.74
2.80
2.82
2.88
V
5V
—
100
—
3V
—
60
—
1.18
1.202
1.21
1.17
—
1.22
VLVD1
P Low-voltage detection threshold —
low range
VLVD0
VDD falling
VDD rising
P Low-voltage warning threshold —
high range 1
VLVW3
VDD falling
VDD rising
P Low-voltage warning threshold —
high range 0
VLVW2
VDD falling
VDD rising
P Low-voltage warning threshold
low range 1
VLVW1
VDD falling
VDD rising
P Low-voltage warning threshold —
low range 0
VLVW0
VDD falling
VDD rising
T Low-voltage inhibit reset/recover hysteresis
2
Typ1
Condition
VDD falling
VDD rising
23
1
Min
Symbol
24
P Bandgap voltage reference at 25C10
25
P
Bandgap voltage reference across temperature
range10
Vhys
mV
VBG
V
V
Typical values are measured at 25C. Characterized, not tested
DC potential difference.
When keyboard interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors.
The specified resistor value is the actual value internal to the device. The pullup value may measure higher when measured externally
on the pin.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If
positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply
going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk
when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce
overall power consumption).
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance
values for positive and negative clamp voltages, then use the larger of the two values.
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
13
Electrical Characteristics
7
All functional non-supply pins except PTF1/RESET are internally clamped to VSS and VDD.
The PTF1/RESET pin does not have a clamp diode to VDD. Do not drive this pin above VDD.
9
Maximum is highest voltage that POR is guaranteed.
10
Factory trimmed at VDD = 5.0 V
8
1.0
2
125°C
25°C
–40°C
0.8
VOL (V)
VOL (V)
1.5
1
0.5
0
125°C
25°C
–40°C
Max 1.5V@20mA
Max 0.8V@5mA
0.6
0.4
0.2
0
5
10
15
IOL (mA)
a) VDD = 5V, High Drive
20
0
25
0
2
4
6
IOL (mA)
b) VDD = 3V, High Drive
8
10
Figure 5. Typical VOL vs IOL, High Drive Strength (except PTF1/RESET)
2
1.0
125°C
25°C
–40°C
0.8
VOL (V)
VOL (V)
1.5
1
0.5
0
125°C
25°C
–40°C
Max 1.5V@4mA
Max 0.8V@1mA
0.6
0.4
0.2
0
1
2
3
IOL (mA)
a) VDD = 5V, Low Drive
4
5
0
0
0.4
0.8
1.2
IOL (mA)
b) VDD = 3V, Low Drive
1.6
2.0
Figure 6. Typical VOL vs IOL, Low Drive Strength (except PTF1/RESET)
MC9S08MP16 Series Data Sheet, Rev. 2
14
Freescale Semiconductor
Electrical Characteristics
2
1.0
125°C
25°C
–40°C
0.8
VDD – VOH (V)
VDD – VOH (V)
1.5
1
0.5
0
125°C
25°C
–40°C
Max 1.5V@ –20mA
Max 0.8V@ –5mA
0.6
0.4
0.2
0
–5
–10
–15
–20
IOH (mA)
a) VDD = 5V, High Drive
0
–25
0
–2
–4
–6
–8
IOH (mA)
b) VDD = 3V, High Drive
–10
Figure 7. Typical VDD – VOH vs IOH, High Drive Strength
1.0
2
125°C
25°C
–40°C
0.8
VDD – VOH (V)
VDD – VOH (V)
1.5
1
0.5
0
125°C
25°C
–40°C
Max 1.5V@ –4mA
Max 0.8V@ –1mA
0.6
0.4
0.2
0
–1
–2
–3
IOH (mA)
a) VDD = 5V, Low Drive
–4
–5
0
0
–0.4
–0.8
–1.2
–1.6
IOH (mA)
b) VDD = 3V, Low Drive
–2.0
Figure 8. Typical VDD – VOH vs IOH, Low Drive Strength
2.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 8. Supply Current Characteristics
Num
C
C
1
C
P
2
C
Parameter
Symbol
3
Run supply current measured at
(CPU clock = 4 MHz, fBus = 2 MHz)
RIDD
Run supply current3 measured at
(CPU clock = 16 MHz, fBus = 8 MHz)
RIDD
VDD
(V)
Typ1
Max2
5
2.16
3
3
1.8
2.5
5
5.26
7.5
3
4.92
7
Unit
mA
mA
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
15
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Num
C
C
3
C
P
4
C
P
5
—
6
C
Parameter
Symbol
4
Run supply current measured at
(CPU clock = 32 MHz, fBus = 16 MHz)
RIDD
5
Run supply current measured at
(CPU clock = 51.34 MHz, fBus = 25.67 MHz)
RIDD
Run supply current measured at
(CPU clock = 40 MHz, fBus = 20 MHz)
RIDD
Wait mode supply current measured at
(CPU clock = 8 MHz, fBus = 4 MHz)
(FEI mode, all modules off)
WIDD
VDD
(V)
Typ1
Max2
5
9.4
10
3
9
10
5
14.3
30
3
13.9
20
5
16
30
3
—
—
5
2.7
—
Unit
mA
mA
mA
mA
Stop3 mode supply current
7
C
–40C
0.96
—
P
25C
1.3
—
C
85C
7.5
25
P6
105C
37
90
P
125C
65
150
C
–40C
0.85
—
P
25C
1.2
—
C
85C
6.5
20
P6
105C
32.7
80
P
125C
58
130
C
–40C
0.94
—
P
25C
1.25
—
C
85C
7
25
P6
105C
30
65
P
125C
64
120
C
–40C
0.83
—
P
25C
1.1
—
C
85C
6.3
20
P6
105C
25
55
125C
57
100
5
300
500
nA
3
300
500
nA
5
S3IDD
3
A
A
Stop2 mode supply current
8
P
C
9
RTC adder to stop2 or
stop37
5
S2IDD
3
S23IDDRTC
A
A
MC9S08MP16 Series Data Sheet, Rev. 2
16
Freescale Semiconductor
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Num
C
C
Parameter
LVD adder to stop3 (LVDE = LVDSE = 1)
10
11
1
2
3
4
5
6
7
8
C
Adder to stop3 for oscillator
(EREFSTEN =1)
enabled8
Symbol
VDD
(V)
Typ1
Max2
Unit
S3IDDLVD
5
110
180
A
3
90
160
A
5,3
5
8
A
S3IDDOSC
Typical values are based on characterization data at 25C. See Figure 9 through Figure 14 for typical curves across
temperature and voltage.
Max values in this column apply for the full operating temperature range of the device unless otherwise noted.
All modules except ADC active, ICS configured for FBELP, and does not include any dc loads on port pins
All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins
All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins
Stop currents are tested in production for 25C on all parts. Tests at other temperatures depend upon the part
number suffix and maturity of the product. Freescale may eliminate a test insertion at a particular temperature from
the production test flow once sufficient data has been collected and is approved.
Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher
current wait mode.
Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal and low
power mode (HGO = 0).
16
FBE
FEI
14
Run Idd (mA)
12
10
8
6
4
2
0
2
8
16
20
25
fbus (MHz)
Figure 9. Typical Run IDD vs. Bus Frequency (VDD = 5V)
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
17
Electrical Characteristics
6
FBE
FEI
Run IDD (mA)
5
4
3
2
1
-40
0
25
85
105
125
Temperature (C)
Figure 10. Typical Run IDD vs. Temperature (VDD = 5V, fbus = 8MHz)
16
FBE
FEI
14
Run Idd (mA)
12
10
8
6
4
2
0
2
8
16
20
25
fbus (MHz)
Figure 11. Typical Run IDD vs. Bus Frequency (VDD = 3V)
MC9S08MP16 Series Data Sheet, Rev. 2
18
Freescale Semiconductor
Electrical Characteristics
6
FBE
FEI
Run IDD (mA)
5
4
3
2
1
-40
0
25
85
105
125
Temperature (C)
Figure 12. Typical Run IDD vs. Temperature (VDD = 3V, fbus = 8MHz)
70
STOP2
STOP3
60
Stop IDD (uA)
50
40
30
20
10
0
-40
25
85
105
125
Temperature (C)
Figure 13. Typical Stop IDD vs. Temperature (VDD = 5V)
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
19
Electrical Characteristics
70
STOP2
STOP3
60
Stop IDD (uA)
50
40
30
20
10
0
-40
25
85
105
125
Temperature (C)
Figure 14. Typical Stop IDD vs. Temperature (VDD = 3V)
2.8
External Oscillator (XOSC) Characteristics
Table 9. Oscillator Electrical Specifications
Num
Symbol
Min
Typ1
Max
Unit
flo
32
—
38.4
kHz
fhi
1
—
16
MHz
High range (RANGE = 1, HGO = 1) FBELP mode
fhi-hgo
1
—
16
MHz
High range (RANGE = 1, HGO = 0) FBELP mode
fhi-lp
1
—
8
MHz
C
Rating
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
1
2
C
—
High range (RANGE = 1)
FEE2 or
FBE3 mode
Load capacitors
C1, C2
See crystal or resonator
manufacturer’s recommendation.
Feedback resistor
3
—
Low range (32 kHz to 100 kHz)
RF
—
10
—
—
1
—
Low range, low gain (RANGE = 0, HGO = 0)
—
0
—
Low range, high gain (RANGE = 0, HGO = 1)
—
100
—
—
0
—
High range (1 MHz to 16 MHz)
M
Series resistor
High range, low gain (RANGE = 1, HGO = 0)
4
—
High range, high gain (RANGE = 1, HGO = 1)
RS
k
8 MHz
—
0
0
MHz
—
0
10
MHz
—
0
20
MC9S08MP16 Series Data Sheet, Rev. 2
20
Freescale Semiconductor
Electrical Characteristics
Table 9. Oscillator Electrical Specifications (continued)
Num
Symbol
Min
Typ1
Max
t
CSTL-LP
—
200
—
CSTL-HGO
—
400
—
High range, low gain (RANGE = 1, HGO = 0)5
t
CSTH-LP
—
5
—
High range, high gain (RANGE = 1, HGO = 1)4
t
CSTH-HGO
—
20
—
0.03125
—
51.34
MHz
0
—
51.34
MHz
0
—
51.34
MHz
C
Rating
Unit
Crystal start-up time 4
Low range, low gain (RANGE = 0, HGO = 0)
5
T
Low range, high gain (RANGE = 0, HGO = 1)
t
ms
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode 2
6
T
fextal
FBE mode 3
FBELP mode
1
Typical data was characterized at 5.0 V, 25C or is recommended value.
The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
3 The input clock source must be divided using RDIV to less than or equal to 39.0625 kHz.
4 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve
specifications.
5 4 MHz crystal
2
MCU
EXTAL
XTAL
RF
C1
2.9
Crystal or Resonator
RS
C2
Internal Clock Source (ICS) Characteristics
Table 10. ICS Frequency Specifications
Symbol
Min
Typ1
Max
Unit
Average internal reference frequency — factory trimmed
(consumer- and industrial-qualified devices)
at VDD = 5 V and temperature = 25C
fint_t
—
32.768
—
kHz
P
Average internal reference frequency — factory trimmed
(automotive-qualified devices)
at VDD = 5 V and temperature = 25C
fint_t
—
31.25
—
kHz
2
P
Internal reference frequency — user trimmed
fint_t
31.25
—
39.06
kHz
3
T
Internal reference start-up time
tirefst
—
60
100
s
Num
C
1a
P
1b
Characteristic
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
21
Electrical Characteristics
Table 10. ICS Frequency Specifications (continued)
Num
C
Characteristic
Symbol
P
4
Low range (DRS=00)
DCO output frequency range —
C
Mid range (DRS=01)
trimmed 2
P
High range (DRS=10)
P
5
P
P
DCO output frequency 2
Reference = 32768 Hz and
DMX32 = 1
fdco_t
Low range (DRS=00)
Mid range (DRS=01)
fdco_DMX32
High range (DRS=10)
Min
Typ1
Max
16
—
20
32
—
40
48
—
60
—
19.92
—
—
39.85
—
—
59.77
—
Unit
MHz
MHz
6
C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)
fdco_res_t
—
0.1
0.2
%fdco
7
C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)
fdco_res_t
—
0.2
0.4
%fdco
8
P
Total deviation of trimmed DCO output frequency over voltage and
temperature
fdco_t
—
0.8
2
%fdco
9
C
Total deviation of trimmed DCO output frequency over fixed voltage
and temperature range of 0C to 70 C
fdco_t
—
0.5
1
%fdco
10
C FLL acquisition time 3
tAcquire
—
—
1
ms
11
C Long term jitter of DCO output clock (averaged over 2-ms interval) 4
CJitter
—
0.02
0.2
%fdco
1
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given
interval.
2
MC9S08MP16 Series Data Sheet, Rev. 2
22
Freescale Semiconductor
Electrical Characteristics
Deviation from Trimmed Frequency
3%
2%
1%
0%
-1%
-2%
-3%
-40
-20
0
20
40
60
80
100
120
Temperature (C)
Figure 15. Typical Frequency Deviation vs Temperature (ICS Trimmed to 25 MHz bus@25°C, 5V, FEI)1
2.10
ADC Characteristics
Table 11. 12-bit ADC Operating Conditions
Symbol
Min
Typ1
Max
Unit
VDDA
2.7
—
5.5
V
Input Voltage
VADIN
VREFL
—
VREFH
V
Input Capacitance
CADIN
—
4.5
5.5
pF
Input Resistance
RADIN
—
3
5
k
—
—
—
—
2
5
10 bit mode
fADCK > 4MHz
fADCK < 4MHz
—
—
—
—
5
10
8 bit mode (all valid fADCK)
—
—
10
0.4
—
8.0
0.4
—
4.0
Characteristic
Supply voltage
Analog Source
Resistance
ADC Conversion
Clock Freq.
1
Conditions
Absolute
12 bit mode
fADCK > 4MHz
fADCK < 4MHz
High Speed (ADLPC=0)
Low Power (ADLPC=1)
RAS
fADCK
k
Comment
External to MCU
MHz
Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
1. Based on the average of several hundred units from a typical characterization lot.
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
23
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
+
VADIN
VAS
–
CAS
+
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 16. ADC Input Impedance Equivalency Diagram
Table 12. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
C
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
T
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
IDDA
—
133
—
A
T
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
IDDA
—
218
—
A
T
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
IDDA
—
327
—
A
T
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
IDDA
—
0.582
—
mA
P
ADC Asynchronous High Speed (ADLPC=0)
Clock Source
Low Power (ADLPC=1)
fADACK
2
3.3
5
MHz
1.25
2
3.3
Comment
tADACK =
1/fADACK
MC9S08MP16 Series Data Sheet, Rev. 2
24
Freescale Semiconductor
Electrical Characteristics
Table 12. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
C
Characteristic
D
Conversion Time
(Including sample
time)
D
Sample Time
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Short Sample (ADLSMP=0)
tADC
—
20
—
—
40
—
ADCK
cycles
—
3.5
—
—
23.5
—
See ADC
chapter in the
Reference
Manual for
conversion time
variances
—
3.266
—
—
3.638
—
VTEMP25
—
1.396
—
mV
ETUE
—
3.0
6.5
LSB2
10 bit mode
—
1
2.5
8 bit mode
—
0.5
1.0
—
1.75
3.5
—
0.5
1.0
—
0.3
0.5
—
1.5
4.5
10 bit mode
—
0.5
1.0
8 bit mode
—
0.3
0.5
—
1.5
0.0/
-3.0
Long Sample (ADLSMP=1)
Short Sample (ADLSMP=0)
tADS
Long Sample (ADLSMP=1)
T
Temp Sensor
Slope
-40C to 25C
T
Temp Sensor
Voltage
25C
T
Total Unadjusted
Error
12 bit mode
P
T
T
P
Differential
Non-Linearity
P
12 bit mode
DNL
10 bit mode3
8 bit mode
Integral
Non-Linearity
T
T
25C to 125C
3
T
T
m
Zero-Scale Error
12 bit mode
12 bit mode
INL
EZS
P
10 bit mode
—
0.5
1.5
T
8 bit mode
—
0.5
0.5
—
1.0
+1.75/
1.25
T
Full-Scale Error
12 bit mode
EFS
T
10 bit mode
—
0.5
1
T
8 bit mode
—
0.5
0.5
—
-1 to 0
—
10 bit mode
—
—
0.5
8 bit mode
—
—
0.5
—
1
—
10 bit mode
—
0.2
2.5
8 bit mode
—
0.1
1
D
D
Quantization Error
12 bit mode
Input Leakage Error 12 bit mode
EQ
EIL
ADCK
cycles
mV/C
Includes
quantization
LSB2
LSB2
LSB2
VADIN = VSSAD
LSB2
VADIN = VDDAD
LSB2
LSB2
Pad leakage4 *
RAS
1
Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
1 LSB = (VREFH - VREFL)/2N
3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
4 Based on input pad leakage current. Refer to pad electricals.
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
25
Electrical Characteristics
2.11
•
•
•
Digital to Analog (DAC) Characteristics
The accuracy at worst case: +/- 1.5% maximum
The settling time must be less than 100 ns
When changing the output voltage level, the voltage glitch cannot be completely eliminated
Table 13. 5-bit DAC Characteristics
Num
C
2
D
Supply current adder (enabled)
3
D
DAC reference inputs
5
D
DAC step size
6
D
DAC voltage range
2.12
Characteristic
Symbol
Min
Typical
Max
Unit
IDDAC
—
—
20
A
Vin
VSSA
—
VDDA
V
Vstep
0.75 Vin/32
Vin/32
1.25 Vin/32
V
Vdacout
Vin/32
—
Vin
V
High Speed Comparator (HSCMP) Characteristics
Table 14. High Speed Comparator Electrical Specifications
1
2
Characteristic1
Symbol
Min
Typical
Supply current, High Speed Mode
(EN=1, PMODE=1)
IDDAHS
—
200
A
D
Supply current, Low Speed Mode
(EN=1, PMODE=0)
IDDALS
—
10
A
3
—
Analog input voltage
VAIN
VSSA
—
VDDA
V
4
P
Analog input offset voltage
VAIO
—
5
40
mV
5
C
Analog Comparator hysteresis
VH
3.0
9
20.0
mV
6
T
Propagation Delay, High Speed Mode
(EN=1, PMODE=1)
tDHS2
—
70
120
ns
7
T
Propagation Delay, Low Speed Mode
(EN=1, PMODE=0)
tDLS2
—
400
600
ns
8
D
Analog comparator initialization delay
tAINIT
—
400
—
ns
Num
C
1
D
2
Max
Unit
All timing assumes slew rate control disabled and high drive strength enabled.
Delay from analog input to the CMPxOUT output pin. Measured with an input waveform that switches 30 mV above and
below the reference.
2.13
Programmable Gain Amplifier (PGA) Characteristics
Table 15. Programmable Gain Amplifier Electrical Specifications
Num
C
1
T
Parameter
Supply current adder
• normal mode (LP=0)
• low power mode (LP=1)
2
T
Supply current adder (stand-by)
3
T
Absolute analog input level
Symbol
Min
Typical
Max
—
—
450
250
550
300
IDDAOFF
—
1
10
nA
VIL
VSSA
VDDA/2
VDDA
V
IDDON
uA
MC9S08MP16 Series Data Sheet, Rev. 2
26
Unit
Freescale Semiconductor
Electrical Characteristics
Table 15. Programmable Gain Amplifier Electrical Specifications (continued)
Num
C
Parameter
Symbol
4
D
Differential input voltage
VDIFFMAX
5
T
Linearity (@ voltage gain)1
• 1x
• 2x
• 4x
• 8x
• 16x
• 32x
LV
EG
T
Max gain error
7a
D
PGA clock
• normal mode (LP=0)
• low power mode (LP=1)
fPGA
PGA sampling frequency3
fSAMPL
D
(
V DDA – 1.4
– ----------------------------2 Gain
Typical
Max
0
)
Unit
V
V DDA – 1.4
-----------------------------2 Gain
V/V
6
7b
Min
1 – 1/2 LSB
2 – 1/2 LSB
4 – 1 LSB
8 – 1 LSB
16 – 4 LSB
32 – 4 LSB
1
2
4
8
16
32
1 + 1/2 LSB
2 + 1/2 LSB
4 + 1 LSB
8 + 1 LSB
16 + 4 LSB
32 + 4 LSB
—
1
2
—
—
82
4
82
4
—
1
---------------------------------------------------------------------------------------------------12 + 18 NUM_CLK_GS
5
43
-----------------------------------------------------------------+ ------------- + ------------
f
f
f
—
Samples
per second
%
MHz
PGA
ADC
BUS
8
D
Input signal bandwidth
BW
0
fSAMPL 8
fSAMPL 2
Hz
9
D
Charge pump clock frequency
fcpclk
100
fPGA 4
—
Hz
1
LSB in 12-bit resolution
8 MHz is required for PGA achieving 1 s sampling time.
3 ADC in 12-bit mode, long sampling time, f
ADC = fPGA
2
2.14
AC Characteristics
This section describes timing characteristics for each peripheral system.
2.14.1
Control Timing
Table 16. Control Timing
Num
C
1
D
2
P
Symbol
Min
Typ1
Max
Unit
–40 to 105 C
fBus
DC
—
25.67
MHz
–40 to 125 C
fBus
DC
—
20
MHz
tLPO
700
—
1300
s
textrst
100
—
—
ns
Rating
Bus frequency
(tcyc = 1/fBus)
Internal low power oscillator period
width2
3
D
External reset pulse
4
D
Reset low drive
trstdrv
34 x tcyc
—
—
ns
5
D
BKGD/MS setup time after issuing background debug force
reset to enter user or BDM modes
tMSSU
500
—
—
ns
6
D
BKGD/MS hold time after issuing background debug force
reset to enter user or BDM modes 3
tMSH
100
—
—
s
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
27
Electrical Characteristics
Table 16. Control Timing (continued)
Num
C
7
D
8
1
2
3
4
5
6
C
Rating
Symbol
Min
Typ1
Max
tILIH, tIHIL
100
1.5 x tcyc
—
—
—
—
Unit
ns
Keyboard interrupt pulse width
Asynchronous path4
Synchronous path5
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
ns
—
—
40
75
—
—
ns
—
—
11
35
—
—
Typical values are based on characterization data at VDD = 5.0V, 25C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises
above VLVD.
This is the minimum pulse width that is guaranteed to be recognized as a keyboard interrupt request in stop mode.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not
be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40C to 125C.
textrst
RESET PIN
Figure 17. Reset Timing
tIHIL
KBIxPn
KBIxPn
tILIH
Figure 18. KBIxPn Timing
2.14.2
FTM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the FTM timer counter. These synchronizers operate from the current ICSOUT clock. The ICSOUT
clock period = 0.5 tcyc = 1/(fBus 2).
Table 17. FTM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
D
External clock frequency
fTCLK
0
fICSOUT/41
Hz
2
D
External clock period
tTCLK
2
—
tcyc
3
D
External clock high time
tclkh
0.75
—
tcyc
MC9S08MP16 Series Data Sheet, Rev. 2
28
Freescale Semiconductor
Electrical Characteristics
Table 17. FTM Input Timing (continued)
1
No.
C
Function
4
D
External clock low time
5
D
Input capture pulse width
Symbol
Min
Max
Unit
tclkl
0.75
—
tcyc
tICPW
0.75
—
tcyc
The maximum external clock frequency is limited to 10MHz due to input filter characteristics.
tTCLK
tclkh
TCLK
tclkl
Figure 19. FTM External Clock
tICPW
FTMxCHn
FTMxCHn
tICPW
Figure 20. FTM Input Capture Pulse
2.14.3
MTIM Module Timing
Synchronizer circuits determine the fastest clock that can be used as the optional external clock source to the MTIM timer
counter. These synchronizers operate from the current bus rate clock.
Table 18. MTIM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
D
External clock frequency
fTCLK
0
fBus/4
Hz
2
D
External clock period
tTCLK
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 21. MTIM Timer External Clock
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
29
Electrical Characteristics
2.14.4
SPI
Table 19 and Figure 22 through Figure 25 describe the timing requirements for the SPI system.
Table 19. SPI Electrical Characteristics
Num1
C
1
D
Rating2
Symbol
Min
Max
Unit
Master
Slave
tSCK
tSCK
2
4
4096
—
tcyc
tcyc
Master
Slave
tLead
tLead
—
1/2
1/2
—
tSCK
tSCK
Master
Slave
tLag
tLag
—
1/2
1/2
—
tSCK
tSCK
Cycle time
Enable lead time
2
D
3
D
4
D
Clock (SPSCK) high time
Master and Slave
tSCKH
1/2 tSCK – 25
—
ns
5
D
Clock (SPSCK) low time
Master and Slave
tSCKL
1/2 tSCK – 25
—
ns
6
D
Master
Slave
tSI(M)
tSI(S)
30
30
—
—
ns
ns
7
D
Master
Slave
tHI(M)
tHI(S)
30
30
—
—
ns
ns
8
D
Access time, slave3
tA
0
40
ns
9
D
slave4
tdis
—
40
ns
10
D
Master
Slave
tSO
tSO
—
—
25
25
ns
ns
11
D
Master
Slave
tHO
tHO
–10
–10
—
—
ns
ns
fBus/4096
dc
fBus/4096
dc
85
fBus/4
56
56
MHz
Enable lag time
Data setup time (inputs)
Data hold time (inputs)
Disable time,
Data setup time (outputs)
Data hold time (outputs)
Operating frequency
12
1
2
3
4
5
6
D
Master
Slave
Master
Slave
(SPIFE=0)
(SPIFE=0)
(SPIFE=1)
(SPIFE=1)
fop
MHz
MHz
Refer to Figure 22 through Figure 25.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All
timing assumes slew rate control disabled and high drive strength enabled for SPI output pins.
Time to data active from high-impedance state.
Hold time to high-impedance state.
Maximum baud rate must be limited to 8 MHz.
Maximum baud rate must be limited to 5 MHz due to input filter characteristics.
MC9S08MP16 Series Data Sheet, Rev. 2
30
Freescale Semiconductor
Electrical Characteristics
SS1
(OUTPUT)
3
1
2
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN2
BIT 6 . . . 1
10
MOSI
(OUTPUT)
LSB IN
11
10
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 22. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
3
2
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN(2)
LSB IN
11
10
MOSI
(OUTPUT)
BIT 6 . . . 1
MSB OUT(2)
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 23. SPI Master Timing (CPHA = 1)
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
31
Electrical Characteristics
SS
(INPUT)
3
1
SCK
(CPOL = 0)
(INPUT)
5
4
2
SCK
(CPOL = 1)
(INPUT)
5
4
8
MISO
(OUTPUT)
11
10
BIT 6 . . . 1
MSB OUT
SLAVE
SLAVE LSB OUT
SEE
NOTE
7
6
MOSI
(INPUT)
9
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 24. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
3
1
2
SCK
(CPOL = 0)
(INPUT)
5
4
SCK
(CPOL = 1)
(INPUT)
5
4
10
MISO
(OUTPUT)
SEE
NOTE
8
MOSI
(INPUT)
SLAVE
11
MSB OUT
6
BIT 6 . . . 1
9
SLAVE LSB OUT
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 25. SPI Slave Timing (CPHA = 1)
MC9S08MP16 Series Data Sheet, Rev. 2
32
Freescale Semiconductor
Electrical Characteristics
2.15
Flash Memory Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see the Memory section.
Table 20. Flash Memory Characteristics
Num
1
2
C
—
—
Characteristic
Symbol
Supply voltage for program/erase
-40C to 125C
Vprog/erase
Supply voltage for read operation
frequency1
Min
Typical
Max
Unit
2.7
5.5
VRead
2.7
5.5
V
fFCLK
150
200
kHz
5
6.67
s
V
3
—
Internal FCLK
4
—
Internal FCLK period (1/FCLK)
tFcyc
5
C
Byte program time (random location)2
tprog
9
tFcyc
6
7
—
D
Byte program time (burst
tBurst
4
tFcyc
Page erase
time2
tPage
4000
tFcyc
time2
tMass
20,000
tFcyc
8
D
Mass erase
9
C
Byte program current3
10
C
mode)2
Page erase current
3
RIDDBP
—
4
—
mA
RIDDPE
—
6
—
mA
10,000
—
100,000
—
—
cycles
15
100
—
years
endurance4
11
C
Program/erase
TL to TH = –40C to + 125C
T = 25C
12
C
Data retention5
tD_ret
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with
VDD = 5.0 V, bus frequency = 4.0 MHz.
4 Typical endurance for Flash is based upon the intrinsic bit cell performance. For additional information on how Freescale defines
typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to
25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to
Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
2
2.16
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
2.16.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
33
Ordering Information
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East).
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.
Table 21. Radiated Emissions, Electric Field
Parameter
Symbol
Radiated emissions,
electric field
Conditions
VRE_TEM
VDD = 5V
TA = +25C
package type
48 LQFP
Frequency
fOSC/fBUS
Level1
(Max)
0.15 – 50 MHz
3
50 – 150 MHz
8
150 – 500 MHz
dBV
–4
4 MHz crystal
2 MHz bus
500 – 1000 MHz
Unit
–8
2
IEC Level
N
—
SAE Level3
1
—
1
Data based on qualification test results. The reported emission level is the value of the maximum emission, rounded up to the
next whole number, from among the measured orientations in each frequency range.
2
IEC level maximums: N 12 dBV, L 24 dBV, I 36 dBV
3
SAE level maximums: 1 10 dBV, 2 20 dBV, 3 30 dBV, 4 40 dBV
3
Ordering Information
This section contains ordering information for MC9S08MP16 and MC9S08MP12 devices.
Table 22. Device and Package Options
Device Number1
Temp
Range
Available Packages2
Memory
Flash
RAM
48-Pin
32-Pin
28-Pin
Consumer and Industrial Qualification
MC9S08MP16
V
16K
1024
48 LQFP
32 LQFP
28 SOIC
MC9S08MP12
V
12K
512
—
—
28 SOIC
—
—
Automotive Qualification
S9S08MP16
C, V, M
16K
1024
48 LQFP
1
See the MC9S08MP16RM Reference Manual (MC9S08MP16RM) for a complete description of modules included on each
device.
2 See Table 23 for package information.
MC9S08MP16 Series Data Sheet, Rev. 2
34
Freescale Semiconductor
Package Information
3.1
Device Numbering Scheme
Example of the device numbering system:
xx 9 S08 MP nn E2 y zz
Package designator (see Table 23)
Status
MC = Consumer &
Industrial
S = Automotive Qualified
Memory
9 = Flash-based
Core
Temperature range
C = –40C to 85C
V = –40C to 105C
M = –40C to 125C
Wafer fab site and mask revision
(this field appears only in automotive-qualified
part numbers)
Family
4
Flash size
16 KBytes
12 KBytes
Package Information
The latest package outline drawings are available on the product summary pages on our web site:
http://www.freescale.com/8bit. The following table lists the document numbers per package. Use these numbers in the web
page’s keyword search engine to find the latest package outline drawings.
NOTE
The 32 LQFP and 28 SOIC are not qualified to meet automotive requirements.
Table 23. Package Descriptions
5
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
48
Low Quad Flat Pack
LQFP
LF
932-03
98ASH00962A
32
Low Quad Flat Pack
LQFP
LC
873A-03
98ASH70029A
28
Small Outline Integrated Circuit
SOIC
WL
751F-05
98ASB42345B
Related Documentation
Find the most current versions of all documents at http://www.freescale.com.
Reference Manual
(MC9S08MP16RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
6
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your
printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://www.freescale.com
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
35
Table 24 summarizes changes contained in this document.
Table 24. Revision History
Rev
Date
Description of Changes
1
10/15/2009
Initial public revision
2
08/09/2011
Updated Table 10. Changed the value of row 8 column “C” from to C to P.
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