MCIMX31LVKN5CR2

Freescale Semiconductor Data Sheet: Technical Data Document Number: MCIMX31 Rev. 4.1, 11/2008 MCIMX31 and MCIMX31L MCIMX31 and MCIMX31L Multimedia Applications Processors 1 Introduction The MCIMX31 and MCIMX31L multimedia applications processors represent the next step in low-power, high-performance application processors. Unless otherwise specified, the material in this data sheet is applicable to both the MCIMX31 and MCIMX31L processors and referred to singularly throughout this document as MCIMX31. The MCIMX31L does not include a graphics processing unit (GPU). Based on an ARM11™ microprocessor core, the MCIMX31 provides the performance with low power consumption required by modern digital devices such as: • Feature-rich cellular phones • Portable media players and mobile gaming machines • Personal digital assistants (PDAs) and Wireless PDAs • Portable DVD players • Digital cameras Package Information Plastic Package Case 1581 14 x 14 mm, 0.5 mm Pitch Case 1931 19 x 19 mm, 0.8 mm Pitch Ordering Information See Table 1 on page 3 for ordering information. Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering Information . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ARM11 Microprocessor Core . . . . . . . . . . . . . . 4 Module Inventory . . . . . . . . . . . . . . . . . . . . . . . 6 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . 10 Chip-Level Conditions . . . . . . . . . . . . . . . . . . 10 Supply Power-Up/Power-Down Requirements and Restrictions . . . . . . . . . . . . . . . . . . . . 18 Module-Level Electrical Specifications . . . . . . 21 Package Information and Pinout . . . . . . . . . 104 MAPBGA Production Package— 457 14 x 14 mm, 0.5 mm Pitch . . . . . . . . . . . 104 MAPBGA Production Package— 473 19 x 19 mm, 0.8 mm Pitch . . . . . . . . . . . 110 Ball Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Product Differences . . . . . . . . . . . . . . . . . . . . 118 Product Documentation . . . . . . . . . . . . . . . . 119 Revision History . . . . . . . . . . . . . . . . . . . . . . . 120 The MCIMX31 takes advantage of the ARM1136JF-S™ core running at up to 532 MHz, and is optimized for This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005–2008. All rights reserved. Introduction minimal power consumption using the most advanced techniques for power saving (DPTC, DVFS, power gating, clock gating). With 90 nm technology and dual-Vt transistors (two threshold voltages), the MCIMX31 provides the optimal performance versus leakage current balance. The performance of the MCIMX31 is boosted by a multi-level cache system, and features peripheral devices such as an MPEG-4 Hardware Encoder (VGA, 30 fps), an Autonomous Image Processing Unit, a Vector Floating Point (VFP11) co-processor, and a RISC-based SDMA controller. The MCIMX31 supports connections to various types of external memories, such as DDR, NAND Flash, NOR Flash, SDRAM, and SRAM. The MCIMX31 can be connected to a variety of external devices using technology, such as high-speed USB2.0 OTG, ATA, MMC/SDIO, and compact flash. 1.1 Features The MCIMX31 is designed for the high-tier, mid-tier smartphone markets, and portable media players. They provide low-power solutions for high-performance demanding multimedia and graphics applications. The MCIMX31 is built around the ARM11 MCU core and implemented in the 90 nm technology. The systems include the following features: • Multimedia and floating-point hardware acceleration supporting: — MPEG-4 real-time encode of up to VGA at 30 fps — MPEG-4 real-time video post-processing of up to VGA at 30 fps — Video conference call of up to QCIF-30 fps (decoder in software), 128 kbps — Video streaming (playback) of up to VGA-30 fps, 384 kbps — 3D graphics and other applications acceleration with the ARM® tightly-coupled Vector Floating Point co-processor — On-the-fly video processing that reduces system memory load (for example, the power-efficient viewfinder application with no involvement of either the memory system or the ARM CPU) • Advanced power management — Dynamic voltage and frequency scaling — Multiple clock and power domains — Independent gating of power domains • Multiple communication and expansion ports including a fast parallel interface to an external graphic accelerator (supporting major graphic accelerator vendors) • Security MCIMX31/MCIMX31L Technical Data, Rev. 4.1 2 Freescale Semiconductor Introduction 1.2 Ordering Information Table 1 provides the ordering information for the MCIMX31. Table 1. Ordering Information 1 2 3 4 5 Part Number Silicon Revision1, 2, 3,4 Device Mask Operating Temperature Range (°C) MCIMX31VKN5 1.15 2L38W and 3L38W 0 to 70 MCIMX31LVKN5 1.15 2L38W and 3L38W 0 to 70 MCIMX31VKN5B 1.2 M45G 0 to 70 MCIMX31LVKN5B 1.2 M45G 0 to 70 MCIMX31VKN5C 2.0 M91E 0 to 70 MCIMX31LVKN5C 2.0 M91E 0 to 70 MCIMX31CVKN5C 2.0 M91E –40 to 85 MCIMX31LCVKN5C 2.0 M91E –40 to 85 MCIMX31VMN5C 2.0 M91E 0 to 70 MCIMX31LVMN5C 2.0 M91E 0 to 70 Package5 14 x 14 mm, 0.5 mm pitch, MAPBGA-457, Case 1581 14 x 14 mm, 0.5 mm pitch, MAPBGA-457, Case 1581 19 x 19 mm, 0.8 mm pitch, Case 1931 Information on reading the silicon revision register can be found in the IC Identification (IIM) chapter of the Reference Manual, see Section 7, “Product Documentation.” Errata and fix information of the various mask sets can be found in the standard MCIMX31 Chip Errata, see Section 7, “Product Documentation.” Changes in output buffer characteristics can be found in the I/O Setting Exceptions and Special Pad Descriptions table in the Reference Manual, see Section 7, “Product Documentation.” JTAG functionality is not tested nor guaranteed at -40°C. Case 1581 and 1931 are RoHS compliant, lead-free, MSL = 3, and solders at 260°C. 1.2.1 Feature Differences Between Mask Sets The following is a summary of differences between silicon Revision 2.0, mask set M91E, and previous revisions of silicon. A complete list of these differences is given in Table 72. • Extended operating temperature range is available: –40°C to 85°C • Supply current information changes, as shown in Table 13 and Table 14 • FUSE_VDD supply voltage is floated or grounded during read operation • No restriction on PLL versus core supply voltage • Operating frequency as shown in Table 8. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 3 Functional Description and Application Information 1.3 Block Diagram Figure 1 shows the MCIMX31 simplified interface block diagram. SRAM, PSRAM, NOR Flash SDRAM DDR NAND Flash, SmartMedia Parallel Display (2) Camera Sensor (2) Serial LCD Tamper Detection Mouse Keyboard External Memory Interface (EMI) Camera Interface AP Peripherals AUDMUX SSI (2) Blending UART (5) Image Processing Unit (IPU) Inversion and Rotation MPEG-4 Video Encoder SDMA I2C (3) FIR CSPI (3) PWM USB Host (2) Display/TV Ctl Pre and Post Processing Internal Memory Expansion ARM11TM Platform SDHC (2) PCMCIA/CF Mem Stick (2) ARM1136JF-STM I-Cache D-Cache SIM L2-Cache Debug ECT SJC Timers RTC WDOG USB-OTG KPP GPT EPIT (2) GPIO CCM 1-WIRE® IIM ATA MAX ROMPATCH Security SCC RTIC Power Management IC 8x8 Keypad Serial EPROM GPU* RNGA GPS VFP ETM Fast IrDA * GPU unavailable for i.MX31L Bluetooth Baseband WLAN SD Card PC Card PC Card ATA Hard Drive USB Host/Device Figure 1. MCIMX31 Simplified Interface Block Diagram 2 2.1 Functional Description and Application Information ARM11 Microprocessor Core The CPU of the MCIMX31 is the ARM1136JF-S core based on the ARM v6 architecture. It supports the ARM Thumb® instruction sets, features Jazelle® technology (which enables direct execution of Java byte codes), and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers. The ARM1136JF-S processor core features: • Integer unit with integral EmbeddedICE™ logic • Eight-stage pipeline • Branch prediction with return stack • Low-interrupt latency MCIMX31/MCIMX31L Technical Data, Rev. 4.1 4 Freescale Semiconductor Functional Description and Application Information • • • • • • • • Instruction and data memory management units (MMUs), managed using micro TLB structures backed by a unified main TLB Instruction and data L1 caches, including a non-blocking data cache with Hit-Under-Miss Virtually indexed/physically addressed L1 caches 64-bit interface to both L1 caches Write buffer (bypassable) High-speed Advanced Micro Bus Architecture (AMBA)™ L2 interface Vector Floating Point co-processor (VFP) for 3D graphics and other floating-point applications hardware acceleration ETM™ and JTAG-based debug support 2.1.1 Memory System The ARM1136JF-S complex includes 16 KB Instruction and 16 KB Data L1 caches. It connects to the MCIMX31 L2 unified cache through 64-bit instruction (read-only), 64-bit data read/write (bi-directional), and 64-bit data write interfaces. The embedded 16K SRAM can be used for audio streaming data to avoid external memory accesses for the low-power audio playback, for security, or for other applications. There is also a 32-KB ROM for bootstrap code and other frequently-used code and data. A ROM patch module provides the ability to patch the internal ROM. It can also initiate an external boot by overriding the boot reset sequence by a jump to a configurable address. Table 2 shows information about the MCIMX31 core in tabular form. Table 2. MCIMX31 Core Core Acronym Core Name ARM11 or ARM1136 ARM1136 Platform Brief Description The ARM1136™ Platform consists of the ARM1136JF-S core, the ETM real-time debug modules, a 6 x 5 multi-layer AHB crossbar switch (MAX), and a Vector Floating Processor (VFP). The MCIMX31 provides a high-performance ARM11 microprocessor core and highly integrated system functions. The ARM Application Processor (AP) and other subsystems address the needs of the personal, wireless, and portable product market with integrated peripherals, advanced processor core, and power management capabilities. Integrated Memory Includes • 16 Kbyte Instruction Cache • 16 Kbyte Data Cache • 128 Kbyte L2 Cache • 32 Kbyte ROM • 16 Kbyte RAM MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 5 Functional Description and Application Information 2.2 Module Inventory Table 3 shows an alphabetical listing of the modules in the multimedia applications processor. For extended descriptions of the modules, see the reference manual. A cross-reference is provided to the electrical specifications and timing information for each module with external signal connections. Table 3. Digital and Analog Modules Block Mnemonic Block Name Functional Grouping Section/ Page Brief Description 1-Wire® 1-Wire Interface Connectivity The 1-Wire module provides bi-directional communication between Peripheral the ARM11 core and external 1-Wire devices. 4.3.4/26 ATA Advanced Connectivity The ATA block is an AT attachment host interface. It is designed to Technology (AT) Peripheral interface with IDE hard disc drives and ATAPI optical disc drives. Attachment 4.3.5/27 Digital Audio Multiplexer Multimedia Peripheral The AUDMUX interconnections allow multiple, simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint configurations. 4.3.6/36 Clock Amplifier Module Clock The CAMP converts a square wave/sinusoidal input into a rail-to-rail square wave. The output of CAMP feeds the predivider. 4.3.3/25 CCM Clock Control Module Clock The CCM provides clock, reset, and power management control for the MCIMX31. — CSPI Configurable Connectivity The CSPI is equipped with data FIFOs and is a master/slave configurable serial peripheral interface module, capable of Serial Peripheral Peripheral interfacing to both SPI master and slave devices. Interface (x 3) 4.3.7/36 DPLL Digital Phase Lock Loop Clock The DPLLs produce high-frequency on-chip clocks with low frequency and phase jitters. Note: External clock sources provide the reference frequencies. 4.3.8/37 ECT Embedded Cross Trigger Debug The ECT is composed of three CTIs (Cross Trigger Interface) and one CTM (Cross Trigger Matrix—key in the multi-core and multi-peripheral debug strategy. — EMI External Memory Interface Memory Interface (EMI) The EMI includes • Multi-Master Memory Interface (M3IF) • Enhanced SDRAM Controller (ESDCTL) • NAND Flash Controller (NFC) • Wireless External Interface Module (WEIM) EPIT Enhanced Periodic Interrupt Timer Timer Peripheral The EPIT is a 32-bit “set and forget” timer which starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. ETM Embedded Trace Macrocell Debug/Trace The ETM (from ARM, Ltd.) supports real-time instruction and data tracing by way of ETM auxiliary I/O port. 4.3.10/54 FIR Fast InfraRed Interface Connectivity This FIR is capable of establishing a 0.576 Mbit/s, 1.152 Mbit/s or 4 Peripheral Mbit/s half duplex link via a LED and IR detector. It supports 0.576 Mbit/s, 1.152 Mbit/s medium infrared (MIR) physical layer protocol and 4Mbit/s fast infrared (FIR) physical layer protocol defined by IrDA, Rev. 1.4. 4.3.11/55 AUDMUX CAMP — 4.3.9.3/46, 4.3.9.1/38, 4.3.9.2/41 — MCIMX31/MCIMX31L Technical Data, Rev. 4.1 6 Freescale Semiconductor Functional Description and Application Information Table 3. Digital and Analog Modules (continued) Block Mnemonic Fusebox Block Name Functional Grouping Brief Description Section/ Page Fusebox ROM The Fusebox is a ROM that is factory configured by Freescale. GPIO General Purpose I/O Module Pins The GPIO provides several groups of 32-bit bidirectional, general purpose I/O. This peripheral provides dedicated general-purpose signals that can be configured as either inputs or outputs. — GPT General Purpose Timer Timer Peripheral The GPT is a multipurpose module used to measure intervals or generate periodic output. — GPU Graphics Processing Unit Multimedia Peripheral The GPU provides hardware acceleration for 2D and 3D graphics algorithms. — I2C Inter IC Communication Connectivity The I2C provides serial interface for controlling the Sensor Interface Peripheral and other external devices. Data rates of up to 100 Kbits/s are supported. IIM IC Identification Module ID The IIM provides an interface for reading device identification. IPU Image Processing Unit Multimedia Peripheral The IPU processes video and graphics functions in the MCIMX31 and interfaces to video, still image sensors, and displays. KPP Keypad Port Connectivity The KPP is used for keypad matrix scanning or as a general purpose Peripheral I/O. This peripheral simplifies the software task of scanning a keypad matrix. — MPEG-4 MPEG-4 Video Encoder Multimedia Peripherals — MSHC Memory Stick Host Controller Connectivity The MSHC is placed in between the AIPS and the customer memory Peripheral stick to support data transfer from the MCIMX31 to the customer memory stick. 4.3.16/84 PADIO Pads I/O Buffers and Drivers 4.3.1/22 PCM Connectivity The PCMCIA Host Adapter provides the control logic for PCMCIA Peripheral socket interfaces. 4.3.17/86 PWM Pulse-Width Modulator Timer Peripheral The PWM has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. 4.3.18/88 RNGA Random Number Generator Accelerator Security The RNGA module is a digital integrated circuit capable of generating 32-bit random numbers. It is designed to comply with FIPS-140 standards for randomness and non-determinism. — PCMCIA The MPEG-4 encoder accelerates video compression, following the MPEG-4 standard The PADIO serves as the interface between the internal modules and the device's external connections. 4.3.12/55 See also Table 11 4.3.13/56 — 4.3.14/57, 4.3.15/59 RTC Real Time Clock Timer Peripheral The RTC module provides a current stamp of seconds, minutes, hours, and days. Alarm and timer functions are also available for programming. The RTC supports dates from the year 1980 to 2050. — RTIC Run-Time Integrity Checkers The RTIC ensures the integrity of the peripheral memory contents and assists with boot authentication. — Security MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 7 Functional Description and Application Information Table 3. Digital and Analog Modules (continued) Block Mnemonic SCC Block Name Functional Grouping Section/ Page Brief Description Security Controller Module Security The SCC is a hardware component composed of two blocks—the Secure RAM module, and the Security Monitor. The Secure RAM provides a way of securely storing sensitive information. SDHC Secured Digital Host Controller Connectivity The SDHC controls the MMC (MultiMediaCard), SD (Secure Digital) Peripheral memory, and I/O cards by sending commands to cards and performing data accesses to and from the cards. SDMA Smart Direct System Memory Access Control Peripheral The SDMA controller maximizes the system’s performance by relieving the ARM core of the task of bulk data transfer from memory to memory or between memory and on-chip peripherals. — 4.3.19/89 — SIM Subscriber Identification Module Connectivity The SIM interfaces to an external Subscriber Identification Card. It is Peripheral an asynchronous serial interface adapted for Smart Card communication for e-commerce applications. 4.3.20/90 SJC Secure JTAG Controller Debug The SJC provides debug and test control with maximum security and provides a flexible architecture for future derivatives or future multi-cores architecture. 4.3.21/94 SSI Synchronous Serial Interface Multimedia Peripheral The SSI is a full-duplex, serial port that allows the device to communicate with a variety of serial devices, such as standard codecs, Digital Signal Processors (DSPs), microprocessors, peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S) and Intel AC97 standard. 4.3.22/96 UART Universal Asynchronous Receiver/Trans mitter Connectivity The UART provides serial communication capability with external Peripheral devices through an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA compatibility. USB Universal Serial Bus— 2 Host Controllers and 1 OTG (On-The-Go) Connectivity Peripherals WDOG Watchdog Timer Timer Module Peripheral — • USB Host 1 is designed to support transceiverless connection to 4.3.23/104 the on-board peripherals in Low Speed and Full Speed mode, and connection to the ULPI (UTMI+ Low-Pin Count) and Legacy Full Speed transceivers. • USB Host 2 is designed to support transceiverless connection to the Cellular Modem Baseband Processor. • The USB-OTG controller offers HS/FS/LS capabilities in Host mode and HS/FS in device mode. In Host mode, the controller supports direct connection of a FS/LS device (without external hub). In device (bypass) mode, the OTG port functions as gateway between the Host 1 Port and the OTG transceiver. The WDOG module protects against system failures by providing a method for the system to recover from unexpected events or programming errors. — MCIMX31/MCIMX31L Technical Data, Rev. 4.1 8 Freescale Semiconductor Signal Descriptions 3 Signal Descriptions Signal descriptions are in the reference manual. Special signal considerations are listed following this paragraph. The BGA ball assignment is in Section 5, “Package Information and Pinout.” Special Signal Considerations: • Tamper detect (GPIO1_6) Tamper detect logic is used to issue a security violation. This logic is activated if the tamper detect input is asserted. The tamper detect logic is disabled after reset. After enabling the logic, it is impossible to disable it until the next reset. The GPR[16] bit functions as the tamper detect enable bit. GPIO1_6 functions similarly to other I/O with GPIO capabilities regardless of the status of the tamper detect enable bit. (For example, the GPIO1_6 can function as an input with GPIO capabilities, such as sampling through PSR or generating interrupts.) • Power ready (GPIO1_5) The power ready input, GPIO1_5, should be connected to an external power management IC power ready output signal. If not used, GPIO1_5 must either be (a) externally pulled-up to NVCC1 or (b) a no connect, internally pulled-up by enabling the on-chip pull-up resistor. GPIO1_5 is a dedicated input and cannot be used as a general-purpose input/output. • SJC_MOD SJC_MOD must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 kΩ) is allowed, but the value should be much smaller than the on-chip 100 kΩ pull-up. • CE_CONTROL CE_CONTROL is a reserved input and must be externally tied to GND through a 1 kΩ resistor. • TTM_PAD TTM_PAD is for Freescale factory use only. Control bits indicate pull-up/down disabled. However, TTM_PAD is actually connected to an on-chip pull-down device. Users must either float this signal or tie it to GND. • M_REQUEST and M_GRANT These two signals are not utilized internally. The user should make no connection to these signals. • Clock Source Select (CLKSS) The CLKSS is the input that selects the default reference clock source providing input to the DPLL. To select CKIH, tie CLKSS to NVCC1. To select CKIL, tie CLKSS to ground. After initialization, the reference clock source can be changed (initial setting is overwritten) by programming the PRCS bits in the CCMR. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 9 Electrical Characteristics 4 Electrical Characteristics This section provides the device-level and module-level electrical characteristics for the MCIMX31. 4.1 Chip-Level Conditions This section provides the device-level electrical characteristics for the IC. See Table 4 for a quick reference to the individual tables and sections. Table 4. MCIMX31 Chip-Level Conditions For these characteristics, … Topic appears … Table 5, “Absolute Maximum Ratings” on page 10 Table 7, “Thermal Resistance Data—19 × 19 mm Package” on page 11 Table 8, “Operating Ranges” on page 13 Table 9, “Specific Operating Ranges for Silicon Revision 2.0” on page 14 Table 10, “Interface Frequency” on page 14 Section 4.1.1, “Supply Current Specifications” on page 16 Section 4.2, “Supply Power-Up/Power-Down Requirements and Restrictions” on page 19 CAUTION Stresses beyond those listed under Table 5 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Table 8, "Operating Ranges," on page 13 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 5. Absolute Maximum Ratings Parameter Symbol Min Max Units Supply Voltage (Core) QVCCmax –0.5 1.65 V Supply Voltage (I/O) NVCCmax –0.5 3.3 V Input Voltage Range VImax –0.5 NVCC +0.3 V Storage Temperature Tstorage –40 125 oC — 1500 — 200 — 500 — 15 ESD Damage Immunity: Human Body Model (HBM) Machine Model (MM) Vesd Charge Device Model (CDM) Offset voltage allowed in run mode between core supplies. 1 Vcore_offset1 V mV The offset is the difference between all core voltage pair combinations of QVCC, QVCC1, and QVCC4. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 10 Freescale Semiconductor Electrical Characteristics Table 6 provides the thermal resistance data for the 14 × 14 mm, 0.5 mm pitch package. Table 6. Thermal Resistance Data—14 × 14 mm Package Rating Board Symbol Value Unit Notes Junction to Ambient (natural convection) Single layer board (1s) RθJA 56 °C/W 1, 2, 3 Junction to Ambient (natural convection) Four layer board (2s2p) RθJA 30 °C/W 1, 3 Junction to Ambient (@200 ft/min) Single layer board (1s) RθJMA 46 °C/W 1, 2, 3 Junction to Ambient (@200 ft/min) Four layer board (2s2p) RθJMA 26 °C/W 1, 3 Junction to Board — RθJB 17 °C/W 1, 4 Junction to Case — RθJC 10 °C/W 1, 5 Junction to Package Top (natural convection) — ΨJT 2 °C/W 1, 6 NOTES 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Table 7 provides the thermal resistance data for the 19 × 19 mm, 0.8 mm pitch package. Table 7. Thermal Resistance Data—19 × 19 mm Package Rating Board Symbol Value Unit Notes Junction to Ambient (natural convection) Single layer board (1s) RθJA 46 °C/W 1, 2, 3 Junction to Ambient (natural convection) Four layer board (2s2p) RθJA 29 °C/W 1, 2, 3 Junction to Ambient (@200 ft/min) Single layer board (1s) RθJMA 38 °C/W 1, 2, 3 Junction to Ambient (@200 ft/min) Four layer board (2s2p) RθJMA 25 °C/W 1, 2, 3 Junction to Board — RθJB 19 °C/W 1, 3 Junction to Case (Top) — RθJCtop 10 °C/W 1, 4 Junction to Package Top (natural convection) — ΨJT 2 °C/W 1, 5 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 11 Electrical Characteristics 1. 2. 3. 4. 5. NOTES Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 12 Freescale Semiconductor Electrical Characteristics Table 8 provides the operating ranges. NOTE The term NVCC in this section refers to the associated supply rail of an input or output. The association is shown in the Signal Multiplexing chapter of the reference manual. CAUTION NVCC6 and NVCC9 must be at the same voltage potential. These supplies are connected together on-chip to optimize ESD damage immunity. Table 8. Operating Ranges Symbol QVCC, QVCC1, QVCC4 NVCC1, NVCC3–10 NVCC2, NVCC21, NVCC22 Parameter Core Operating Voltage 0 ≤ fARM ≤ 400 MHz, non-overdrive 0 ≤ fARM ≤ 400 MHz, overdrive4 0 ≤ fARM ≤ 532 MHz, overdrive4 Silicon rev 1.15, 1.2, and 2.0 FUSE_VDD TA 1 2 3 4 5 6 Max Units 1.22 >1.47 1.55 1.47 1.65 1.65 V State Retention Voltage5 0.95 — I/O Supply Voltage, except DDR6non-overdrive overdrive7 1.75 >3.1 3.1 3.3 V I/O Supply Voltage, DDR only 1.75 1.95 V 1.3 >1.47 1.47 1.6 1.6 1.9 V 1.65 1.95 V 3.0 3.3 V 70 oC FVCC, MVCC, PLL (Phase-Locked Loop) and FPM (Frequency Pre-multiplier) Supply Voltage8 non-overdrive SVCC, UVCC overdrive4 IOQVDD Min 1,2,3 On-device Level Shifter Supply Voltage Fusebox read Supply Voltage9, 10 Fusebox write (program) Supply Voltage11 Operating Ambient Temperature Range12 V 0 Measured at package balls, including peripherals, ARM, and L2 cache supplies (QVCC, QVCC1, QVCC4, respectively). The core voltage must be higher than 1.38V to avoid corrupted data during transfers from the USB HS. Please refer to Errata file ENGcm02610 ID. If the Core voltage is supplied by the MC13738, it will be 1.6 ± 0.05 V during the power-up sequence. This is allowed. After power-up the voltage should be reduced to avoid operation in overdrive mode. Supply voltage is considered “overdrive” for voltages above 1.47 V. Operation time in overdrive—whether switching or not—must be limited to a cumulative duration of 1.25 years (10,950 hours) or less to sustain the maximum operating voltage without significant device degradation—for example, 25% (average 6 hours out of 24 yours per day) duty cycle for 5-year rated equipment. To tolerate the maximum operating overdrive voltage for 10 years, the device must have a duty cycle of 12.5% or less in overdrive (for example 3 out of 24 hours per day). Below 1.47V, duty cycle restrictions may apply for equipment rated above 5 years. The SR voltage is applied to QVCC, QVCC1, and QVCC4 after the device is placed in SR mode. The Real-Time Clock (RTC) is operational in State Retention (SR) mode. Overshoot and undershoot conditions (transitions above NVCC and below GND) on I/O must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 13 Electrical Characteristics 7 Supply voltage is considered “overdrive” for voltages above 3.1 V. Operation time in overdrive—whether switching or not—must be limited to a cumulative duration of 1 year (8,760 hours) or less to sustain the maximum operating voltage without significant device degradation—for example, 20% (average 4.8 hours out of 24 hours per day) duty cycle for 5-year rated equipment. Operation at 3.3 V that exceeds a cumulative 3,504 hours may cause non-operation whenever supply voltage is reduced to 1.8 V; degradation may render the device too slow or inoperable. Below 3.1 V, duty cycle restrictions may apply for equipment rated above 5 years. 8 For normal operating conditions, PLLs’ and core supplies must maintain the following relation: PLL ≥ Core – 100 mV. In other words, for a 1.6 V core supply, PLL supplies must be set to 1.5 V or higher. This restriction is no longer necessary on mask set M91E. PLL supplies may be set independently of core supply. PLL voltage must not be altered after power up, otherwise the PLL will be unstable and lose lock. To minimize inducing noise on the PLL supply line, source the voltage from a low-noise, dedicated supply. PLL parameters in Table 31, "DPLL Specifications," on page 37, are guaranteed over the entire specified voltage range. 9 Fusebox read supply voltage applies to silicon Revisions 1.2 and previous. 10 In read mode, FUSE_VDD can be floated or grounded for mask set M91E (silicon Revision 2.0). 11 Fuses might be inadvertently blown if written to while the voltage is below this minimum. 12 The temperature range given is for the consumer version. Please refer to Table 1 for extended temperature range offerings and the associated part numbers. Table 9. Specific Operating Ranges for Silicon Revision 2.0 Symbol FUSE_VDD 1 2 Parameter Fusebox read Supply Voltage1 Fusebox write (program) Supply Voltage2 Min Max Units — — V 3.0 3.3 V In read mode, FUSE_VDD should be floated or grounded. Fuses might be inadvertently blown if written to while the voltage is below the minimum. Table 10 provides information for interface frequency limits. For more details about clocks characteristics, see Section 4.3.8, “DPLL Electrical Specifications,” and Section 4.3.3, “Clock Amplifier Module (CAMP) Electrical Characteristics.” Table 10. Interface Frequency ID 1 2 3 Parameter Symbol Min Typ Max Units fJTAG DC 5 10 MHz 1 fCKIL 32 32.768 38.4 kHz Frequency2 fCKIH 15 26 75 MHz JTAG TCK Frequency CKIL Frequency CKIH 1 CKIL must be driven by an external clock source to ensure proper start-up and operation of the device. CKIL is needed to clock the internal reset synchronizer, the watchdog, and the real-time clock. 2 DPTC functionality, specifically the voltage/frequency relation table, is dependent on CKIH frequency. At the time of publication, standard tables used by Freescale OSs provided for a CKIH frequency of 26 MHz only. Any deviation from this frequency requires an update to the OS. For more details, refer to the particular OS user's guide documentation. Table 11 shows the fusebox supply current parameters. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 14 Freescale Semiconductor Electrical Characteristics Table 11. Fusebox Supply Current Parameters Ref. Num 1 2 Description 1 1 eFuse Program Current. Current to program one eFuse bit: efuse_pgm = 3.0 V 2 eFuse Read Current2 Current to read an 8-bit eFuse word vdd_fusebox = 1.875 V Symbol Minimum Typical Maximum Units Iprogram — 35 60 mA Iread — 5 8 mA The current Iprogram is during program time (tprogram). The current Iread is present for approximately 50 ns of the read access to the 8-bit word, and only applies to Silicon Rev. 1.2 and previous. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 15 Electrical Characteristics 4.1.1 Supply Current Specifications Table 12 shows the core current consumption for 0°C to 70°C for Silicon Revision 1.2 and previous for the MCIMX31. Table 12. Current Consumption for 0°C to 70°C1, 2 for Silicon Revision 1.2 and Previous Mode Conditions State • QVCC and QVCC1 = 0.95 V Retention • L2 caches are power gated (QVCC4 = 0 V) • All PLLs are off, VCC = 1.4 V • ARM is in well bias • FPM is off • 32 kHz input is on • CKIH input is off • CAMP is off • TCK input is off • All modules are off • No external resistive loads • RNGA oscillator is off Wait 1 2 • • • • • • • • • • • • QVCC,QVCC1, and QVCC4 = 1.22 V ARM is in wait for interrupt mode MAX is active L2 cache is stopped but powered MCU PLL is on (532 MHz), VCC = 1.4 V USB PLL and SPLL are off, VCC = 1.4 V FPM is on CKIH input is on CAMP is on 32 kHz input is on All clocks are gated off All modules are off (by programming CGR[2:0] registers) • RNGA oscillator is off • No external resistive loads QVCC (Peripheral) QVCC1 (ARM) QVCC4 (L2) FVCC + MVCC + SVCC + UVCC Unit (PLL) Typ Max Typ Max Typ Max Typ Max 0.80 — 0.50 — — — 0.04 — mA 6.00 — 3.00 — 0.04 — 3.50 — mA Typical column: TA = 25°C Maximum column: TA = 70°C MCIMX31/MCIMX31L Technical Data, Rev. 4.1 16 Freescale Semiconductor Electrical Characteristics Table 13 shows the core current consumption for –40°C to 85°C for Silicon Revision 2.0 for the MCIMX31. Table 13. Current Consumption for –40°C to 85°C1, 2 for Silicon Revision 2.0 Mode Deep Sleep Conditions • QVCC = 0.95 V • ARM and L2 caches are power gated (QVCC1 = QVCC4 = 0 V) • All PLLs are off, VCC = 1.4 V • ARM is in well bias • FPM is off • 32 kHz input is on • CKIH input is off • CAMP is off • TCK input is off • All modules are off • No external resistive loads • RNGA oscillator is off State • QVCC and QVCC1 = 0.95 V Retention • L2 caches are power gated (QVCC4 = 0 V) • All PLLs are off, VCC = 1.4 V • ARM is in well bias • FPM is off • 32 kHz input is on • CKIH input is off • CAMP is off • TCK input is off • All modules are off • No external resistive loads • RNGA oscillator is off Wait 1 2 • • • • • • • • • • • • QVCC,QVCC1, and QVCC4 = 1.22 V ARM is in wait for interrupt mode MAX is active L2 cache is stopped but powered MCU PLL is on (532 MHz), VCC = 1.4 V USB PLL and SPLL are off, VCC = 1.4 V FPM is on CKIH input is on CAMP is on 32 kHz input is on All clocks are gated off All modules are off (by programming CGR[2:0] registers) • RNGA oscillator is off • No external resistive loads QVCC (Peripheral) QVCC1 (ARM) QVCC4 (L2) FVCC + MVCC + SVCC + UVCC Unit (PLL) Typ Max Typ Max Typ Max Typ Max 0.16 5.50 — — — — 0.02 0.10 mA 0.16 5.50 0.07 2.20 — — 0.02 0.10 mA 6.00 15.00 2.20 25.00 3.60 4.40 mA 0.03 0.29 Typical column: TA = 25°C Maximum column: TA = 85°C MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 17 Electrical Characteristics Table 14 shows the core current consumption for 0°C to 70°C for Silicon Revision 2.0 for the MCIMX31. Table 14. Current Consumption for 0°C to 70°C1, 2 for Silicon Revision 2.0 Mode Deep Sleep Conditions • QVCC = 0.95 V • ARM and L2 caches are power gated (QVCC1 2= QVCC4 = 0 V) • All PLLs are off, VCC = 1.4 V • ARM is in well bias • FPM is off • 32 kHz input is on • CKIH input is off • CAMP is off • TCK input is off • All modules are off • No external resistive loads • RNGA oscillator is off State • QVCC and QVCC1 = 0.95 V Retention • L2 caches are power gated (QVCC4 = 0 V) • All PLLs are off, VCC = 1.4 V • ARM is in well bias • FPM is off • 32 kHz input is on • CKIH input is off • CAMP is off • TCK input is off • All modules are off • No external resistive loads • RNGA oscillator is off Wait 1 2 • • • • • • • • • • • • QVCC,QVCC1, and QVCC4 = 1.22 V ARM is in wait for interrupt mode MAX is active L2 cache is stopped but powered MCU PLL is on (532 MHz), VCC = 1.4 V USB PLL and SPLL are off, VCC = 1.4 V FPM is on CKIH input is on CAMP is on 32 kHz input is on All clocks are gated off All modules are off (by programming CGR[2:0] registers) • RNGA oscillator is off • No external resistive loads QVCC (Peripheral) QVCC1 (ARM) QVCC4 (L2) FVCC, +MVCC, +SVCC, +UVCC Unit (PLL) Typ Max Typ Max Typ Max Typ Max 0.16 2.50 — — — — 0.02 0.10 mA 0.16 2.50 0.07 1.60 — — 0.02 0.10 mA 6.00 13.00 2.20 16.00 0.03 0.17 3.60 4.40 mA Typical column: TA = 25°C Maximum column: TA = 70°C MCIMX31/MCIMX31L Technical Data, Rev. 4.1 18 Freescale Semiconductor Electrical Characteristics 4.2 Supply Power-Up/Power-Down Requirements and Restrictions Any MCIMX31 board design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the device. Any deviation from these sequences may result in any or all of the following situations: • Cause excessive current during power up phase • Prevent the device from booting • Cause irreversible damage to the MCIMX31 (worst-case scenario) 4.2.1 Powering Up The Power On Reset (POR) pin must be kept asserted (low) throughout the power up sequence. Power up logic must guarantee that all power sources reach their target values prior to the release (de-assertion) of POR. Figure 2 shows the power-up sequence for silicon Revisions 1.2 and previous. Figure 3 and Figure 4 show the power-up sequence for silicon Revision 2.0. NOTE Stages need to be performed in the order shown; however, within each stage, supplies can be powered up in any order. For example, supplies IOQVDD, NVCC1, and NVCC3 through NVCC10 do not need to be powered up in the order shown. CAUTION NVCC6 and NVCC9 must be at the same voltage potential. These supplies are connected together on-chip to optimize ESD damage immunity. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 19 Electrical Characteristics Hold POR Asserted Notes: 1 1 2 QVCC, QVCC1, QVCC4 3 1 The board design must guarantee that supplies reach 90% level before transition to the next state, using Power Management IC or other means. The NVCC1 supply must not precede IOQVDD by more than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD is powered up first, there are no restrictions. It is allowable for FVCC, MVCC, SVCC, and UVCC to be up after FUSE_VDD. 1, 2 IOQVDD, NVCC1, NVCC3–10 NVCC2, NVCC21, NVCC22 FUSE_VDD 1, 3 1 FVCC, MVCC, 1 SVCC, UVCC Release POR Figure 2. Power-Up Sequence for Silicon Revisions 1.2 and Previous 4.2.1.1 Power-Up Sequence for Silicon Revision 2 Silicon revision 2.0 offers two options for power-up sequencing. Option 1 is backwards compatible with silicon revision 1.2 and earlier versions of the IC. It should be noted that using option 1 on silicon Rev. 2.0 introduces a slight increase in current drain on IOQVDD when IOQVDD is raised before NVCC21. The expected resulting increase is in the range of 3 mA to 5 mA, which does not pose a risk to the IC. Option 2 is an alternative power-up sequence that allows the powering up of NVCC2, NVCC21, NVCC22 with IOQVDD, NVCC1, and NVCC3-10 without producing a current drain increase on IOQVDD. These two power-up options on the 2.0 silicon allow the user to select the optimum power-up sequence for their application. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 20 Freescale Semiconductor Electrical Characteristics Notes: 1 Hold POR Asserted 2 QVCC, QVCC1, QVCC4 1 3 1, 2 IOQVDD, NVCC1, NVCC3–10 4 NVCC2, NVCC21, NVCC22 1, 3, 5 1,3 FVCC, MVCC, SVCC, UVCC 5 4 The board design must guarantee that supplies reach 90% level before transition to the next state, using Power Management IC or other means. The NVCC1 supply must not precede IOQVDD by more than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD is powered up first, there are no restrictions. The parallel paths in the flow indicate that supply group NVCC2, NVCC21, and NVCC22, and supply group FVCC, MVCC, SVCC, and UVCC ramp-ups are independent. Note that this power-up sequence is backward compatible to Silicon Revs. 1.15 and 1.2, because NVCC2x ramp-up proceeding PLL supplies is allowed. Unlike the power-up sequence for Silicon Revision 1.2, FUSE_VDD should not be driven on power-up for Silicon Revision 2.0. This supply is dedicated for fuse burning (programming), and should not be driven upon boot-up. Raising IOQVDD before NVCC21 produces a slight increase in current drain on IOQVDD of approximately 3–5 mA. The current increase will not damage the IC. Refer to Errata ID TLSbo91750 for details. Release POR Figure 3. Option 1 Power-Up Sequence (Silicon Revision 2.0) Notes: 1 Hold POR Asserted 2 QVCC, QVCC1, QVCC4 1 3 1, 2,3 IOQVDD, NVCC1, NVCC3–10, NVCC2, NVCC21, NVCC22 4 The board design must guarantee that supplies reach 90% level before transition to the next state, using Power Management IC or other means. The NVCC1 supply must not precede IOQVDD by more than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD is powered up first, there are no restrictions. Raising NVCC2, NVCC21, and NVCC22 at the same time as IOQVDD does not produce the slight increase in current drain on IOQVDD (as described in Figure 3, Note 5). Unlike the power-up sequence for Silicon Revision 1.2, FUSE_VDD should not be driven on power-up for Silicon Revision 2.0. This supply is dedicated for fuse burning (programming), and should not be driven upon boot-up. 1 FVCC, MVCC, SVCC, UVCC 4 Release POR Figure 4. Option 2 Power-Up Sequence (Silicon Revision 2.0) MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 21 Electrical Characteristics 4.2.2 Powering Down The power-down sequence prior to silicon Revision 2.0 should be completed as follows: 1. Lower the FUSE_VDD supply (when in write mode). 2. Lower the remaining supplies. For silicon revisions beginning with Revision 2.0 there is no special requirements for power down sequence. 4.3 Module-Level Electrical Specifications This section contains the MCIMX31 electrical information including timing specifications, arranged in alphabetical order by module name. 4.3.1 I/O Pad (PADIO) Electrical Specifications This section specifies the AC/DC characterization of functional I/O of the MCIMX31. There are two main types of I/O: regular and DDR. In this document, the “Regular” type is referred to as GPIO. 4.3.1.1 DC Electrical Characteristics The MCIMX31 I/O parameters appear in Table 15 for GPIO. See Table 8 for temperature and supply voltage ranges. NOTE The term NVCC in this section refers to the associated supply rail of an input or output. The association is shown in the Signal Multiplexing chapter of the reference manual. NVCC for Table 15 refers to NVCC1 and NVCC3–10; QVCC refers to QVCC, QVCC1, and QVCC4. Table 15. GPIO DC Electrical Parameters Parameter High-level output voltage Low-level output voltage Symbol Test Conditions Min Typ Max Units VOH IOH = –1 mA NVCC –0.15 — — V IOH = specified Drive 0.8*NVCC — — V IOL = 1 mA — — 0.15 V IOL = specified Drive — — 0.2*NVCC V VOH =0.8*NVCC Std Drive High Drive Max Drive — — mA –2 –4 –8 VOH =0.8*NVCC Std Drive High Drive Max Drive — — mA –4 –6 –8 VOL High-level output current, slow slew rate High-level output current, fast slew rate IOH_S IOH_F MCIMX31/MCIMX31L Technical Data, Rev. 4.1 22 Freescale Semiconductor Electrical Characteristics Table 15. GPIO DC Electrical Parameters (continued) Parameter Low-level output current, slow slew rate Low-level output current, fast slew rate Symbol Test Conditions Min IOL_S VOL =0.2*NVCC Std Drive High Drive Max Drive 2 4 8 VOL =0.2*NVCC Std Drive High Drive Max Drive 4 6 8 IOL_F Typ Max Units — — mA — — mA High-Level DC input voltage VIH — 0.7*NVCC — NVCC V Low-Level DC input voltage VIL — 0 — 0.3*QVCC V Input Hysteresis VHYS Hysteresis enabled 0.25 — — V Schmitt trigger VT+ VT + Hysteresis enabled 0.5*QVCC — — V Schmitt trigger VT– VT – Hysteresis enabled — — 0.5*QVCC V Pull-up resistor (100 kΩ PU) RPU — — 100 — Pull-down resistor (100 kΩ PD) RPD — — 100 — Input current (no PU/PD) IIN VI = NVCC or GND — — ±1 μA Input current (100 kΩ PU) IIN VI = 0 VI = NVCC — — 25 0.1 μA μA Input current (100 kΩ PD) IIN VI = 0 VI = NVCC — — 0.25 28 μA μA Tri-state leakage current IOZ VI = NVCC or GND I/O = High Z — — ±2 μA kΩ The MCIMX31 I/O parameters appear in Table 16 for DDR (Double Data Rate). See Table 8, "Operating Ranges," on page 13 for temperature and supply voltage ranges. NOTE NVCC for Table 16 refers to NVCC2, NVCC21, and NVCC22. Table 16. DDR (Double Data Rate) I/O DC Electrical Parameters Parameter High-level output voltage Low-level output voltage High-level output current Symbol Test Conditions Min Typ Max Units VOH IOH = –1 mA NVCC –0.12 — — V IOH = specified Drive 0.8*NVCC — — V IOL = 1 mA — — 0.08 V IOL = specified Drive — — 0.2*NVCC V VOH =0.8*NVCC Std Drive High Drive Max Drive DDR Drive1 — — mA –3.6 –7.2 –10.8 –14.4 VOL IOH MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 23 Electrical Characteristics Table 16. DDR (Double Data Rate) I/O DC Electrical Parameters (continued) Parameter Low-level output current Symbol Test Conditions Min IOL VOL=0.2*NVCC Std Drive High Drive Max Drive DDR Drive1 3.6 7.2 10.8 14.4 Typ Max Units — — mA High-Level DC input voltage VIH — 0.7*NVCC Low-Level DC input voltage VIL — –0.3 0 0.3*NVCC V Tri-state leakage current IOZ VI = NVCC or GND I/O = High Z — — ±2 μA 1 NVCC NVCC+0.3 V Use of DDR Drive can result in excessive overshoot and ringing. 4.3.2 AC Electrical Characteristics Figure 5 depicts the load circuit for outputs. Figure 6 depicts the output transition time waveform. The range of operating conditions appears in Table 17 for slow general I/O, Table 18 for fast general I/O, and Table 19 for DDR I/O (unless otherwise noted). From Output Under Test Test Point CL CL includes package, probe and fixture capacitance Figure 5. Load Circuit for Output NVCC 80% 80% 20% 20% Output (at I/O) 0V PA1 PA1 Figure 6. Output Transition Time Waveform Table 17. AC Electrical Characteristics of Slow1 General I/O ID PA1 1 Parameter Symbol Test Condition Min Typ Max Units Output Transition Times (Max Drive) tpr 25 pF 50 pF 0.92 1.5 1.95 2.98 3.17 4.75 ns Output Transition Times (High Drive) tpr 25 pF 50 pF 1.52 2.75 — 4.81 8.42 ns Output Transition Times (Std Drive) tpr 25 pF 50 pF 2.79 5.39 — 8.56 16.43 ns Fast/slow characteristic is selected per GPIO (where available) by “slew rate” control. See reference manual. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 24 Freescale Semiconductor Electrical Characteristics Table 18. AC Electrical Characteristics of Fast1 General I/O 2 ID PA1 1 Parameter Symbol Test Condition Min Typ Max Units Output Transition Times (Max Drive) tpr 25 pF 50 pF 0.68 1.34 1.33 2.6 2.07 4.06 ns Output Transition Times (High Drive) tpr 25 pF 50 pF .91 1.79 1.77 3.47 2.74 5.41 ns Output Transition Times (Std Drive) tpr 25 pF 50 pF 1.36 2.68 2.64 5.19 4.12 8.11 ns Fast/slow characteristic is selected per GPIO (where available) by “slew rate” control. See reference manual. Use of GPIO in fast mode with the associated NVCC > 1.95 V can result in excessive overshoot and ringing. 2 Table 19. AC Electrical Characteristics of DDR I/O ID PA1 1 Parameter Symbol Test Condition Min Typ Max Units Output Transition Times (DDR Drive)1 tpr 25 pF 50 pF 0.51 0.97 0.82 1.58 1.28 2.46 ns Output Transition Times (Max Drive) tpr 25 pF 50 pF 0.67 1.29 1.08 2.1 1.69 3.27 ns Output Transition Times (High Drive) tpr 25 pF 50 pF .99 1.93 1.61 3.13 2.51 4.89 ns Output Transition Times (Std Drive) tpr 25 pF 50 pF 1.96 3.82 3.19 6.24 4.99 9.73 ns Use of DDR Drive can result in excessive overshoot and ringing. 4.3.3 Clock Amplifier Module (CAMP) Electrical Characteristics This section outlines the Clock Amplifier Module (CAMP) specific electrical characteristics. Table 20 shows clock amplifier electrical characteristics. Table 20. Clock Amplifier Electrical Characteristics for CKIH Input Parameter Min Typ Max Units Input Frequency 15 — 75 MHz VIL (for square wave input) 0 — 0.3 V VIH (for square wave input) (VDD 1– 0.25) — 3 V — VDD Vp-p 50 55 % Sinusoidal Input Amplitude Duty Cycle 1 2 0.4 45 2 VDD is the supply voltage of CAMP. See reference manual. This value of the sinusoidal input will be measured through characterization. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 25 Electrical Characteristics 4.3.4 1-Wire Electrical Specifications Figure 7 depicts the RPP timing, and Table 21 lists the RPP timing parameters. OWIRE Tx “Reset Pulse” DS2502 Tx “Presence Pulse” OW2 1-Wire bus (BATT_LINE) OW3 OW1 OW4 Figure 7. Reset and Presence Pulses (RPP) Timing Diagram Table 21. RPP Sequence Delay Comparisons Timing Parameters ID Parameters Symbol Min Typ Max Units OW1 Reset Time Low tRSTL 480 511 — µs OW2 Presence Detect High tPDH 15 — 60 µs OW3 Presence Detect Low tPDL 60 — 240 µs OW4 Reset Time High tRSTH 480 512 — µs Figure 8 depicts Write 0 Sequence timing, and Table 22 lists the timing parameters. OW6 1-Wire bus (BATT_LINE) OW5 Figure 8. Write 0 Sequence Timing Diagram Table 22. WR0 Sequence Timing Parameters ID Parameter OW5 Write 0 Low Time OW6 Transmission Time Slot Symbol Min Typ Max Units tWR0_low 60 100 120 µs tSLOT OW5 117 120 µs Figure 9 depicts Write 1 Sequence timing, Figure 10 depicts the Read Sequence timing, and Table 23 lists the timing parameters. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 26 Freescale Semiconductor Electrical Characteristics OW8 1-Wire bus (BATT_LINE) OW7 Figure 9. Write 1 Sequence Timing Diagram OW8 1-Wire bus (BATT_LINE) OW7 OW9 Figure 10. Read Sequence Timing Diagram Table 23. WR1/RD Timing Parameters ID 4.3.5 Parameter Symbol Min Typ Max Units OW7 Write 1 / Read Low Time tLOW1 1 5 15 µs OW8 Transmission Time Slot tSLOT 60 117 120 µs OW9 Release Time tRELEASE 15 — 45 µs ATA Electrical Specifications (ATA Bus, Bus Buffers) This section discusses ATA parameters. For a detailed description, refer to the ATA specification. The user needs to use level shifters for 3.3 Volt or 5.0 Volt compatibility on the ATA interface. The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode operation is needed, this may not be compatible with bus buffers. Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus. According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals. When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 27 Electrical Characteristics 4.3.5.1 Timing Parameters In the timing equations, some timing parameters are used. These parameters depend on the implementation of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 24 shows ATA timing parameters. Table 24. ATA Timing Parameters Name T ti_ds ti_dh Bus clock period (ipg_clk_ata) peripheral clock frequency Set-up time ata_data to ata_iordy edge (UDMA-in only) UDMA0 UDMA1 UDMA2, UDMA3 UDMA4 UDMA5 15 ns 10 ns 7 ns 5 ns 4 ns Hold time ata_iordy edge to ata_data (UDMA-in only) UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 UDMA5 5.0 ns 4.6 ns tco Propagation delay bus clock L-to-H to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en 12.0 ns tsu Set-up time ata_data to bus clock L-to-H 8.5 ns tsui Set-up time ata_iordy to bus clock H-to-L 8.5 ns thi Hold time ata_iordy to bus clock H to L 2.5 ns tskew1 Max difference in propagation delay bus clock L-to-H to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en 7 ns tskew2 Max difference in buffer propagation delay for any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en transceiver tskew3 Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read) transceiver Max buffer propagation delay transceiver tbuf 1 Value/ Contributing Factor1 Description tcable1 Cable propagation delay for ata_data cable tcable2 Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack cable tskew4 Max difference in cable propagation delay between ata_iordy and ata_data (read) cable tskew5 Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) cable tskew6 Max difference in cable propagation delay without accounting for ground bounce cable Values provided where applicable. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 28 Freescale Semiconductor Electrical Characteristics 4.3.5.2 PIO Mode Timing Figure 11 shows timing for PIO read, and Table 25 lists the timing parameters for PIO read. Figure 11. PIO Read Timing Diagram Table 25. PIO Read Timing Parameters ATA Parameter Parameter from Figure 11 Value Controlling Variable t1 t1 t1 (min) = time_1 * T – (tskew1 + tskew2 + tskew5) time_1 t2 t2r t2 min) = time_2r * T – (tskew1 + tskew2 + tskew5) time_2r t9 t9 t9 (min) = time_9 * T – (tskew1 + tskew2 + tskew6) time_3 t5 t5 t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 If not met, increase time_2 t6 t6 0 tA tA tA (min) = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf) trd trd1 t0 — — trd1 (max) = (–trd) + (tskew3 + tskew4) trd1 (min) = (time_pio_rdx – 0.5)*T – (tsu + thi) (time_pio_rdx – 0.5) * T > tsu + thi + tskew3 + tskew4 t0 (min) = (time_1 + time_2 + time_9) * T time_ax time_pio_rdx time_1, time_2r, time_9 Figure 12 shows timing for PIO write, and Table 26 lists the timing parameters for PIO write. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 29 Electrical Characteristics Figure 12. Multiword DMA (MDMA) Timing Table 26. PIO Write Timing Parameters ATA Parameter Parameter from Figure 12 Controlling Variable Value t1 t1 t1 (min) = time_1 * T – (tskew1 + tskew2 + tskew5) time_1 t2 t2w t9 t9 t9 (min) = time_9 * T – (tskew1 + tskew2 + tskew6) t3 — t3 (min) = (time_2w – time_on)* T – (tskew1 + tskew2 +tskew5) t4 t4 t4 (min) = time_4 * T – tskew1 time_4 tA tA tA = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf) time_ax t0 — t0(min) = (time_1 + time_2 + time_9) * T — — Avoid bus contention when switching buffer on by making ton long enough. — — — Avoid bus contention when switching buffer off by making toff long enough. — t2 (min) = time_2w * T – (tskew1 + tskew2 + tskew5) time_2w time_9 If not met, increase time_2w time_1, time_2r, time_9 Figure 13 shows timing for MDMA read, Figure 14 shows timing for MDMA write, and Table 27 lists the timing parameters for MDMA read and write. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 30 Freescale Semiconductor Electrical Characteristics Figure 13. MDMA Read Timing Diagram Figure 14. MDMA Write Timing Diagram Table 27. MDMA Read and Write Timing Parameters ATA Parameter Parameter from Figure 13, Figure 14 tm, ti tm tm (min) = ti (min) = time_m * T – (tskew1 + tskew2 + tskew5) time_m td td, td1 td1.(min) = td (min) = time_d * T – (tskew1 + tskew2 + tskew6) time_d tk tk tk.(min) = time_k * T – (tskew1 + tskew2 + tskew6) time_k t0 — t0 (min) = (time_d + time_k) * T tg(read) tgr tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr.(min-drive) = td – te(drive) tf(read) tfr tfr (min-drive) = 0 tg(write) — tg (min-write) = time_d * T – (tskew1 + tskew2 + tskew5) time_d tf(write) — tf (min-write) = time_k * T – (tskew1 + tskew2 + tskew6) time_k tL — tL (max) = (time_d + time_k–2)*T – (tsu + tco + 2*tbuf + 2*tcable2) tn, tj tkjn tn= tj= tkjn = (max(time_k,. time_jn) * T – (tskew1 + tskew2 + tskew6) — ton toff ton = time_on * T – tskew1 toff = time_off * T – tskew1 Value Controlling Variable time_d, time_k time_d — time_d, time_k time_jn — MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 31 Electrical Characteristics 4.3.5.3 UDMA In Timing Figure 15 shows timing when the UDMA in transfer starts, Figure 16 shows timing when the UDMA in host terminates transfer, Figure 17 shows timing when the UDMA in device terminates transfer, and Table 28 lists the timing parameters for UDMA in burst. Figure 15. UDMA In Transfer Starts Timing Diagram Figure 16. UDMA In Host Terminates Transfer Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 32 Freescale Semiconductor Electrical Characteristics Figure 17. UDMA In Device Terminates Transfer Timing Diagram Table 28. UDMA In Burst Timing Parameters ATA Parameter Parameter from Figure 15, Figure 16, Figure 17 tack tack tack (min) = (time_ack * T) – (tskew1 + tskew2) time_ack tenv tenv tenv (min) = (time_env * T) – (tskew1 + tskew2) tenv (max) = (time_env * T) + (tskew1 + tskew2) time_env tds tds1 tds – (tskew3) – ti_ds > 0 tdh tdh1 tdh – (tskew3) – ti_dh > 0 tcyc tc1 (tcyc – tskew) > T trp trp trp (min) = time_rp * T – (tskew1 + tskew2 + tskew6) time_rp time_rp 1 Description Controlling Variable tskew3, ti_ds, ti_dh should be low enough T big enough — tx1 (time_rp * T) – (tco + tsu + 3T + 2 *tbuf + 2*tcable2) > trfs (drive) tmli tmli1 tmli1 (min) = (time_mlix + 0.4) * T time_mlix tzah tzah tzah (min) = (time_zah + 0.4) * T time_zah tdzfs tdzfs tdzfs = (time_dzfs * T) – (tskew1 + tskew2) time_dzfs tcvh tcvh tcvh = (time_cvh *T) – (tskew1 + tskew2) time_cvh — ton toff ton = time_on * T – tskew1 toff = time_off * T – tskew1 — 1 There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2. Make ton and toff big enough to avoid bus contention MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 33 Electrical Characteristics 4.3.5.4 UDMA Out Timing Figure 18 shows timing when the UDMA out transfer starts, Figure 19 shows timing when the UDMA out host terminates transfer, Figure 20 shows timing when the UDMA out device terminates transfer, and Table 29 lists the timing parameters for UDMA out burst. Figure 18. UDMA Out Transfer Starts Timing Diagram Figure 19. UDMA Out Host Terminates Transfer Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 34 Freescale Semiconductor Electrical Characteristics Figure 20. UDMA Out Device Terminates Transfer Timing Diagram Table 29. UDMA Out Burst Timing Parameters ATA Parameter Parameter from Figure 18, Figure 19, Figure 20 tack tack tack (min) = (time_ack * T) – (tskew1 + tskew2) time_ack tenv tenv tenv (min) = (time_env * T) – (tskew1 + tskew2) tenv (max) = (time_env * T) + (tskew1 + tskew2) time_env tdvs tdvs tdvs = (time_dvs * T) – (tskew1 + tskew2) time_dvs tdvh tdvh tdvs = (time_dvh * T) – (tskew1 + tskew2) time_dvh tcyc tcyc tcyc = time_cyc * T – (tskew1 + tskew2) time_cyc t2cyc — t2cyc = time_cyc * 2 * T time_cyc trfs1 trfs trfs = 1.6 * T + tsui + tco + tbuf + tbuf — tdzfs tss tss tmli tdzfs_mli tli Value tdzfs = time_dzfs * T – (tskew1) tss = time_ss * T – (tskew1 + tskew2) Controlling Variable — time_dzfs time_ss tdzfs_mli =max (time_dzfs, time_mli) * T – (tskew1 + tskew2) — tli1 tli1 > 0 — tli tli2 tli2 > 0 — tli tli3 tli3 > 0 — tcvh tcvh tcvh = (time_cvh *T) – (tskew1 + tskew2) — ton toff ton = time_on * T – tskew1 toff = time_off * T – tskew1 time_cvh — MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 35 Electrical Characteristics 4.3.6 AUDMUX Electrical Specifications The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is hence governed by the SSI module. Please refer to their respective electrical specifications. 4.3.7 CSPI Electrical Specifications This section describes the electrical information of the CSPI. 4.3.7.1 CSPI Timing Figure 21 and Figure 22 depict the master mode and slave mode timings of CSPI, and Table 30 lists the timing parameters. SPI_RDY CS11 SSx CS1 CS3 CS2 CS6 CS5 CS3 CS4 SCLK CS2 CS7 CS8 MOSI CS9 CS10 MISO Figure 21. CSPI Master Mode Timing Diagram SSx CS1 CS3 CS2 CS6 CS5 CS3 CS4 SCLK CS7 CS8 CS2 MISO CS9 CS10 MOSI Figure 22. CSPI Slave Mode Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 36 Freescale Semiconductor Electrical Characteristics Table 30. CSPI Interface Timing Parameters ID 1 Parameter Symbol Min Max Units CS1 SCLK Cycle Time tclk 60 — ns CS2 SCLK High or Low Time tSW 30 — ns CS3 SCLK Rise or Fall tRISE/FALL — 7.6 ns CS4 SSx pulse width tCSLH 25 — ns CS5 SSx Lead Time (CS setup time) tSCS 25 — ns CS6 SSx Lag Time (CS hold time) tHCS 25 — ns CS7 Data Out Setup Time tSmosi 5 — ns CS8 Data Out Hold Time tHmosi 5 — ns CS9 Data In Setup Time tSmiso 6 — ns CS10 Data In Hold Time tHmiso 5 — ns CS11 SPI_RDY Setup Time1 tSRDY — — ns SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. 4.3.8 DPLL Electrical Specifications The three PLL’s of the MCIMX31 (MCU, USB, and Serial PLL) are all based on same DPLL design. The characteristics provided herein apply to all of them, except where noted explicitly. The PLL characteristics are provided based on measurements done for both sources—external clock source (CKIH), and FPM (Frequency Pre-Multiplier) source. 4.3.8.1 Electrical Specifications Table 31 lists the DPLL specification. Table 31. DPLL Specifications Parameter Min Typ Max Unit Comments CKIH frequency 15 261 752 MHz — CKIL frequency (Frequency Pre-multiplier (FPM) enable mode) — 32; 32.768, 38.4 — kHz FPM lock time ≈ 480 µs. Predivision factor (PD bits) 1 — 16 PLL reference frequency range after Predivider 15 — 35 MHz 15 ≤ CKIH frequency/PD ≤ 35 MHz 15 ≤ FPM output/PD ≤ 35 MHz 532 240 MHz — — PLL output frequency range: MPLL and SPLL 52 UPLL 190 — — Maximum allowed reference clock phase noise. — — ± 100 ps Frequency lock time (FOL mode or non-integer MF) — — 398 — — Cycles of divided reference clock. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 37 Electrical Characteristics Table 31. DPLL Specifications (continued) Parameter Min Typ Max Unit Comments Phase lock time — — 100 µs Maximum allowed PLL supply voltage ripple — — 25 mV Fmodulation < 50 kHz Maximum allowed PLL supply voltage ripple — — 20 mV 50 kHz < Fmodulation < 300 kHz Maximum allowed PLL supply voltage ripple — — 25 mV Fmodulation > 300 kHz PLL output clock phase jitter — — 5.2 ns Measured on CLKO pin PLL output clock period jitter — — 420 ps Measured on CLKO pin In addition to the frequency 1 The user or board designer must take into account that the use of a frequency other than 26 MHz would require adjustment to the DPTC–DVFS table, which is incorporated into operating system code. 2 The PLL reference frequency must be ≤ 35 MHz. Therefore, for frequencies between 35 MHz and 70 MHz, program the predivider to divide by 2 or more. If the CKIH frequency is above 70 MHz, program the predivider to 3 or more. For PD bit description, see the reference manual. 4.3.9 EMI Electrical Specifications This section provides electrical parametrics and timings for EMI module. 4.3.9.1 NAND Flash Controller Interface (NFC) The NFC supports normal timing mode, using two flash clock cycles for one access of RE and WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 23, Figure 24, Figure 25, and Figure 26 depict the relative timing requirements among different signals of the NFC at module level, for normal mode, and Table 32 lists the timing parameters. NFCLE NF2 NF1 NF3 NF4 NFCE NF5 NFWE NF6 NF7 NFALE NF8 NF9 NFIO[7:0] Command Figure 23. Command Latch Cycle Timing DIagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 38 Freescale Semiconductor Electrical Characteristics NFCLE NF1 NF4 NF3 NFCE NF10 NF11 NF5 NFWE NF7 NF6 NFALE NF8 NF9 Address NFIO[7:0] Figure 24. Address Latch Cycle Timing DIagram NFCLE NF1 NF3 NFCE NF10 NF11 NF5 NFWE NF7 NF6 NFALE NF8 NF9 NFIO[15:0] Data to NF Figure 25. Write Data Latch Cycle Timing DIagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 39 Electrical Characteristics NFCLE NFCE NF14 NF15 NF13 NFRE NF17 NF16 NFRB NF12 NFIO[15:0] Data from NF Figure 26. Read Data Latch Cycle Timing DIagram Table 32. NFC Timing Parameters1 ID 1 2 Parameter Symbol Timing T = NFC Clock Cycle2 Example Timing for NFC Clock ≈ 33 MHz T = 30 ns Min Max Min Max Unit NF1 NFCLE Setup Time tCLS T–1.0 ns — 29 — ns NF2 NFCLE Hold Time tCLH T–2.0 ns — 28 — ns NF3 NFCE Setup Time tCS T–1.0 ns — 29 — ns NF4 NFCE Hold Time tCH T–2.0 ns — 28 — ns NF5 NF_WP Pulse Width tWP NF6 NFALE Setup Time tALS T — 30 — ns NF7 NFALE Hold Time tALH T–3.0 ns — 27 — ns NF8 Data Setup Time tDS T — 30 — ns NF9 Data Hold Time tDH T–5.0 ns — 25 — ns T–1.5 ns 28.5 ns NF10 Write Cycle Time tWC 2T 60 ns NF11 NFWE Hold Time tWH T–2.5 ns 27.5 ns NF12 Ready to NFRE Low tRR 6T — 180 — ns NF13 NFRE Pulse Width tRP 1.5T — 45 — ns NF14 READ Cycle Time tRC 2T — 60 — ns NF15 NFRE High Hold Time tREH 0.5T–2.5 ns 12.5 — ns NF16 Data Setup on READ tDSR N/A 10 — ns NF17 Data Hold on READ tDHR N/A 0 — ns The flash clock maximum frequency is 50 MHz. Subject to DPLL jitter specification on Table 31, "DPLL Specifications," on page 37. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 40 Freescale Semiconductor Electrical Characteristics NOTE High is defined as 80% of signal value and low is defined as 20% of signal value. Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is approximately 33 MHz (30 ns). All timings are listed according to this NFC clock frequency (multiples of NFC clock phases), except NF16 and NF17, which are not NFC clock related. 4.3.9.2 Wireless External Interface Module (WEIM) All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising edge or falling edge according to corresponding assertion/negation control fields. Address always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according to control register configuration. Output data begins related to BCLK rising edge except in muxed mode where both rising and falling edge may be used according to control register configuration. Input data, ECB and DTACK all captured according to BCLK rising edge time. Figure 27 depicts the timing of the WEIM module, and Table 33 lists the timing parameters. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 41 Electrical Characteristics WEIM Outputs Timing WE22 WE21 ... BCLK WE23 WE1 WE2 WE3 WE4 WE5 WE6 WE7 WE8 WE9 WE10 WE11 WE12 WE13 WE14 Address CS[x] RW OE EB[x] LBA Output Data WEIM Inputs Timing BCLK WE16 Input Data WE15 WE18 ECB WE17 WE20 DTACK WE19 Figure 27. WEIM Bus Timing Diagram Table 33. WEIM Bus Timing Parameters ID Parameter Min Max Unit WE1 Clock fall to Address Valid –0.5 2.5 ns WE2 Clock rise/fall to Address Invalid –0.5 5 ns WE3 Clock rise/fall to CS[x] Valid –3 3 ns WE4 Clock rise/fall to CS[x] Invalid –3 3 ns WE5 Clock rise/fall to RW Valid –3 3 ns WE6 Clock rise/fall to RW Invalid –3 3 ns WE7 Clock rise/fall to OE Valid –3 3 ns MCIMX31/MCIMX31L Technical Data, Rev. 4.1 42 Freescale Semiconductor Electrical Characteristics Table 33. WEIM Bus Timing Parameters (continued) ID Parameter Min Max Unit WE8 Clock rise/fall to OE Invalid –3 3 ns WE9 Clock rise/fall to EB[x] Valid –3 3 ns WE10 Clock rise/fall to EB[x] Invalid –3 3 ns WE11 Clock rise/fall to LBA Valid –3 3 ns WE12 Clock rise/fall to LBA Invalid –3 3 ns WE13 Clock rise/fall to Output Data Valid –2.5 4 ns WE14 Clock rise to Output Data Invalid –2.5 4 ns WE15 Input Data Valid to Clock rise, FCE=0 FCE=1 8 2.5 — WE16 Clock rise to Input Data Invalid, FCE=0 FCE=1 –2 –2 — WE17 ECB setup time, FCE=0 FCE=1 6.5 3.5 — WE18 ECB hold time, FCE=0 FCE=1 –2 2 — WE19 DTACK setup time1 0 — ns WE20 DTACK hold time1 4.5 — ns WE21 BCLK High Level Width2, 3 — T/2 – 3 ns WE22 BCLK Low Level Width2, 3 — T/2 – 3 ns WE23 BCLK Cycle time2 15 — ns ns ns ns ns 1 Applies to rising edge timing BCLK parameters are being measured from the 50% VDD. 3 The actual cycle time is derived from the AHB bus clock frequency. 2 NOTE High is defined as 80% of signal value and low is defined as 20% of signal value. Test conditions: load capacitance, 25 pF. Recommended drive strength for all controls, address, and BCLK is Max drive. Figure 28, Figure 29, Figure 30, Figure 31, Figure 32, and Figure 33 depict some examples of basic WEIM accesses to external memory devices with the timing parameters mentioned in Table 33 for specific control parameter settings. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 43 Electrical Characteristics BCLK WE2 WE1 V1 Last Valid Address ADDR Next Address WE3 WE4 WE11 WE12 WE7 WE8 WE9 WE10 CS[x] RW LBA OE EB[y] WE16 V1 DATA WE15 Figure 28. Asynchronous Memory Timing Diagram for Read Access—WSC=1 BCLK WE2 WE1 ADDR CS[x] Last Valid Address WE3 WE4 WE5 WE6 RW LBA Next Address V1 WE11 WE12 OE EB[y] WE9 WE10 WE14 DATA V1 WE13 Figure 29. Asynchronous Memory Timing Diagram for Write Access— WSC=1, EBWA=1, EBWN=1, LBN=1 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 44 Freescale Semiconductor Electrical Characteristics BCLK WE1 WE2 ADDR Last Valid Addr Address V1 Address V2 WE4 WE3 CS[x] RW WE11 LBA WE12 WE8 WE7 OE WE10 WE9 EB[y] WE18 WE18 ECB WE17 WE17 WE16 WE16 V1 V1+2 Halfword Halfword DATA WE15 V2 Halfword V2+2 Halfword WE15 Figure 30. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses— WSC=2, SYNC=1, DOL=0 BCLK WE2 WE1 ADDR Last Valid Addr CS[x] RW LBA Address V1 WE3 WE4 WE5 WE6 WE11 WE12 OE EB[y] WE10 WE9 WE18 ECB WE17 WE14 V1+4 V1+8 V1+12 V1 DATA WE13 WE14 WE13 Figure 31. Synchronous Memory TIming Diagram for Burst Write Access— BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 45 Electrical Characteristics BCLK WE1 ADDR/ Last Valid Addr M_DATA CS[x] RW WE14 WE2 Write Data Address V1 WE13 WE3 WE5 WE4 WE6 Write WE11 WE12 LBA OE EB[y] WE9 WE10 Figure 32. Muxed A/D Mode Timing Diagram for Asynchronous Write Access— WSC=7, LBA=1, LBN=1, LAH=1 BCLK WE1 ADDR/ Last Valid Addr M_DATA WE3 CS[x] WE2 Address V1 WE16 Read Data WE15 WE4 RW WE11 WE12 LBA WE7 OE EB[y] WE9 WE8 WE10 Figure 33. Muxed A/D Mode Timing Diagram for Asynchronous Read Access— WSC=7, LBA=1, LBN=1, LAH=1, OEA=7 4.3.9.3 ESDCTL Electrical Specifications Figure 34, Figure 35, Figure 36, Figure 37, Figure 38, and Figure 39 depict the timings pertaining to the ESDCTL module, which interfaces Mobile DDR or SDR SDRAM. Table 34, Table 35, Table 36, Table 37, Table 38, and Table 39 list the timing parameters. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 46 Freescale Semiconductor Electrical Characteristics SD1 SDCLK SDCLK SD2 SD3 SD4 CS SD5 RAS SD4 SD5 SD4 CAS SD4 SD5 SD5 WE SD6 SD7 ADDR ROW/BA COL/BA SD8 SD10 SD9 DQ Data SD4 DQM Note: CKE is high during the read/write cycle. SD5 Figure 34. SDRAM Read Cycle Timing Diagram Table 34. DDR/SDR SDRAM Read Cycle Timing Parameters ID Parameter Symbol Min Max Unit SD1 SDRAM clock high-level width tCH 3.4 4.1 ns SD2 SDRAM clock low-level width tCL 3.4 4.1 ns SD3 SDRAM clock cycle time tCK 7.5 — ns SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.0 — ns SD5 CS, RAS, CAS, WE, DQM, CKE hold time tCMH 1.8 — ns SD6 Address setup time tAS 2.0 — ns SD7 Address hold time tAH 1.8 — ns SD8 SDRAM access time tAC — 6.47 ns MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 47 Electrical Characteristics Table 34. DDR/SDR SDRAM Read Cycle Timing Parameters (continued) ID 1 Parameter Symbol Min Max Unit SD9 Data out hold time1 tOH 1.8 — ns SD10 Active to read/write command period tRC 10 — clock Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see Table 38 and Table 39. NOTE SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz. The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 34 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 48 Freescale Semiconductor Electrical Characteristics SD1 SDCLK SDCLK SD2 SD3 SD4 CS SD5 RAS SD11 SD4 CAS SD5 SD4 SD4 WE SD5 SD5 SD12 SD7 SD6 ADDR BA COL/BA ROW / BA SD13 DQ SD14 DATA DQM Figure 35. SDR SDRAM Write Cycle Timing Diagram Table 35. SDR SDRAM Write Timing Parameters ID Parameter Symbol Min Max Unit SD1 SDRAM clock high-level width tCH 3.4 4.1 ns SD2 SDRAM clock low-level width tCL 3.4 4.1 ns SD3 SDRAM clock cycle time tCK 7.5 — ns SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.0 — ns SD5 CS, RAS, CAS, WE, DQM, CKE hold time tCMH 1.8 — ns SD6 Address setup time tAS 2.0 — ns SD7 Address hold time tAH 1.8 — ns SD11 Precharge cycle period1 tRP 1 4 clock tRCD 1 8 clock SD12 Active to read/write command delay1 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 49 Electrical Characteristics Table 35. SDR SDRAM Write Timing Parameters (continued) ID 1 Parameter Symbol Min Max Unit SD13 Data setup time tDS 2.0 — ns SD14 Data hold time tDH 1.3 — ns SD11 and SD12 are determined by SDRAM controller register settings. NOTE SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 35 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. SD1 SDCLK SDCLK SD2 SD3 CS RAS SD11 CAS SD10 SD10 WE SD7 SD6 ADDR BA ROW/BA Figure 36. SDRAM Refresh Timing Diagram Table 36. SDRAM Refresh Timing Parameters ID Parameter Symbol Min Max Unit SD1 SDRAM clock high-level width tCH 3.4 4.1 ns SD2 SDRAM clock low-level width tCL 3.4 4.1 ns MCIMX31/MCIMX31L Technical Data, Rev. 4.1 50 Freescale Semiconductor Electrical Characteristics Table 36. SDRAM Refresh Timing Parameters (continued) ID 1 Parameter Symbol Min Max Unit SD3 SDRAM clock cycle time tCK 7.5 — ns SD6 Address setup time tAS 1.8 — ns SD7 Address hold time tAH 1.8 — ns SD10 Precharge cycle period1 tRP 1 4 clock SD11 Auto precharge command period1 tRC 2 20 clock SD10 and SD11 are determined by SDRAM controller register settings. NOTE SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 36 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 51 Electrical Characteristics SDCLK CS RAS CAS WE ADDR BA SD16 CKE SD16 Don’t care Figure 37. SDRAM Self-Refresh Cycle Timing Diagram NOTE The clock will continue to run unless both CKEs are low. Then the clock will be stopped in low state. Table 37. SDRAM Self-Refresh Cycle Timing Parameters ID SD16 Parameter CKE output delay time Symbol Min Max Unit tCKS 1.8 — ns MCIMX31/MCIMX31L Technical Data, Rev. 4.1 52 Freescale Semiconductor Electrical Characteristics SDCLK SDCLK SD20 SD19 DQS (output) SD18 SD17 DQ (output) DQM (output) SD17 SD18 Data Data Data Data Data Data Data Data DM DM DM DM DM DM DM DM SD17 SD17 SD18 SD18 Figure 38. Mobile DDR SDRAM Write Cycle Timing Diagram Table 38. Mobile DDR SDRAM Write Cycle Timing Parameters1 ID 1 Parameter Symbol Min Max Unit SD17 DQ and DQM setup time to DQS tDS 0.95 — ns SD18 DQ and DQM hold time to DQS tDH 0.95 — ns SD19 Write cycle DQS falling edge to SDCLK output delay time. tDSS 1.8 — ns SD20 Write cycle DQS falling edge to SDCLK output hold time. tDSH 1.8 — ns Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703. NOTE SDRAM CLK and DQS related parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 38 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 53 Electrical Characteristics SDCLK SDCLK SD23 DQS (input) SD22 SD21 DQ (input) Data Data Data Data Data Data Data Data Figure 39. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram Table 39. Mobile DDR SDRAM Read Cycle Timing Parameters ID Parameter SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS). SD22 DQS DQ HOLD time from DQS SD23 DQS output access time from SDCLK posedge Symbol Min Max Unit tDQSQ — 0.85 ns tQH 2.3 — ns tDQSCK — 6.7 ns NOTE SDRAM CLK and DQS related parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 39 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. 4.3.10 ETM Electrical Specifications ETM is an ARM protocol. The timing specifications in this section are given as a guide for a TPA that supports TRACECLK frequencies up to 133 MHz. Figure 40 depicts the TRACECLK timings of ETM, and Table 40 lists the timing parameters. Figure 40. ETM TRACECLK Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 54 Freescale Semiconductor Electrical Characteristics Table 40. ETM TRACECLK Timing Parameters ID Parameter Min Max Unit Frequency dependent — ns Tcyc Clock period Twl Low pulse width 2 — ns Twh High pulse width 2 — ns Tr Clock and data rise time — 3 ns Tf Clock and data fall time — 3 ns Figure 41 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and Table 41 lists the timing parameters. Figure 41. Trace Data Timing Diagram Table 41. ETM Trace Data Timing Parameters ID 4.3.10.1 Parameter Min Max Unit Ts Data setup 2 — ns Th Data hold 1 — ns Half-Rate Clocking Mode When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and falling edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 41. 4.3.11 FIR Electrical Specifications FIR implements asynchronous infrared protocols (FIR, MIR) that are defined by IrDA® (Infrared Data Association). Refer to http://www.IrDA.org for details on FIR and MIR protocols. 4.3.12 Fusebox Electrical Specifications Table 42. Fusebox Timing Characteristics 1 Ref. Num Description Symbol Minimum Typical Maximum Units 1 Program time for eFuse1 tprogram 125 — — µs The program length is defined by the value defined in the epm_pgm_length[2:0] bits of the IIM module. The value to program is based on a 32 kHz clock source (4 * 1/32 kHz = 125 µs). MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 55 Electrical Characteristics 4.3.13 I2C Electrical Specifications This section describes the electrical information of the I2C Module. 4.3.13.1 I2C Module Timing Figure 42 depicts the timing of I2C module. Table 43 lists the I2C module timing parameters where the I/O supply is 2.7 V. 1 I2CLK IC11 IC10 I2DAT IC2 IC10 START IC7 IC4 IC8 IC11 IC6 IC9 IC3 STOP START START IC5 IC1 Figure 42. I2C Bus Timing Diagram Table 43. I2C Module Timing Parameters—I2C Pin I/O Supply=2.7 V Standard Mode ID Fast Mode Parameter Unit Min Max Min Max IC1 I2CLK cycle time 10 — 2.5 — μs IC2 Hold time (repeated) START condition 4.0 — 0.6 — μs IC3 Set-up time for STOP condition 4.0 — 0.6 — μs IC4 Data hold time 01 3.45 01 0.92 μs IC5 HIGH Period of I2CLK Clock 4.0 — 0.6 — μs IC6 LOW Period of the I2CLK Clock 4.7 — 1.3 — μs IC7 Set-up time for a repeated START condition 4.7 — 0.6 — μs — ns 2 IC8 Data set-up time 250 — 1003 IC9 Bus free time between a STOP and START condition 4.7 — 1.3 IC10 Rise time of both I2DAT and I2CLK signals — 1000 — μs 20+0.1Cb 4 300 ns 4 300 ns 400 pF IC11 Fall time of both I2DAT and I2CLK signals — 300 20+0.1Cb IC12 Capacitive load for each bus line (Cb) — 400 — 1 A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK. 2 The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal. 3 A Fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement of set-up time (ID IC7) of 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal. If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released. 4 Cb = total capacitance of one bus line in pF. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 56 Freescale Semiconductor Electrical Characteristics 4.3.14 IPU—Sensor Interfaces 4.3.14.1 Supported Camera Sensors Table 44 lists the known supported camera sensors at the time of publication. Table 44. Supported Camera Sensors1 Vendor Model Conexant CX11646, CX204902, CX204502 Agilant HDCP–2010, ADCS–10212, ADCS–10212 Toshiba TC90A70 ICMedia ICM202A, ICM1022 iMagic IM8801 Transchip TC5600, TC5600J, TC5640, TC5700, TC6000 Fujitsu MB86S02A Micron MI–SOC–0133 Matsushita MN39980 STMicro W6411, W6500, W65012, W66002, W65522, STV09742 OmniVision OV7620, OV6630 Sharp LZ0P3714 (CCD) Motorola MC30300 (Python)2, SCM200142, SCM201142, SCM221142, SCM200272 National Semiconductor LM96182 1 Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only camera suppliers. 2 These sensors not validated at time of publication. 4.3.14.2 Functional Description There are three timing modes supported by the IPU. 4.3.14.2.1 Pseudo BT.656 Video Mode Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656 standard. This operation mode follows the recommendations of ITU BT.656 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 57 Electrical Characteristics 4.3.14.2.2 Gated Clock Mode The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See Figure 43. Active Line Start of Frame nth frame n+1th frame SENSB_VSYNC SENSB_HSYNC SENSB_PIX_CLK SENSB_DATA[9:0] invalid invalid 1st byte 1st byte Figure 43. Gated Clock Mode Timing Diagram A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the SENSB_VSYNC timing repeats. 4.3.14.2.3 Non-Gated Clock Mode The timing is the same as the gated-clock mode (described in Section 4.3.14.2.2, “Gated Clock Mode”), except for the SENSB_HSYNC signal, which is not used. See Figure 44. All incoming pixel clocks are valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus. Start of Frame nth frame n+1th frame SENSB_VSYNC SENSB_PIX_CLK SENSB_DATA[7:0] invalid invalid 1st byte 1st byte Figure 44. Non-Gated Clock Mode Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 58 Freescale Semiconductor Electrical Characteristics The timing described in Figure 44 is that of a Motorola sensor. Some other sensors may have a slightly different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC; active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK. 4.3.14.3 Electrical Characteristics Figure 45 depicts the sensor interface timing, and Table 45 lists the timing parameters. 1/IP1 SENSB_MCLK (Sensor Input) SENSB_PIX_CLK (Sensor Output) IP3 IP2 1/IP4 SENSB_DATA, SENSB_VSYNC, SENSB_HSYNC Figure 45. Sensor Interface Timing Diagram Table 45. Sensor Interface Timing Parameters1 ID 1 Parameter Symbol Min. Max. Units IP1 Sensor input clock frequency Fmck 0.01 133 MHz IP2 Data and control setup time Tsu 5 — ns IP3 Data and control holdup time Thd 3 — ns IP4 Sensor output (pixel) clock frequency Fpck 0.01 133 MHz The timing specifications for Figure 45 are referenced to the rising edge of SENS_PIX_CLK when the SENS_PIX_CLK_POL bit in the CSI_SENS_CONF register is cleared. When the SENS_PIX_CLK_POL is set, the clock is inverted and all timing specifications will remain the same but are referenced to the falling edge of the clock. 4.3.15 4.3.15.1 IPU—Display Interfaces Supported Display Components Table 46 lists the known supported display components at the time of publication. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 59 Electrical Characteristics Table 46. Supported Display Components1 Type Vendor TFT displays (memory-less) Display controllers Smart display modules Digital video encoders (for TV) Model Sharp (HR-TFT Super Mobile LCD family) LQ035Q7 DB02, LM019LC1Sxx Samsung (QCIF and QVGA TFT modules for mobile phones) LTS180S1-HF1, LTS180S3-HF1, LTS350Q1-PE1, LTS350Q1-PD1, LTS220Q1-HE12 Toshiba (LTM series) LTM022P8062, LTM04C380K2, LTM018A02A2, LTM020P3322, LTM021P3372, LTM019P3342, LTM022A7832, LTM022A05ZZ2 NEC NL6448BC20-08E, NL8060BC31-27 Epson S1D15xxx series, S1D19xxx series, S1D13713, S1D13715 Solomon Systech SSD1301 (OLED), SSD1828 (LDCD) Hitachi HD66766, HD66772 ATI W2300 Epson L1F10043 T2, L1F10044 T2, L1F10045 T2, L2D220022, L2D200142, L2F500322, L2D25001 T2 Hitachi 120 160 65K/4096 C-STN (#3284 LTD-1398-2) based on HD 66766 controller Densitron Europe LTD All displays with MPU 80/68K series interface and serial peripheral interface Sharp LM019LC1Sxx Sony ACX506AKM Analog Devices ADV7174/7179 Crystal (Cirrus Logic) CS49xx series Focus FS453/4 1 Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only display component suppliers. 2 These display components not validated at time of publication. 4.3.15.2 4.3.15.2.1 Synchronous Interfaces Interface to Active Matrix TFT LCD Panels, Functional Description Figure 46 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with negative polarity. The sequence of events for active matrix interface timing is: • DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, DISPB_D3_CLK runs continuously. • DISPB_D3_HSYNC causes the panel to start a new line. • DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 60 Freescale Semiconductor Electrical Characteristics • DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. DISPB_D3_VSYNC DISPB_D3_HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n DISPB_D3_HSYNC DISPB_D3_DRDY 1 2 3 m-1 m DISPB_D3_CLK DISPB_D3_DATA Figure 46. Interface Timing Diagram for TFT (Active Matrix) Panels 4.3.15.2.2 Interface to Active Matrix TFT LCD Panels, Electrical Characteristics Figure 47 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals. IP7 IP9 IP6 IP10 IP8 Start of line IP5 DISPB_D3_CLK DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_DATA Figure 47. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 48 depicts the vertical timing (timing of one frame). All figure parameters shown are programmable. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 61 Electrical Characteristics End of frame Start of frame IP13 DISPB_D3_VSYNC DISPB_D3_HSYNC DISPB_D3_DRDY IP11 IP15 IP14 IP12 Figure 48. TFT Panels Timing Diagram—Vertical Sync Pulse Table 47 shows timing parameters of signals presented in Figure 47 and Figure 48. Table 47. Synchronous Display Interface Timing Parameters—Pixel Level ID 1 Parameter Symbol Value Units IP5 Display interface clock period Tdicp Tdicp1 ns IP6 Display pixel clock period Tdpcp (DISP3_IF_CLK_CNT_D+1) * Tdicp ns IP7 Screen width Tsw (SCREEN_WIDTH+1) * Tdpcp ns IP8 HSYNC width Thsw (H_SYNC_WIDTH+1) * Tdpcp ns IP9 Horizontal blank interval 1 Thbi1 BGXP * Tdpcp ns IP10 Horizontal blank interval 2 Thbi2 (SCREEN_WIDTH – BGXP – FW) * Tdpcp ns IP11 HSYNC delay Thsd H_SYNC_DELAY * Tdpcp ns IP12 Screen height Tsh (SCREEN_HEIGHT+1) * Tsw ns IP13 VSYNC width Tvsw if V_SYNC_WIDTH_L = 0 than (V_SYNC_WIDTH+1) * Tdpcp else (V_SYNC_WIDTH+1) * Tsw ns IP14 Vertical blank interval 1 Tvbi1 BGYP * Tsw ns IP15 Vertical blank interval 2 Tvbi2 (SCREEN_HEIGHT – BGYP – FH) * Tsw ns Display interface clock period immediate value. ⎧ DISP3_IF_CLK_PER_WR ⎪ T HSP_CLK ⋅ ------------------------------------------------------------------, HSP_CLK_PERIOD ⎪ Tdicp = ⎨ DISP3_IF_CLK_PER_WR ⎪T ⋅ ⎛ floor ------------------------------------------------------------------ + 0.5 ± 0.5⎞⎠ , ⎪ HSP_CLK ⎝ HSP_CLK_PERIOD ⎩ DISP3_IF_CLK_PER_WR for integer -----------------------------------------------------------------HSP_CLK_PERIOD DISP3_IF_CLK_PER_WR for fractional -----------------------------------------------------------------HSP_CLK_PERIOD Display interface clock period average value. DISP3_IF_CLK_PER_WR Tdicp = T HSP_CLK ⋅ -----------------------------------------------------------------HSP_CLK_PERIOD MCIMX31/MCIMX31L Technical Data, Rev. 4.1 62 Freescale Semiconductor Electrical Characteristics NOTE HSP_CLK is the High-Speed Port Clock, which is the input to the Image Processing Unit (IPU). Its frequency is controlled by the Clock Control Module (CCM) settings. The HSP_CLK frequency must be greater than or equal to the AHB clock frequency. The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF, SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters are programmed via the DI_DISP3_TIME_CONF, DI_HSP_CLK_PER and DI_DISP_ACC_CC Registers. Figure 49 depicts the synchronous display interface timing for access level, and Table 48 lists the timing parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the DI_DISP3_TIME_CONF Register. IP20 DISPB_D3_VSYNC DISPB_D3_HSYNC DISPB_D3_DRDY other controls DISPB_D3_CLK IP16 IP17 IP19 IP18 DISPB_DATA Figure 49. Synchronous Display Interface Timing Diagram—Access Level Table 48. Synchronous Display Interface Timing Parameters—Access Level ID Parameter Symbol Typ1 Min Max Units IP16 Display interface clock low time Tckl Tdicd–Tdicu–1.5 Tdicd2–Tdicu3 Tdicd–Tdicu+1.5 ns IP17 Display interface clock high time Tckh Tdicp–Tdicd+Tdicu–1.5 Tdicp–Tdicd+Tdicu Tdicp–Tdicd+Tdicu+1.5 ns IP18 Data setup time Tdsu Tdicd–3.5 Tdicu — ns IP19 Data holdup time Tdhd Tdicp–Tdicd–3.5 Tdicp–Tdicu — ns IP20 Control signals setup time to display interface clock Tcsu Tdicd–3.5 Tdicu — ns 1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 63 Electrical Characteristics 2 Display interface clock down time 1 2 ⋅ DISP3_IF_CLK_DOWN_WR Tdicd = --- T HSP_CLK ⋅ ceil --------------------------------------------------------------------------------2 HSP_CLK_PERIOD 3 Display interface clock up time 1 2 ⋅ DISP3_IF_CLK_UP_WR Tdicu = --- T HSP_CLK ⋅ ceil ---------------------------------------------------------------------2 HSP_CLK_PERIOD where CEIL(X) rounds the elements of X to the nearest integers towards infinity. 4.3.15.3 Interface to Sharp HR-TFT Panels Figure 50 depicts the Sharp HR-TFT panel interface timing, and Table 49 lists the timing parameters. The CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY, REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” The timing images correspond to straight polarity of the Sharp signals. Horizontal timing DISPB_D3_CLK D1 D2 DISPB_D3_DATA DISPB_D3_SPL IP21 D320 1 DISPB_D3_CLK period DISPB_D3_HSYNC IP23 IP22 DISPB_D3_CLS IP24 DISPB_D3_PS IP25 IP26 DISPB_D3_REV Example is drawn with FW+1=320 pixel/line, FH+1=240 lines. SPL pulse width is fixed and aligned to the first data of the line. REV toggles every HSYNC period. Figure 50. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level MCIMX31/MCIMX31L Technical Data, Rev. 4.1 64 Freescale Semiconductor Electrical Characteristics Table 49. Sharp Synchronous Display Interface Timing Parameters—Pixel Level ID Parameter Symbol Value Units IP21 SPL rise time Tsplr (BGXP – 1) * Tdpcp ns IP22 CLS rise time Tclsr CLS_RISE_DELAY * Tdpcp ns IP23 CLS fall time Tclsf CLS_FALL_DELAY * Tdpcp ns IP24 CLS rise and PS fall time Tpsf PS_FALL_DELAY * Tdpcp ns IP25 PS rise time Tpsr PS_RISE_DELAY * Tdpcp ns IP26 REV toggle time Trev REV_TOGGLE_DELAY * Tdpcp ns 4.3.15.4 Synchronous Interface to Dual-Port Smart Displays Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are identical to parameters of the synchronous interface. See Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” 4.3.15.4.1 Interface to a TV Encoder, Functional Description The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 51 depicts the interface timing, • The frequency of the clock DISPB_D3_CLK is 27 MHz (within 10%). • The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low. • The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal. It remains low for a single clock cycle. • The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC signal. It remains low for at least one clock cycle. — At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC and DISPB_D3_HSYNC coincide. — At a transition to an even field (of the same frame), they do not coincide. • The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC signal being high. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 65 Electrical Characteristics DISPB_D3_CLK DISPB_D3_HSYNC DISPB_D3_VSYNC DISPB_D3_DRDY DISPB_DATA Cb Y Cr Y Cb Y Cr Pixel Data Timing DISPB_D3_HSYNC 523 524 525 1 2 3 5 4 6 10 DISPB_D3_DRDY DISPB_D3_VSYNC Even Field 261 262 Odd Field 263 264 265 266 267 268 269 273 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC Even Field Odd Field Line and Field Timing - NTSC DISPB_D3_HSYNC 621 622 623 624 625 1 3 2 4 23 DISPB_D3_DRDY DISPB_D3_VSYNC Even Field 308 Odd Field 309 310 311 312 313 314 315 316 336 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC Even Field Odd Field Line and Field Timing - PAL Figure 51. TV Encoder Interface Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 66 Freescale Semiconductor Electrical Characteristics 4.3.15.4.2 Interface to a TV Encoder, Electrical Characteristics The timing characteristics of the TV encoder interface are identical to the synchronous display characteristics. See Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” 4.3.15.5 4.3.15.5.1 Asynchronous Interfaces Parallel Interfaces, Functional Description The IPU supports the following asynchronous parallel interfaces: • System 80 interface — Type 1 (sampling with the chip select signal) with and without byte enable signals. — Type 2 (sampling with the read and write signals) with and without byte enable signals. • System 68k interface — Type 1 (sampling with the chip select signal) with or without byte enable signals. — Type 2 (sampling with the read and write signals) with or without byte enable signals. For each of four system interfaces, there are three burst modes: 1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters of the IDMAC (when data is transferred from the system memory) of by the HBURST signal (when the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type 1 interfaces, data is sampled by the CS signal and other control signals changes only when transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals (system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during the whole burst. 2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are changed simultaneously with data when the bus state (read, write or wait) is altered. The CS signals and other controls move to non-active state after burst has been completed. 3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The data is sampled with CS or other controls according the interface type as described above. All controls (including CS) become non-active for one display interface clock after each access. This mode corresponds to the ATI single access mode. Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 52, Figure 53, Figure 54, and Figure 55. These timing images correspond to active-low DISPB_D#_CS, DISPB_D#_WR and DISPB_D#_RD signals. Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 67 Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by CS signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 52. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 68 Freescale Semiconductor Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by WR/RD signals DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 53. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 69 Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by CS signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 54. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 70 Freescale Semiconductor Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by ENABLE signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 55. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram Display read operation can be performed with wait states when each read access takes up to four display interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the DI_DISP0_TIME_CONF_3, DI_DISP1_TIME_CONF_3, DI_DISP2_TIME_CONF_3 Registers. Figure 56 shows timing of the parallel interface with read wait states. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 71 Electrical Characteristics WRITE OPERATION READ OPERATION DISP0_RD_WAIT_ST=00 DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISP0_RD_WAIT_ST=01 DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISP0_RD_WAIT_ST=10 DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA Figure 56. Parallel Interface Timing Diagram—Read Wait States 4.3.15.5.2 Parallel Interfaces, Electrical Characteristics Figure 57, Figure 59, Figure 58, and Figure 60 depict timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces. Table 50 lists the timing parameters at display access level. All timing images are based on active low control signals (signals polarity is controlled via the DI_DISP_SIG_POL Register). MCIMX31/MCIMX31L Technical Data, Rev. 4.1 72 Freescale Semiconductor Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) IP35, IP33 IP36, IP34 DISPB_D#_CS DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) IP31, IP29 IP32, IP30 read point IP38 IP37 DISPB_DATA (Input) Read Data IP40 IP39 DISPB_DATA (Output) IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 57. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 73 Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_D#_CS IP35, IP33 IP36, IP34 DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) IP31, IP29 IP32, IP30 read point IP37 DISPB_DATA (Input) IP38 Read Data IP39 IP40 DISPB_DATA (Output) IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 58. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 74 Freescale Semiconductor Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) IP35,IP33 IP36, IP34 DISPB_D#_CS DISPB_WR (READ/WRITE) IP31, IP29 IP32, IP30 read point IP37 DISPB_DATA (Input) IP38 Read Data IP39 IP40 DISPB_DATA (Output) IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 59. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 75 Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_D#_CS IP35,IP33 IP36, IP34 DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) DISPB_WR (READ/WRITE) IP32, IP30 IP31, IP29 read point IP38 IP37 DISPB_DATA (Input) Read Data IP39 IP40 DISPB_DATA (Output) IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 60. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram Table 50. Asynchronous Parallel Interface Timing Parameters—Access Level ID Parameter IP27 Read system cycle time IP28 Write system cycle time Symbol Tcycr Tcycw Typ.1 Min. Tdicpr–1.5 Tdicpr2 3 Max. Units Tdicpr+1.5 ns Tdicpw–1.5 Tdicpw Tdicpw+1.5 ns Tdicdr4–Tdicur5 Tdicdr–Tdicur+1.5 ns Tdicpr–Tdicdr+Tdicur+1.5 ns IP29 Read low pulse width Trl Tdicdr–Tdicur–1.5 IP30 Read high pulse width Trh Tdicpr–Tdicdr+Tdicur–1.5 Tdicpr–Tdicdr+ Tdicur IP31 Write low pulse width Twl Tdicdw–Tdicuw–1.5 Tdicdw6–Tdicuw7 Tdicdw–Tdicuw+1.5 ns IP32 Write high pulse width Twh Tdicpw–Tdicdw+ Tdicuw–1.5 Tdicpw–Tdicdw+ Tdicuw Tdicpw–Tdicdw+ Tdicuw+1.5 ns IP33 Controls setup time for read Tdcsr Tdicur–1.5 Tdicur — ns IP34 Controls hold time for read Tdchr Tdicpr–Tdicdr–1.5 Tdicpr–Tdicdr — ns IP35 Controls setup time for write Tdcsw Tdicuw–1.5 Tdicuw — ns MCIMX31/MCIMX31L Technical Data, Rev. 4.1 76 Freescale Semiconductor Electrical Characteristics Table 50. Asynchronous Parallel Interface Timing Parameters—Access Level (continued) ID Parameter Symbol IP36 Controls hold time for write IP37 Slave device data delay Tdchw 8 Typ.1 Min. Tdicpw–Tdicdw–1.5 Max. Units — ns Tdicpw–Tdicdw 9 10 Tracc 0 — Tdrp –Tlbd –Tdicur–1.5 ns Troh Tdrp–Tlbd–Tdicdr+1.5 — Tdicpr–Tdicdr–1.5 ns IP39 Write data setup time Tds Tdicdw–1.5 Tdicdw — ns IP40 Write data hold time Tdh Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw — ns Tdicpr–1.5 Tdicpr Tdicpr+1.5 ns Tdicpw Tdicpw–1.5 Tdicpw Tdicpw+1.5 ns Tdicdr Tdicdr–1.5 Tdicdr Tdicdr+1.5 ns Tdicur Tdicur–1.5 Tdicur Tdicur+1.5 ns Tdicdw Tdicdw–1.5 Tdicdw Tdicdw+1.5 ns Tdicuw Tdicuw–1.5 Tdicuw Tdicuw+1.5 ns Tdrp Tdrp+1.5 ns IP38 Slave device data hold time IP41 Read 8 period2 Tdicpr 3 IP42 Write period IP43 Read down time4 5 IP44 Read up time IP45 Write down IP46 Write up time6 time7 IP47 Read time point9 Tdrp Tdrp–1.5 1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. 2 Display interface clock period value for read: DISP#_IF_CLK_PER_RD Tdicpr = T HSP_CLK ⋅ ceil ---------------------------------------------------------------HSP_CLK_PERIOD 3 Display interface clock period value for write: DISP#_IF_CLK_PER_WR Tdicpw = T HSP_CLK ⋅ ceil -----------------------------------------------------------------HSP_CLK_PERIOD 4 Display interface clock down time for read: 2 ⋅ DISP#_IF_CLK_DOWN_RD 1 Tdicdr = --- T HSP_CLK ⋅ ceil ------------------------------------------------------------------------------HSP_CLK_PERIOD 2 5 Display interface clock up time for read: 1 2 ⋅ DISP#_IF_CLK_UP_RD Tdicur = --- T HSP_CLK ⋅ ceil -------------------------------------------------------------------2 HSP_CLK_PERIOD 6 Display interface clock down time for write: 1 2 ⋅ DISP#_IF_CLK_DOWN_WR Tdicdw = --- T HSP_CLK ⋅ ceil --------------------------------------------------------------------------------2 HSP_CLK_PERIOD 7 Display interface clock up time for write: 1 2 ⋅ DISP#_IF_CLK_UP_WR Tdicuw = --- T HSP_CLK ⋅ ceil ---------------------------------------------------------------------2 HSP_CLK_PERIOD 8 9 This parameter is a requirement to the display connected to the IPU Data read point DISP#_READ_EN Tdrp = T HSP_CLK ⋅ ceil -------------------------------------------------HSP_CLK_PERIOD 10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 77 Electrical Characteristics The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers. 4.3.15.5.3 Serial Interfaces, Functional Description The IPU supports the following types of asynchronous serial interfaces: • 3-wire (with bidirectional data line) • 4-wire (with separate data input and output lines) • 5-wire type 1 (with sampling RS by the serial clock) • 5-wire type 2 (with sampling RS by the chip select signal) Figure 61 depicts timing of the 3-wire serial interface. The timing images correspond to active-low DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal. For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal provided by the IPU. Each data transfer can be preceded by an optional preamble with programmable length and contents. The preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is programmable. The RW bit can be disabled. The following data can consist of one word or of a whole burst. The interface parameters are controlled by the DI_SER_DISP1_CONF and DI_SER_DISP2_CONF Registers. DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D RW Preamble RS D7 D6 D5 D4 D3 D2 D1 D0 Input or output data Figure 61. 3-Wire Serial Interface Timing Diagram Figure 62 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output data lines both inside and outside the device. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 78 Freescale Semiconductor Electrical Characteristics Write DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW RS D7 D6 D5 Preamble D4 D3 D2 D1 D0 Output data DISPB_SD_D (Input) Read DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW RS Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 Input data Figure 62. 4-Wire Serial Interface Timing Diagram Figure 63 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries of words. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 79 Electrical Characteristics Write DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW D7 D6 D5 Preamble D4 D3 D2 D1 D0 Output data DISPB_SD_D (Input) DISPB_SER_RS Read DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 Input data DISPB_SER_RS Figure 63. 5-Wire Serial Interface (Type 1) Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 80 Freescale Semiconductor Electrical Characteristics Figure 64 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries of words. Write DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW D7 D6 D5 D4 D3 D2 D1 D0 Output data Preamble DISPB_SD_D (Input) DISPB_SER_RS 1 display IF clock cycle Read DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW Preamble DISPB_SD_D (Input) DISPB_SER_RS D7 D6 D5 1 display IF clock cycle D4 D3 D2 D1 D0 Input data Figure 64. 5-Wire Serial Interface (Type 2) Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 81 Electrical Characteristics Serial Interfaces, Electrical Characteristics 4.3.15.5.4 Figure 65 depicts timing of the serial interface. Table 51 lists the timing parameters at display access level. IP49, IP48 DISPB_SER_RS IP56,IP54 IP57, IP55 DISPB_SD_D_CLK IP51, IP53 IP50, IP52 read point IP59 IP58 DISPB_DATA (Input) Read Data IP60 IP61 DISPB_DATA (Output) IP67,IP65 IP47 IP64, IP66 IP62, IP63 Figure 65. Asynchronous Serial Interface Timing Diagram Table 51. Asynchronous Serial Interface Timing Parameters—Access Level ID Parameter Symbol Typ.1 Min. Max. Units IP48 Read system cycle time Tcycr Tdicpr–1.5 Tdicpr2 Tdicpr+1.5 ns IP49 Write system cycle time Tcycw Tdicpw–1.5 Tdicpw3 Tdicpw+1.5 ns IP50 Read clock low pulse width Trl Tdicdr–Tdicur–1.5 Tdicdr4–Tdicur5 Tdicdr–Tdicur+1.5 ns IP51 Read clock high pulse width Trh Tdicpr–Tdicdr+Tdicur–1.5 Tdicpr–Tdicdr+ Tdicur Tdicpr–Tdicdr+Tdicur+1.5 ns IP52 Write clock low pulse width Twl Tdicdw–Tdicuw–1.5 Tdicdw6–Tdicuw7 Tdicdw–Tdicuw+1.5 ns IP53 Write clock high pulse width Twh Tdicpw–Tdicdw+ Tdicuw–1.5 Tdicpw–Tdicdw+ Tdicuw Tdicpw–Tdicdw+ Tdicuw+1.5 ns IP54 Controls setup time for read Tdcsr Tdicur–1.5 Tdicur — ns IP55 Controls hold time for read Tdchr Tdicpr–Tdicdr–1.5 Tdicpr–Tdicdr — ns MCIMX31/MCIMX31L Technical Data, Rev. 4.1 82 Freescale Semiconductor Electrical Characteristics Table 51. Asynchronous Serial Interface Timing Parameters—Access Level (continued) ID Parameter Symbol Typ.1 Min. IP56 Controls setup time for write Tdcsw Tdicuw–1.5 Tdicuw IP57 Controls hold time for write Tdchw Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw IP58 Slave device data delay 8 Max. Units — ns — ns 9 10 Tracc 0 — Tdrp –Tlbd –Tdicur–1.5 ns Troh Tdrp–Tlbd–Tdicdr+1.5 — Tdicpr–Tdicdr–1.5 ns IP60 Write data setup time Tds Tdicdw–1.5 Tdicdw — ns IP61 Write data hold time Tdh Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw — ns Tdicpr–1.5 Tdicpr Tdicpr+1.5 ns Tdicpw Tdicpw–1.5 Tdicpw Tdicpw+1.5 ns Tdicdr Tdicdr–1.5 Tdicdr Tdicdr+1.5 ns Tdicur Tdicur–1.5 Tdicur Tdicur+1.5 ns Tdicdw Tdicdw–1.5 Tdicdw Tdicdw+1.5 ns Tdicuw Tdicuw–1.5 Tdicuw Tdicuw+1.5 ns Tdrp Tdrp+1.5 ns IP59 Slave device data hold time IP62 Read period2 IP63 Write period3 IP64 Read down time Tdicpr 4 time5 IP65 Read up IP66 Write down IP67 Write up 8 time6 time7 IP68 Read time point9 Tdrp Tdrp–1.5 1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. 2 Display interface clock period value for read: DISP#_IF_CLK_PER_RD Tdicpr = T HSP_CLK ⋅ ceil ---------------------------------------------------------------HSP_CLK_PERIOD 3 Display interface clock period value for write: DISP#_IF_CLK_PER_WR Tdicpw = T HSP_CLK ⋅ ceil -----------------------------------------------------------------HSP_CLK_PERIOD 4 Display interface clock down time for read: 1 2 ⋅ DISP#_IF_CLK_DOWN_RD Tdicdr = --- T HSP_CLK ⋅ ceil ------------------------------------------------------------------------------2 HSP_CLK_PERIOD 5 Display interface clock up time for read: 1 2 ⋅ DISP#_IF_CLK_UP_RD Tdicur = --- T ⋅ ceil -------------------------------------------------------------------2 HSP_CLK HSP_CLK_PERIOD 6 Display interface clock down time for write: 1 2 ⋅ DISP#_IF_CLK_DOWN_WR Tdicdw = --- T ⋅ ceil --------------------------------------------------------------------------------2 HSP_CLK HSP_CLK_PERIOD 7 Display interface clock up time for write: 1 2 ⋅ DISP#_IF_CLK_UP_WR Tdicuw = --- T HSP_CLK ⋅ ceil ---------------------------------------------------------------------2 HSP_CLK_PERIOD 8 This parameter is a requirement to the display connected to the IPU. Data read point: 9 Tdrp = T 10 HSP_CLK DISP#_READ_EN ⋅ ceil -------------------------------------------------HSP_CLK_PERIOD Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 83 Electrical Characteristics The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers. 4.3.16 Memory Stick Host Controller (MSHC) Figure 66, Figure 67, and Figure 68 depict the MSHC timings, and Table 52 and Table 53 list the timing parameters. tSCLKc tSCLKwh tSCLKwl MSHC_SCLK tSCLKr tSCLKf Figure 66. MSHC_CLK Timing Diagram tSCLKc MSHC_SCLK tBSsu tBSh MSHC_BS tDsu tDh MSHC_DATA (Output) tDd MSHC_DATA (Intput) Figure 67. Transfer Operation Timing Diagram (Serial) MCIMX31/MCIMX31L Technical Data, Rev. 4.1 84 Freescale Semiconductor Electrical Characteristics tSCLKc MSHC_SCLK tBSsu tBSh MSHC_BS tDsu tDh MSHC_DATA (Output) tDd MSHC_DATA (Intput) Figure 68. Transfer Operation Timing Diagram (Parallel) NOTE The Memory Stick Host Controller is designed to meet the timing requirements per Sony's Memory Stick Pro Format Specifications document. Tables in this section details the specifications requirements for parallel and serial modes, and not the MCIMX31 timing. Table 52. Serial Interface Timing Parameters1 Standards Signal MSHC_SCLK Parameter Symbol Unit Min. Max. Cycle tSCLKc 50 — ns H pulse length tSCLKwh 15 — ns L pulse length tSCLKwl 15 — ns Rise time tSCLKr — 10 ns Fall time tSCLKf — 10 ns Setup time tBSsu 5 — ns Hold time tBSh 5 — ns Setup time tDsu 5 — ns Hold time tDh 5 — ns Output delay time tDd — 15 ns MSHC_BS MSHC_DATA 1 Timing is guaranteed for NVCC from 2.7 through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC restrictions described in Table 8, "Operating Ranges," on page 13. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 85 Electrical Characteristics Table 53. Parallel Interface Timing Parameters1 Standards Signal MSHC_SCLK Parameter Symbol Unit Min Max Cycle tSCLKc 25 — ns H pulse length tSCLKwh 5 — ns L pulse length tSCLKwl 5 — ns Rise time tSCLKr — 10 ns Fall time tSCLKf — 10 ns Setup time tBSsu 8 — ns Hold time tBSh 1 — ns Setup time tDsu 8 — ns Hold time tDh 1 — ns Output delay time tDd — 15 ns MSHC_BS MSHC_DATA 1 Timing is guaranteed for NVCC from 2.7 through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC restrictions described in Table 8, "Operating Ranges," on page 13. 4.3.17 Personal Computer Memory Card International Association (PCMCIA) Figure 69 and Figure 70 depict the timings pertaining to the PCMCIA module, each of which is an example of one clock of strobe set-up time and one clock of strobe hold time. Table 54 lists the timing parameters. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 86 Freescale Semiconductor Electrical Characteristics HCLK HADDR CONTROL HWDATA ADDR 1 CONTROL 1 DATA write 1 HREADY HRESP OKAY A[25:0] ADDR 1 D[15:0] OKAY OKAY DATA write 1 WAIT REG REG OE/WE/IORD/IOWR CE1/CE2 RW POE PSST PSL PSHT Figure 69. Write Accesses Timing Diagram—PSHT=1, PSST=1 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 87 Electrical Characteristics HCLK ADDR 1 HADDR CONTROL CONTROL 1 DATA read 1 RWDATA HREADY HRESP OKAY A[25:0] ADDR 1 OKAY OKAY D[15:0] WAIT REG REG OE/WE/IORD/IOWR CE1/CE2 RW POE PSST PSHT PSL Figure 70. Read Accesses Timing Diagram—PSHT=1, PSST=1 Table 54. PCMCIA Write and Read Timing Parameters Symbol Parameter Min Max Unit PSHT PCMCIA strobe hold time 0 63 clock PSST PCMCIA strobe set up time 1 63 clock PSL PCMCIA strobe length 1 128 clock 4.3.18 PWM Electrical Specifications This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 88 Freescale Semiconductor Electrical Characteristics 4.3.18.1 PWM Timing Figure 71 depicts the timing of the PWM, and Table 55 lists the PWM timing characteristics. 1 2a 3b System Clock 2b 4b 3a 4a PWM Output Figure 71. PWM Timing Table 55. PWM Output Timing Parameters ID 1 4.3.19 Parameter Min Max Unit 0 ipg_clk MHz 1 System CLK frequency1 2a Clock high time 12.29 — ns 2b Clock low time 9.91 — ns 3a Clock fall time — 0.5 ns 3b Clock rise time — 0.5 ns 4a Output delay time — 9.37 ns 4b Output setup time 8.71 — ns CL of PWMO = 30 pF SDHC Electrical Specifications This section describes the electrical information of the SDHC. 4.3.19.1 SDHC Timing Figure 72 depicts the timings of the SDHC, and Table 56 lists the timing parameters. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 89 Electrical Characteristics SD4 SD1 SD3 SD2 CLK SD5 SD6 CMD DATA[3:0] Output from SDHC to card SD7 CMD DATA[3:0] Input to SDHC SD8 Figure 72. SDHC Timing Diagram Table 56. SDHC Interface Timing Parameters ID Parameter Symbol Min Max Unit Clock Frequency (Low Speed) fPP1 0 400 kHz Clock Frequency (SD/SDIO Full Speed) fPP2 0 25 MHz Clock Frequency (MMC Full Speed) fPP3 0 20 MHz Clock Frequency (Identification Mode) fOD4 100 400 kHz SD2 Clock Low Time tWL 10 — ns SD3 Clock High Time tWH 10 — ns SD4 Clock Rise Time tTLH — 10 ns SD5 Clock Fall Time tTHL — 10 ns tODL –6.5 3 ns Card Input Clock SD1 SDHC Output/Card Inputs CMD, DAT (Reference to CLK) SD6 SDHC output delay SDHC Input/Card Outputs CMD, DAT (Reference to CLK) SD7 SDHC input setup tIS — 18.5 ns SD8 SDHC input hold tIH — –11.5 ns 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 V–3.3 V. In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 MHz–25 MHz. 3 In normal data transfer mode for MMC card, clock frequency can be any value between 0 MHz–20 MHz. 4 In card identification mode, card clock must be 100 kHz–400 kHz, voltage ranges from 2.7 V–3.3 V. 2 4.3.20 SIM Electrical Specifications Each SIM card interface consist of a total of 12 pins (for 2 separate ports of 6 pins each. Mostly one port with 5 pins is used). MCIMX31/MCIMX31L Technical Data, Rev. 4.1 90 Freescale Semiconductor Electrical Characteristics The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins. There is no timing relationship between the clock and the data. The clock that the SIM module provides to the aim card will be used by the SIM card to recover the clock from the data much like a standard UART. All six (or 5 in case bi-directional TXRX is used) of the pins for each half of the SIM module are asynchronous to each other. There are no required timing relationships between the signals in normal mode, but there are some in two specific cases: reset and power down sequences. 4.3.20.1 General Timing Requirements Figure 73 shows the timing of the SIM module, and Figure 57 lists the timing parameters. 1/Sfreq CLK Sfall Srise Figure 73. SIM Clock Timing Diagram Table 57. SIM Timing Specification—High Drive Strength Num Description Symbol Min Max Unit 1 SIM Clock Frequency (CLK)1 Sfreq 0.01 5 (Some new cards may reach 10) MHz 2 SIM CLK Rise Time 2 Srise — 20 ns 3 SIM CLK Fall Time 3 Sfall — 20 ns 4 SIM Input Transition Time (RX, SIMPD) Strans — 25 ns 1 50% duty cycle clock With C = 50pF 3 With C = 50pF 2 4.3.20.2 4.3.20.2.1 Reset Sequence Cards with Internal Reset The sequence of reset for this kind of SIM Cards is as follows (see Figure 74): • After powerup, the clock signal is enabled on SGCLK (time T0) • After 200 clock cycles, RX must be high. • The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles after T0. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 91 Electrical Characteristics SVEN CLK response RX 1 2 T0 400 clock cycles < 1 < 200 clock cycles 2 < 40000 clock cycles Figure 74. Internal-Reset Card Reset Sequence 4.3.20.2.2 Cards with Active Low Reset The sequence of reset for this kind of card is as follows (see Figure 75): 1. After powerup, the clock signal is enabled on CLK (time T0) 2. After 200 clock cycles, RX must be high. 3. RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on RX during those 40000 clock cycles) 4. RST is set High (time T1) 5. RST must remain High for at least 40000 clock cycles after T1 and a response must be received on RX between 400 and 40000 clock cycles after T1. SVEN RST CLK response RX 2 1 3 3 T0 T1 400 clock cycles < 400000 clock cycles < 1 < 200 clock cycles 2 < 40000 clock cycles 3 Figure 75. Active-Low-Reset Card Reset Sequence MCIMX31/MCIMX31L Technical Data, Rev. 4.1 92 Freescale Semiconductor Electrical Characteristics 4.3.20.3 Power Down Sequence Power down sequence for SIM interface is as follows: 1. SIMPD port detects the removal of the SIM Card 2. RST goes Low 3. CLK goes Low 4. TX goes Low 5. VEN goes Low Each of this steps is done in one CKIL period (usually 32 kHz). Power down can be started because of a SIM Card removal detection or launched by the processor. Figure 76 and Table 58 show the usual timing requirements for this sequence, with Fckil = CKIL frequency value. Spd2rst SIMPD RST Srst2clk CLK Srst2dat DATA_TX Srst2ven SVEN Figure 76. SmartCard Interface Power Down AC Timing Table 58. Timing Requirements for Power Down Sequence Num Description Symbol Min Max Unit 1 SIM reset to SIM clock stop Srst2clk 0.9*1/FCKIL 0.8 µs 2 SIM reset to SIM TX data low Srst2dat 1.8*1/FCKIL 1.2 µs 3 SIM reset to SIM Voltage Enable Low Srst2ven 2.7*1/FCKIL 1.8 µs 4 SIM Presence Detect to SIM reset Low Spd2rst 0.9*1/FCKIL 25 ns MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 93 Electrical Characteristics 4.3.21 SJC Electrical Specifications This section details the electrical characteristics for the SJC module. Figure 77 depicts the SJC test clock input timing. Figure 78 depicts the SJC boundary scan timing, Figure 79 depicts the SJC test access port, Figure 80 depicts the SJC TRST timing, and Table 59 lists the SJC timing parameters. SJ1 SJ2 TCK (Input) SJ2 VM VIH VM VIL SJ3 SJ3 Figure 77. Test Clock Input Timing Diagram TCK (Input) VIH VIL SJ4 Data Inputs SJ5 Input Data Valid SJ6 Data Outputs Output Data Valid SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Figure 78. Boundary Scan (JTAG) Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 94 Freescale Semiconductor Electrical Characteristics TCK (Input) VIH VIL SJ8 TDI TMS (Input) SJ9 Input Data Valid SJ10 TDO (Output) Output Data Valid SJ11 TDO (Output) SJ10 TDO (Output) Output Data Valid Figure 79. Test Access Port Timing Diagram TCK (Input) SJ13 TRST (Input) SJ12 Figure 80. TRST Timing Diagram Table 59. SJC Timing Parameters All Frequencies ID Parameter Unit Min Max 1001 — ns SJ1 TCK cycle time SJ2 TCK clock pulse width measured at VM2 40 — ns SJ3 TCK rise and fall times — 3 ns SJ4 Boundary scan input data set-up time 10 — ns SJ5 Boundary scan input data hold time 50 — ns SJ6 TCK low to output data valid — 50 ns SJ7 TCK low to output high impedance — 50 ns SJ8 TMS, TDI data set-up time 10 — ns SJ9 TMS, TDI data hold time 50 — ns SJ10 TCK low to TDO data valid — 44 ns MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 95 Electrical Characteristics Table 59. SJC Timing Parameters (continued) All Frequencies ID Parameter Unit Min Max — 44 ns SJ11 TCK low to TDO high impedance SJ12 TRST assert time 100 — ns SJ13 TRST set-up time to TCK low 40 — ns 1 On cases where SDMA TAP is put in the chain, the max TCK frequency is limited by max ratio of 1:8 of SDMA core frequency to TCK limitation. This implies max frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock. 2 VM - mid point voltage 4.3.22 SSI Electrical Specifications This section describes the electrical information of SSI. Note the following pertaining to timing information: • All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. • All timings are on AUDMUX signals when SSI is being used for data transfer. • “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. • For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx Data (for example, during AC97 mode of operation). 4.3.22.1 SSI Transmitter Timing with Internal Clock Figure 81 depicts the SSI transmitter timing with internal clock, and Table 60 lists the timing parameters. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 96 Freescale Semiconductor Electrical Characteristics SS1 SS3 SS5 SS2 SS4 AD1_TXC (Output) SS8 SS6 AD1_TXFS (bl) (Output) SS10 SS12 AD1_TXFS (wl) (Output) SS14 SS15 SS16 SS18 SS17 AD1_TXD (Output) SS43 SS42 SS19 AD1_RXD (Input) Note: SRXD Input in Synchronous mode only SS1 SS3 SS5 SS2 SS4 DAM1_T_CLK (Output) SS6 SS8 DAM1_T_FS (bl) (Output) SS10 SS12 DAM1_T_FS (wl) (Output) SS14 SS15 SS16 SS18 SS17 DAM1_TXD (Output) SS43 SS42 SS19 DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 81. SSI Transmitter with Internal Clock Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 97 Electrical Characteristics Table 60. SSI Transmitter with Internal Clock Timing Parameters ID Parameter Min Max Unit Internal Clock Operation SS1 (Tx/Rx) CK clock period 81.4 — ns SS2 (Tx/Rx) CK clock high period 36.0 — ns SS3 (Tx/Rx) CK clock rise time — 6 ns SS4 (Tx/Rx) CK clock low period 36.0 — ns SS5 (Tx/Rx) CK clock fall time — 6 ns SS6 (Tx) CK high to FS (bl) high — 15.0 ns SS8 (Tx) CK high to FS (bl) low — 15.0 ns SS10 (Tx) CK high to FS (wl) high — 15.0 ns SS12 (Tx) CK high to FS (wl) low — 15.0 ns SS14 (Tx/Rx) Internal FS rise time — 6 ns SS15 (Tx/Rx) Internal FS fall time — 6 ns SS16 (Tx) CK high to STXD valid from high impedance — 15.0 ns SS17 (Tx) CK high to STXD high/low — 15.0 ns SS18 (Tx) CK high to STXD high impedance — 15.0 ns SS19 STXD rise/fall time — 6 ns 10.0 — ns Synchronous Internal Clock Operation SS42 SRXD setup before (Tx) CK falling SS43 SRXD hold after (Tx) CK falling 0 — ns SS52 Loading — 25 pF MCIMX31/MCIMX31L Technical Data, Rev. 4.1 98 Freescale Semiconductor Electrical Characteristics 4.3.22.2 SSI Receiver Timing with Internal Clock Figure 82 depicts the SSI receiver timing with internal clock, and Table 61 lists the timing parameters. SS1 SS3 SS5 SS2 SS4 AD1_TXC (Output) SS9 SS7 AD1_TXFS (bl) (Output) SS11 SS13 AD1_TXFS (wl) (Output) SS20 SS21 AD1_RXD (Input) SS51 SS47 SS48 SS49 SS50 AD1_RXC (Output) SS1 SS3 SS5 SS2 SS4 DAM1_T_CLK (Output) SS7 DAM1_T_FS (bl) (Output) SS9 SS11 SS13 DAM1_T_FS (wl) (Output) SS20 SS21 DAM1_RXD (Input) SS47 SS48 SS51 SS50 SS49 DAM1_R_CLK (Output) Figure 82. SSI Receiver with Internal Clock Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 99 Electrical Characteristics Table 61. SSI Receiver with Internal Clock Timing Parameters ID Parameter Min Max Unit Internal Clock Operation SS1 (Tx/Rx) CK clock period 81.4 — ns SS2 (Tx/Rx) CK clock high period 36.0 — ns SS3 (Tx/Rx) CK clock rise time — 6 ns SS4 (Tx/Rx) CK clock low period 36.0 — ns SS5 (Tx/Rx) CK clock fall time — 6 ns SS7 (Rx) CK high to FS (bl) high — 15.0 ns SS9 (Rx) CK high to FS (bl) low — 15.0 ns SS11 (Rx) CK high to FS (wl) high — 15.0 ns SS13 (Rx) CK high to FS (wl) low — 15.0 ns SS20 SRXD setup time before (Rx) CK low 10.0 — ns SS21 SRXD hold time after (Rx) CK low 0 — ns 15.04 — ns Oversampling Clock Operation SS47 Oversampling clock period SS48 Oversampling clock high period 6 — ns SS49 Oversampling clock rise time — 3 ns SS50 Oversampling clock low period 6 — ns SS51 Oversampling clock fall time — 3 ns MCIMX31/MCIMX31L Technical Data, Rev. 4.1 100 Freescale Semiconductor Electrical Characteristics 4.3.22.3 SSI Transmitter Timing with External Clock Figure 83 depicts the SSI transmitter timing with external clock, and Table 62 lists the timing parameters. SS22 SS23 SS25 SS26 SS24 AD1_TXC (Input) SS27 SS29 AD1_TXFS (bl) (Input) SS33 SS31 AD1_TXFS (wl) (Input) SS39 SS37 SS38 AD1_TXD (Output) SS45 SS44 AD1_RXD (Input) SS46 Note: SRXD Input in Synchronous mode only SS22 SS26 SS23 SS24 SS25 DAM1_T_CLK (Input) SS27 SS29 DAM1_T_FS (bl) (Input) SS33 SS31 DAM1_T_FS (wl) (Input) SS39 SS37 SS38 DAM1_TXD (Output) SS44 SS45 DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only SS46 Figure 83. SSI Transmitter with External Clock Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 101 Electrical Characteristics Table 62. SSI Transmitter with External Clock Timing Parameters ID Parameter Min Max Unit External Clock Operation SS22 (Tx/Rx) CK clock period 81.4 — ns SS23 (Tx/Rx) CK clock high period 36.0 — ns SS24 (Tx/Rx) CK clock rise time — 6.0 ns SS25 (Tx/Rx) CK clock low period 36.0 — ns SS26 (Tx/Rx) CK clock fall time — 6.0 ns SS27 (Tx) CK high to FS (bl) high –10.0 15.0 ns SS29 (Tx) CK high to FS (bl) low 10.0 — ns SS31 (Tx) CK high to FS (wl) high –10.0 15.0 ns SS33 (Tx) CK high to FS (wl) low 10.0 — ns SS37 (Tx) CK high to STXD valid from high impedance — 15.0 ns SS38 (Tx) CK high to STXD high/low — 15.0 ns SS39 (Tx) CK high to STXD high impedance — 15.0 ns Synchronous External Clock Operation SS44 SRXD setup before (Tx) CK falling 10.0 — ns SS45 SRXD hold after (Tx) CK falling 2.0 — ns SS46 SRXD rise/fall time — 6.0 ns MCIMX31/MCIMX31L Technical Data, Rev. 4.1 102 Freescale Semiconductor Electrical Characteristics 4.3.22.4 SSI Receiver Timing with External Clock Figure 84 depicts the SSI receiver timing with external clock, and Table 63 lists the timing parameters. SS22 SS26 SS24 SS25 SS23 AD1_TXC (Input) SS30 SS28 AD1_TXFS (bl) (Input) SS32 AD1_TXFS (wl) (Input) SS34 SS35 SS41 SS36 SS40 AD1_RXD (Input) SS22 SS24 SS26 SS23 SS25 DAM1_T_CLK (Input) SS30 SS28 DAM1_T_FS (bl) (Input) SS32 DAM1_T_FS (wl) (Input) SS34 SS35 SS41 SS36 SS40 DAM1_RXD (Input) Figure 84. SSI Receiver with External Clock Timing Diagram Table 63. SSI Receiver with External Clock Timing Parameters ID Parameter Min Max Unit External Clock Operation SS22 (Tx/Rx) CK clock period 81.4 — ns SS23 (Tx/Rx) CK clock high period 36.0 — ns SS24 (Tx/Rx) CK clock rise time — 6.0 ns SS25 (Tx/Rx) CK clock low period 36.0 — ns SS26 (Tx/Rx) CK clock fall time — 6.0 ns MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 103 Electrical Characteristics Table 63. SSI Receiver with External Clock Timing Parameters (continued) ID 4.3.23 Parameter Min Max Unit SS28 (Rx) CK high to FS (bl) high –10.0 15.0 ns SS30 (Rx) CK high to FS (bl) low 10.0 — ns SS32 (Rx) CK high to FS (wl) high –10.0 15.0 ns SS34 (Rx) CK high to FS (wl) low 10.0 — ns SS35 (Tx/Rx) External FS rise time — 6.0 ns SS36 (Tx/Rx) External FS fall time — 6.0 ns SS40 SRXD setup time before (Rx) CK low 10.0 — ns SS41 SRXD hold time after (Rx) CK low 2.0 — ns USB Electrical Specifications This section describes the electrical information of the USBOTG port. The OTG port supports both serial and parallel interfaces. The high speed (HS) interface is supported via the ULPI (Ultra Low Pin Count Interface). Figure 85 depicts the USB ULPI timing diagram, and Table 64 lists the timing parameters. Clock TSC THC Control out (stp) TSD THD Data out TDC TDC Control in (dir, nxt) TDD Data in Figure 85. USB ULPI Interface Timing Diagram Table 64. USB ULPI Interface Timing Specification1 Parameter Symbol Min Max Units Setup time (control in, 8-bit data in) TSC, TSD 6 — ns Hold time (control in, 8-bit data in) THC, THD 0 — ns Output delay (control out, 8-bit data out) TDC, TDD — 9 ns 1 Timing parameters are given as viewed by transceiver side. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 104 Freescale Semiconductor Package Information and Pinout 5 Package Information and Pinout This section includes the contact assignment information and mechanical package drawing for the MCIMX31. 5.1 MAPBGA Production Package—457 14 x 14 mm, 0.5 mm Pitch This section contains the outline drawing, signal assignment map (see Section 8, “Revision History,” Table 70 for the 0.5 mm 14 × 14 MAPBGA signal assignments), and MAPBGA ground/power ID by ball grid location for the 457 14 x 14 mm, 0.5 mm pitch package. 5.1.1 Production Package Outline Drawing–14 x 14 mm 0.5 mm Figure 86. Production Package: Case 1581—0.5 mm Pitch MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 105 Package Information and Pinout 5.1.2 MAPBGA Signal Assignment–14 × 14 mm 0.5 mm See Section 8, “Revision History,” Figure 70 for the 0.5 mm 14 × 14 MAPBGA signal assignments. 5.1.3 Connection Tables–14 x 14 mm 0.5 mm Table 65 shows the device connection list for power and ground, alpha-sorted. Table 66 shows the device connection list for signals. 5.1.3.1 Ground and Power ID Locations–14 x 14 mm 0.5 mm Table 65. 14 x 14 MAPBGA Ground/Power ID by Ball Grid Location GND/PWR ID Ball Location FGND AB24 FUSE_VDD AC24 FVCC AA24 GND A1, A2, A25, A26, B1, B2, B25, B26, C1, C2, C24, C25, C26, D1, D25, E22, E24, F21, L12, M11, M12, M13, M14, M15, M16, N12, N13, N14, N15, N16, P12, P13, P14, P15, P16, R12, R13, R14, R15, R16, T12, T13, V17, AC2, AC26, AD1, AD2, AD24, AD25, AD26, AE1, AE2, AE24, AE25, AE26, AF1, AF2, AF25, AF26 IOQVDD Y6 MGND T15 MVCC V15 NVCC1 G19, G21, K18 NVCC2 Y17, Y18, Y19, Y20 NVCC3 L9, M9, N11 NVCC4 L18, L19 NVCC5 E5, F6, G7 NVCC6 J15, J16, K15 NVCC7 N18, P18, R18, T18 NVCC8 J12, J13 NVCC9 J17 NVCC10 P9, P11, R11, T11 NVCC21 Y14, Y15, Y16 NVCC22 W7, Y7, Y8, Y9, Y10, Y11, Y12, Y13, AA6 QVCC J14, L13, L14, L15, L16, M18, U18, V10, V11, V12, V13 QVCC1 J10, J11, K9, L11 QVCC4 N9, R9, T9, U9 SGND T14 SVCC V14 UVCC V16 UGND T16 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 106 Freescale Semiconductor Package Information and Pinout 5.1.3.2 BGA Signal ID by Ball Grid Location–14 x 14 0.5 mm Table 66 shows the device connection list for signals only, alpha-sorted by signal identification. Table 66. 14 x 14 BGA Signal ID by Ball Grid Location Signal ID Ball Location Signal ID Ball Location A0 A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A24 A25 A3 A4 A5 A6 A7 A8 A9 ATA_CS0 ATA_CS1 ATA_DIOR ATA_DIOW ATA_DMACK ATA_RESET BATT_LINE BCLK BOOT_MODE0 BOOT_MODE1 BOOT_MODE2 BOOT_MODE3 BOOT_MODE4 CAPTURE CAS CE_CONTROL CKIH AD6 AF5 AF18 AC3 AD3 AD4 AF17 AF16 AF15 AF14 AF13 AF12 AB5 AF11 AF10 AF9 AF8 AF7 AF6 AE4 AA3 AF4 AB3 AE3 AD5 AF3 J6 F2 E2 H6 F1 H3 F7 AB26 F20 C21 D24 C22 D26 A22 AD20 A14 F24 CKIL CLKO CLKSS COMPARE CONTRAST CS0 CS1 CS2 CS3 CS4 CS5 CSI_D10 CSI_D11 CSI_D12 CSI_D13 CSI_D14 CSI_D15 CSI_D4 CSI_D5 CSI_D6 CSI_D7 CSI_D8 CSI_D9 CSI_HSYNC CSI_MCLK CSI_PIXCLK CSI_VSYNC CSPI1_MISO CSPI1_MOSI CSPI1_SCLK CSPI1_SPI_RDY CSPI1_SS0 CSPI1_SS1 CSPI1_SS2 CSPI2_MISO CSPI2_MOSI CSPI2_SCLK CSPI2_SPI_RDY CSPI2_SS0 CSPI2_SS1 CSPI2_SS2 CSPI3_MISO CSPI3_MOSI H21 C23 G26 G18 R24 AE23 AF23 AE21 AD22 AF24 AF22 M24 L26 M21 M25 M20 M26 L21 K25 L24 K26 L20 L25 K20 K24 J26 J25 P7 P2 N2 N3 P3 P1 P6 A4 E3 C7 B6 B5 C6 A5 G3 D2 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 107 Package Information and Pinout Table 66. 14 x 14 BGA Signal ID by Ball Grid Location (continued) Signal ID Ball Location Signal ID Ball Location CSPI3_SCLK CSPI3_SPI_RDY CTS1 CTS2 D0 D1 D10 D11 D12 D13 D14 D15 D2 D3 D3_CLS D3_REV D3_SPL D4 D5 D6 D7 D8 D9 DCD_DCE1 DCD_DTE1 DE DQM0 DQM1 DQM2 DQM3 DRDY0 DSR_DCE1 DSR_DTE1 DTR_DCE1 DTR_DCE2 DTR_DTE1 DVFS0 DVFS1 EB0 EB1 ECB FPSHIFT GPIO1_0 GPIO1_1 GPIO1_2 LD7 E1 G6 B11 G13 AB2 Y3 Y1 U7 W2 V3 W1 U6 AB1 W6 R20 T26 U25 AA2 V7 AA1 W3 Y2 V6 B12 B13 C18 AE19 AD19 AA20 AE18 N26 A11 A12 C11 F12 C12 E25 G24 W21 Y24 AD23 N21 F18 B23 C20 W25 GPIO1_3 GPIO1_4 GPIO1_5 (PWR RDY) GPIO1_6 GPIO3_0 GPIO3_1 HSYNC I2C_CLK I2C_DAT IOIS16 KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL3 KEY_COL4 KEY_COL5 KEY_COL6 KEY_COL7 KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3 KEY_ROW4 KEY_ROW5 KEY_ROW6 KEY_ROW7 L2PG LBA LCS0 LCS1 LD0 LD1 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD2 LD3 LD4 LD5 LD6 SCK6 F25 F19 B24 A23 K21 H26 N25 J24 H25 J3 C15 B17 G15 A17 C16 B18 F15 A18 F13 B15 C14 A15 G14 B16 F14 A16 See VPG1 AE22 P26 P21 T24 U26 V24 Y25 Y26 V21 AA25 W24 AA26 V20 T21 V25 T20 V26 U24 T2 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 108 Freescale Semiconductor Package Information and Pinout Table 66. 14 x 14 BGA Signal ID by Ball Grid Location (continued) Signal ID Ball Location Signal ID Ball Location LD8 LD9 M_GRANT M_REQUEST MA10 MCUPG NFALE NFCE NFCLE NFRB NFRE NFWE NFWP OE PAR_RS PC_BVD1 PC_BVD2 PC_CD1 PC_CD2 PC_POE PC_PWRON PC_READY PC_RST PC_RW PC_VS1 PC_VS2 PC_WAIT POR POWER_FAIL PWMO RAS READ RESET_IN RI_DCE1 RI_DTE1 RTCK RTS1 RTS2 RW RXD1 RXD2 SCK3 SCK4 SCK5 SDCKE0 SDCKE1 U21 W26 Y21 AC25 AC1 See VPG0 V1 T6 U3 U1 V2 T7 U2 AB25 R21 H2 K6 L7 K1 J7 K3 J2 H1 G2 J1 K7 L6 H24 E26 G1 AF19 P20 J21 F11 G12 C17 G11 B14 AB22 A10 A13 R2 C4 D3 AD21 AF21 SCLK0 SD_D_CLK SD_D_I SD_D_IO SD0 SD1 SD1_CLK SD1_CMD SD1_DATA0 SD1_DATA1 SD1_DATA2 SD1_DATA3 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18 SD19 SD2 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD3 SD30 SD31 SD4 SD5 SD6 SD7 SD8 SD9 SDBA0 SDBA1 TRSTB TTM_PAD B22 P24 N20 P25 AD18 AE17 M7 L2 M6 L1 L3 K2 AE15 AE14 AD14 AA14 AE13 AD13 AA13 AD12 AA12 AE11 AA19 AE10 AA11 AE9 AA10 AE8 AD10 AE7 AA9 AA8 AD9 AA18 AE6 AA7 AD17 AA17 AE16 AA16 AD15 AA15 AD7 AE5 B20 U20 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 109 Package Information and Pinout Table 66. 14 x 14 BGA Signal ID by Ball Grid Location (continued) Signal ID Ball Location Signal ID Ball Location SDCLK SDCLK SDQS0 SDQS1 SDQS2 SDQS3 SDWE SER_RS SFS3 SFS4 SFS5 SFS6 SIMPD0 SJC_MOD SRST0 SRX0 SRXD3 SRXD4 SRXD5 SRXD6 STX0 STXD3 STXD4 STXD5 STXD6 SVEN0 TCK TDI TDO TMS AA21 AE20 AD16 AE12 AD11 AD8 AF20 T25 R6 F3 A3 T3 G17 A20 C19 B21 R3 C3 B4 R7 F17 R1 B3 C5 T1 A21 B19 F16 A19 G16 TXD1 TXD2 USB_BYP USB_OC USB_PWR USBH2_CLK USBH2_DATA0 USBH2_DATA1 USBH2_DIR USBH2_NXT USBH2_STP USBOTG_CLK USBOTG_DATA0 USBOTG_DATA1 USBOTG_DATA2 USBOTG_DATA3 USBOTG_DATA4 USBOTG_DATA5 USBOTG_DATA6 USBOTG_DATA7 USBOTG_DIR USBOTG_NXT USBOTG_STP VPG0 VPG1 VSTBY VSYNC0 VSYNC3 WATCHDOG_RST WRITE F10 C13 A9 C10 B10 N1 M1 M3 N7 N6 M2 G10 F9 B8 G9 A7 C8 B7 F8 A6 B9 A8 C9 G25 J20 F26 N24 R26 A24 R25 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 110 Freescale Semiconductor Package Information and Pinout 5.2 MAPBGA Production Package—473 19 x 19 mm, 0.8 mm Pitch This section contains the outline drawing, signal assignment map (see Section 8, “Revision History,” Table 71 for the 19 x 19 mm, 0.8 mm pitch signal assignments), and MAPBGA ground/power ID by ball grid location for the 473 19 x 19 mm, 0.8 mm pitch package. 5.2.1 Production Package Outline Drawing–19 x 19 mm 0.8 mm Figure 87. Production Package: Case 1931—0.8 mm Pitch MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 111 Package Information and Pinout 5.2.2 MAPBGA Signal Assignment–19 × 19 mm 0.8 mm See Table 71 for the 19 × 19 mm, 0.8 mm pitch signal assignments/ball map. 5.2.3 Connection Tables–19 x 19 mm 0.8 mm Table 67 shows the device connection list for power and ground, alpha-sorted followed by Table 68, which shows the no-connects. Table 69 shows the device connection list for signals. 5.2.3.1 Ground and Power ID Locations—19 x 19 mm 0.8 mm Table 67. 19 x 19 BGA Ground/Power ID by Ball Grid Location GND/PWR ID Ball Location FGND U16 FUSE_VDD T15 FVCC T16 GND A1, A2, A3, A21, A22, A23, B1, B2, B22, B23, C1, C2, C22, C23, D22, D23, J12, J13, K10, K11, K12, K13, K14, L10, L11, L12, L13, L14, M9, M10, M11, M12, M13, M14, N10, N11, N12, N13, N14, P10, P11, P12, P13, P14, R12, Y1, Y23, AA1, AA2, AA22, AA23, AB1, AB2, AB21, AB22, AB23, AC1, AC2, AC21, AC22, AC23 IOQVDD T8 MGND U14 MVCC U15 NVCC1 G15, G16, H16, J17 NVCC2 N16, P16, R15, R16, T14 NVCC3 K7, K8, L7, L8 NVCC4 H14, J15, K15 NVCC5 G9, G10, H8, H9 NVCC6 G11, G12, G13, H12 NVCC7 H15, J16, K16, L16, M16 NVCC8 H10, H11, J11 NVCC9 G14 NVCC10 P8, R7, R8, R9, T9 NVCC21 T11, T12, T13, U11 NVCC22 T10, U7, U8, U9, U10, V6, V7, V8, V9, V10 QVCC H13, J14, L15, M15, N9, N15, P9, P15, R10, R11, R13, R14 QVCC1 J8, J9, J10, K9 QVCC4 L9, M7, M8, N8 SGND U13 SVCC U12 UVCC P18 UGND P17 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 112 Freescale Semiconductor Package Information and Pinout Table 68. 19 x 19 BGA No Connects1 1 5.2.3.2 Signal Ball Location NC N7 NC P7 NC U21 These contacts are not used and must be floated by the user. BGA Signal ID by Ball Grid Location—19 x 19 0.8 mm Table 69. 19 x 19 BGA Signal ID by Ball Grid Location Signal ID Ball Location Signal ID Ball Location A0 A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A24 A25 A3 A4 A5 A6 A7 A8 A9 ATA_CS0 ATA_CS1 ATA_DIOR ATA_DIOW ATA_DMACK ATA_RESET BATT_LINE BCLK BOOT_MODE0 BOOT_MODE1 Y6 AC5 V15 AB3 AA3 Y3 Y15 Y14 V14 Y13 V13 Y12 AB5 V12 Y11 V11 Y10 Y9 Y8 AA5 Y5 AC4 AB4 AA4 Y4 AC3 E1 G4 E3 H6 E2 F3 F6 W20 F17 C21 CKIL CLKO CLKSS COMPARE CONTRAST CS0 CS1 CS2 CS3 CS4 CS5 CSI_D10 CSI_D11 CSI_D12 CSI_D13 CSI_D14 CSI_D15 CSI_D4 CSI_D5 CSI_D6 CSI_D7 CSI_D8 CSI_D9 CSI_HSYNC CSI_MCLK CSI_PIXCLK CSI_VSYNC CSPI1_MISO CSPI1_MOSI CSPI1_SCLK CSPI1_SPI_RDY CSPI1_SS0 CSPI1_SS1 CSPI1_SS2 CSPI2_MISO CSPI2_MOSI E21 C20 H17 A20 N21 U17 Y22 Y18 Y19 Y20 AA21 K21 K22 K23 L20 L18 L21 J20 J21 L17 J22 J23 K20 H22 H20 H23 H21 N2 N1 M4 M1 M2 N6 M3 B4 D5 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 113 Package Information and Pinout Table 69. 19 x 19 BGA Signal ID by Ball Grid Location (continued) Signal ID Ball Location Signal ID Ball Location BOOT_MODE2 BOOT_MODE3 BOOT_MODE4 CAPTURE CAS CE_CONTROL CKIH CSPI3_SCLK CSPI3_SPI_RDY CTS1 CTS2 D0 D1 D10 D11 D12 D13 D14 D15 D2 D3 D3_CLS D3_REV D3_SPL D4 D5 D6 D7 D8 D9 DCD_DCE1 DCD_DTE1 DE DQM0 DQM1 DQM2 DQM3 DRDY0 DSR_DCE1 DSR_DTE1 DTR_DCE1 DTR_DCE2 DTR_DTE1 DVFS0 DVFS1 EB0 D20 F18 E20 D18 AA20 D12 F23 H7 F4 A9 C12 U6 W4 V1 U4 U3 R6 U2 U1 W3 V4 P20 P21 N17 T7 W2 V3 W1 T6 V2 C10 D11 D16 AB19 Y16 AA18 AB18 M17 B10 A11 F10 C11 A10 E22 E23 W22 CSPI2_SCLK CSPI2_SPI_RDY CSPI2_SS0 CSPI2_SS1 CSPI2_SS2 CSPI3_MISO CSPI3_MOSI GPIO1_3 GPIO1_4 GPIO1_5 (PWR RDY) GPIO1_6 GPIO3_0 GPIO3_1 HSYNC I2C_CLK I2C_DAT IOIS16 KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL3 KEY_COL4 KEY_COL5 KEY_COL6 KEY_COL7 KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3 KEY_ROW4 KEY_ROW5 KEY_ROW6 KEY_ROW7 L2PG LBA LCS0 LCS1 LD0 LD1 LD10 LD11 LD12 LD13 LD14 LD15 LD16 B5 D6 C5 A4 F7 D2 E4 G20 D21 D19 G18 G23 K17 L23 J18 K18 J7 A15 B15 D14 C15 F13 A16 B16 A17 A13 B13 C13 A14 F12 D13 B14 C14 See VPG1 V17 M22 N23 R23 R22 U22 R18 U20 V23 V22 V21 V20 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 114 Freescale Semiconductor Package Information and Pinout Table 69. 19 x 19 BGA Signal ID by Ball Grid Location (continued) Signal ID Ball Location Signal ID Ball Location EB1 ECB FPSHIFT GPIO1_0 GPIO1_1 GPIO1_2 LD7 LD8 LD9 M_GRANT M_REQUEST MA10 MCUPG NFALE NFCE NFCLE NFRB NFRE NFWE NFWP OE PAR_RS PC_BVD1 PC_BVD2 PC_CD1 PC_CD2 PC_POE PC_PWRON PC_READY PC_RST PC_RW PC_VS1 PC_VS2 PC_WAIT POR POWER_FAIL PWMO RAS READ RESET_IN RI_DCE1 RI_DTE1 RTCK RTS1 RTS2 RW W21 Y21 M23 C19 G17 B20 T20 R17 U23 U18 T17 Y2 See VPG0 T2 R4 T1 R3 T4 T3 P6 T18 P22 G2 H4 J3 H1 J6 K6 H2 F1 G3 H3 G1 J4 F21 F20 F2 AA19 N18 F22 D10 B11 D15 B9 B12 V18 LD17 LD2 LD3 LD4 LD5 LD6 SCK6 SCLK0 SD_D_CLK SD_D_I SD_D_IO SD0 SD1 SD1_CLK SD1_CMD SD1_DATA0 SD1_DATA1 SD1_DATA2 SD1_DATA3 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18 SD19 SD2 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD3 SD30 SD31 SD4 SD5 SD6 W23 R21 R20 T23 T22 T21 R2 B19 M21 M20 M18 AC18 AA17 K2 K3 K4 J1 J2 L6 AB14 AC14 AA13 AB13 AC13 AA12 AC12 AA11 AB11 AC11 AB17 AA10 AB10 AC10 AC9 AA9 AC8 AB8 AC7 AA8 AB7 AC17 AA7 AC6 AA16 AC16 AA15 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 115 Package Information and Pinout Table 69. 19 x 19 BGA Signal ID by Ball Grid Location (continued) Signal ID Ball Location Signal ID Ball Location RXD1 RXD2 SCK3 SCK4 SCK5 SDCKE0 SDCKE1 SDCLK SDCLK SDQS0 SDQS1 SDQS2 SDQS3 SDWE SER_RS SFS3 SFS4 SFS5 SFS6 SIMPD0 SJC_MOD SRST0 SRX0 SRXD3 SRXD4 SRXD5 SRXD6 STX0 STXD3 STXD4 STXD5 STXD6 SVEN0 TCK TDI TDO TMS C9 A12 P1 G6 D4 Y17 V16 AC20 AC19 AB16 AB12 AB9 AB6 AB20 P23 P2 D3 G7 P4 B18 C17 C18 A19 N3 C3 C4 R1 F16 N4 B3 D1 P3 D17 F14 A18 B17 C16 SD7 SD8 SD9 SDBA0 SDBA1 TRSTB TXD1 TXD2 USB_BYP USB_OC USB_PWR USBH2_CLK USBH2_DATA0 USBH2_DATA1 USBH2_DIR USBH2_NXT USBH2_STP USBOTG_CLK USBOTG_DATA0 USBOTG_DATA1 USBOTG_DATA2 USBOTG_DATA3 USBOTG_DATA4 USBOTG_DATA5 USBOTG_DATA6 USBOTG_DATA7 USBOTG_DIR USBOTG_NXT USBOTG_STP VPG0 VPG1 VSTBY VSYNC0 VSYNC3 WATCHDOG_RST WRITE AB15 AC15 AA14 AA6 Y7 F15 D9 F11 C8 B8 A8 L1 M6 K1 L2 L4 L3 D8 G8 C7 A6 F8 D7 B6 A5 C6 A7 B7 F9 G21 G22 H18 L22 N20 B21 N22 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 116 Freescale Semiconductor Freescale Semiconductor 5.3 Ball Maps Table 70. Ball Map—14 x 14 0.5 mm Pitch A 1 GND 2 GND B GND GND C GND GND D GND E F MCIMX31/MCIMX31L Technical Data, Rev. 4.1 CSPI3_ MOSI CSPI3_ ATA_DI SCLK OR ATA_D ATA_C MACK S1 3 SFS5 4 5 6 CSPI2 CSPI2_ USBOT _MISO SS2 G_DAT A7 STXD4 SRXD CSPI2_ CSPI2_ 5 SS0 SPI_R DY SRXD4 SCK4 STXD5 CSPI2_ SS1 PC_RS T J PC_VS 1 K PC_CD 2 L SD1_D ATA1 M USBH2 _DATA0 N USBH2 _CLK PC_BV D1 PC_RE ADY SD1_D ATA3 SD1_C MD USBH2 _STP CSPI1_ SCLK 8 9 USBOT USB_ G_NXT BYP USBOT G_DAT A1 USBOT G_DAT A4 CSPI2_ MOSI SFS4 13 14 15 16 17 18 19 CE_CO KEY_R KEY_R KEY_C KEY_C TDO NTROL OW3 OW7 OL3 OL7 DCD_D DCD_D RTS2 CE1 TE1 KEY_R KEY_R KEY_C KEY_C TCK OW1 OW5 OL1 OL5 KEY_R KEY_C KEY_C RTCK OW2 OL0 OL4 DE 25 26 SJC_M SVEN0 CAPTU GPIO1_ WATCH GND OD RE 6 DOG_R ST TRSTB SRX0 SCLK0 GPIO1_ GPIO1_ GND 1 5 20 21 GND A GND B 22 23 GND C SRST0 GPIO1 BOOT_ BOOT_ CLKO _2 MODE1 MODE3 NVCC5 GND NVCC5 BATT_L USBOT USBOT INE G_DAT G_DAT A6 A0 CSPI3_ NVCC5 USBOT SPI_R G_DAT DY A2 ATA_DI OW ATA_C PC_PO S0 E PC_BV PC_VS QVCC1 D2 2 PC_WA PC_CD NVCC3 IT 1 SD1_D SD1_C NVCC3 ATA0 LK USBH2 USBH2 QVCC4 _NXT _DIR ATA_R ESET IOIS16 STXD6 SCK6 SFS6 NFCE NFWE QVCC4 U NFRB NFCLE D15 D11 QVCC4 V NFALE NFRE W D14 D12 D13 D7 D9 D3 Y D8 D1 AA D6 D4 A4 AB D2 AC MA10 D0 GND A6 A11 AD GND GND A12 A13 A8 AE GND AF GND GND GND A7 A9 A3 A5 SDBA1 SD30 A1 A25 1 2 3 CSPI1_ CSPI1_ SS2 MISO SFS3 SRXD6 NVCC1 0 QVCC4 D5 NVCC2 2 IOQVD NVCC2 NVCC2 NVCC2 D 2 2 2 NVCC2 SD31 SD28 SD27 2 TXD1 RI_DC DTR_D KEY_R KEY_R KEY_C TDI E1 CE2 OW0 OW6 OL6 USBOT RTS1 G_CLK RI_DT CTS2 E1 KEY_R KEY_C TMS OW4 OL2 STX0 GPIO1 GPIO1 BOOT_ GND _0 _4 MODE 0 SIMPD COMP NVCC1 NVCC1 0 ARE NVCC6 QVCC QVCC QVCC QVCC NVCC4 NVCC4 CSI_D8 CSI_D4 GND GND GND GND GND GND QVCC NVCC3 GND GND GND GND GND NVCC7 NVCC1 GND 0 NVCC1 GND 0 NVCC1 GND 0 GND GND GND GND NVCC7 READ GND GND GND GND NVCC7 GND SGND MGND UGND D3_CL PAR_RS S LD4 LD2 NVCC7 QVCC QVCC QVCC QVCC QVCC SVCC MVCC UVCC GND 4 LCS1 5 6 SD25 SDQS2 SD17 SD26 A24 SD20 A21 SD19 A20 10 11 7 SD24 A23 8 SD22 A22 9 SD15 SD12 SD8 SDQS0 SD4 SDQS1 SD14 A19 A18 SD11 A17 SD10 A16 SD6 A15 14 15 12 13 16 SD1 A14 17 SD0 CLKSS G GPIO3_ 1 CSI_PIX CLK CSI_D7 H SDCKE CS3 0 DQM3 DQM0 SDCLK CS2 LBA A10 RAS SDWE SDCKE CS5 1 18 19 20 21 22 J K L M N LD6 U LD10 LD15 LD3 LD7 LD5 LD9 V W EB1 LD11 LD12 Y FVCC LD14 LD16 AA OE BCLK M_REQ GND UEST GND GND AB AC ECB FGND FUSE_V DD GND CS0 CS1 GND CS4 GND GND GND GND AE AF 24 25 26 TTM_P LD8 AD LD17 LD13 EB0 DQM1 CAS VPG0 E SD_D_I LCS0 O WRITE VSYNC 3 SER_R D3_REV S D3_SPL LD1 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 M_GRA 2 2 2 2 1 1 1 NT SD23 SD21 SD18 SD16 SD13 SD9 SD7 SD5 SD3 SD2 DQM2 SDCLK SDBA0 SDQS3 SD29 F SD_D_ CLK CONTR AST LD0 RW A0 D CKIH BOOT_ MODE4 POWER _FAIL GPIO1_ VSTBY 3 CSI_D6 CSI_D9 CSI_D1 1 CSI_D1 CSI_D1 CSI_D1 0 3 5 VSYNC HSYNC DRDY0 0 CSI_D1 CSI_D1 4 2 SD_D_I FPSHIF T A2 BOOT_ GND MODE2 GND DVFS0 I2C_DA T I2C_CL CSI_VS K YNC CSI_MC CSI_D5 LK RESET_ IN CSI_H GPIO3_ SYNC 0 QVCC1 GND GND POR VPG1 NVCC1 GND DVFS1 CKIL QVCC1 QVCC1 NVCC8 NVCC8 QVCC NVCC6 NVCC6 NVCC9 24 23 P R T AD Package Information and Pinout 117 T D10 12 USBOT USB_O DTR_D DTR_D TXD2 G_STP C CE1 TE1 R NFWP 11 DSR_D DSR_D RXD2 CE1 TE1 USBOT USB_P CTS1 G_DIR WR PC_PW RON SD1_D ATA2 USBH2 _DATA1 CSPI1_ SPI_RD Y CSPI1_ CSPI1_ CSPI1_ SS1 MOSI SS0 STXD3 SCK3 SRXD3 P 10 RXD1 SCK5 G PWMO PC_RW CSPI3_ MISO H 7 USBOT G_DAT A3 USBOT G_DAT A5 CSPI2_ SCLK A GND 2 GND 3 GND 4 B GND GND C GND GND SRXD4 SRXD5 CSPI3_ MISO SFS4 SCK5 E ATA_ CS0 ATA_ DMACK ATA_ DIOR CSPI3_ MOSI F PC_ RST PWMO MCIMX31/MCIMX31L Technical Data, Rev. 4.1 G PC_VS2 PC_ BVD1 PC_ H PC_CD2 READY 6 7 CSPI2_ USBOTG_ USBOTG USBOTG SS1 DATA6 _DATA2 _DIR CSPI2_ STXD4 MISO D STXD5 5 8 9 10 11 DSR_ DTE1 12 13 14 15 16 17 18 KEY_ ROW3 KEY_ COL0 KEY_ COL5 KEY_ COL7 TDI 22 23 GND GND GND A GND GND B BOOT_ MODE1 GND GND C GND D CTS1 RXD2 USB_ OC RTS1 DSR_ DCE1 RI_ DTE1 RTS2 KEY_ ROW1 KEY_ ROW6 KEY_ COL1 KEY_ COL6 TDO WATCH SIMPD0 SCLK0 GPIO1_2 DOG_RST CSPI2_ USBOTG_ USBOTG_ SS0 DATA7 DATA1 USB_ BYP RXD1 DCD_ DCE1 DTR_ DCE2 CTS2 KEY_ ROW2 KEY_ ROW7 KEY_ COL3 TMS SJC_ MOD SRST0 CSPI2_ CSPI2_SPI USBOTG_ USBOTG_ TXD1 MOSI _RDY DATA4 CLK RI_ DCE1 DCD_ CE_ KEY_ DTE1 CONTROL ROW5 KEY_ COL2 RTCK DE SVEN0 CAPTURE BATT_ LINE CSPI2_ SS2 USBOTG_ USBOT DTR_ DATA3 G_STP DCE1 TXD2 KEY_ ROW4 KEY_ COL4 PC_ RW ATA_ CS1 SCK4 SFS5 PC_ VS1 PC_ BVD2 ATA_ DIOW CSPI3_ SCLK NVCC5 NVCC5 NVCC8 NVCC8 NVCC6 QVCC USBOTG_ NVCC5 NVCC5 NVCC6 DATA0 NVCC6 TCK GND CKIL DVFS0 POWER_ FAIL POR RESET_ IN GPIO1_3 VPG0 DVFS1 E CKIH F VPG1 GPIO3_0 G NVCC1 I2C_ CLK CSI_D4 CSI_D5 NVCC4 NVCC7 GPIO3_1 I2C_ DAT CSI_D9 CSI_ D10 CSI_D13 CSI_D15 VSYNC0 HSYNC L QVCC1 QVCC1 QVCC1 NVCC8 GND GND QVCC K USBH2_ DATA1 SD1_ CLK SD1_ CMD SD1_ DATA0 PC_ PWRON NVCC3 NVCC3 QVCC1 GND GND GND STXD3 BOOT_ MODE3 GPIO1_4 BOOT_ MODE4 VSTBY IOIS16 CSPI1_S CSPI1_ CSPI1_ CSPI1_ PI_RDY SS0 SS2 SCLK GPIO1 BOOT_ _5 MODE2 CLKSS PC_POE USBH2_ USBH2_ USBH2_ USBH2_ L CLK DIR STP NXT BOOT_ MODE0 CLKO NVCC4 NVCC7 NVCC1 PC_ WAIT GND STX0 GPIO1 _0 CSI_ MCLK PC_ CD1 GND TRSTB SRX0 COMPARE NVCC6 NVCC9 NVCC1 NVCC1 GPIO1_1 GPIO1_6 SD1_ DATA2 CSPI1_ CSPI1_ SRXD3 MOSI MISO 21 CSPI2_ USBOTG_ USBOTG_ SCLK DATA5 NXT SD1_ DATA1 N 20 KEY_ ROW0 J M 19 DTR_ DTE1 ATA_ CSPI3_ RESET SPI_RDY USB_ PWR NVCC4 NVCC7 CSI_ CSI_HSY CSI_PIX H VSYNC NC CLK CSI_D7 CSI_D8 J CSI_ D11 CSI_ D12 K SD1_ DATA3 NVCC3 NVCC3 QVCC4 GND GND GND GND GND QVCC NVCC7 CSI_D6 CSI_ D14 USBH2_ DATA0 QVCC4 QVCC4 GND GND GND GND GND GND QVCC NVCC7 DRDY0 SD_D_ IO SD_D_I CSPI1_ SS1 NC1 QVCC4 QVCC GND GND GND GND GND QVCC NVCC2 D3_ SPL READ VSYNC3 CONTRAST WRITE LCS1 N UGND UVCC D3_CLS D3_ REV PAR_ RS SER_ RS P LD8 LD11 LD3 LD2 LD1 LD0 R SD_D_ CLK LCS0 FPSHIFT M SFS3 STXD6 SFS6 NFWP NC1 NVCC10 QVCC R SRXD6 SCK6 NFRB NFCE D13 NVCC10 NVCC10 NVCC1 QVCC 0 T NFCLE NFALE NFWE NFRE D8 D4 IOQVDD NVCC1 NVCC22 NVCC21 NVCC21 NVCC21 NVCC2 0 FUSE_ VDD FVCC M_ REQUEST OE LD7 LD6 LD5 LD4 T P SCK3 GND GND GND GND GND QVCC GND QVCC QVCC QVCC NVCC2 NVCC2 NVCC2 Freescale Semiconductor U D15 D14 D12 D11 D0 NVCC22 NVCC22 NVCC2 NVCC22 NVCC21 2 V D10 D9 D6 D3 NVCC22 NVCC22 NVCC22 NVCC2 NVCC22 2 W D7 D5 D2 D1 Y GND MA10 A13 A8 A4 A0 SDBA1 A25 A24 A23 A21 A19 A17 A15 A14 DQM1 SDCKE0 CS2 AA GND GND A12 A7 A3 SDBA0 SD30 SD28 SD24 SD20 SD17 SD15 SD12 SD9 SD6 SD4 SD1 AB GND GND A11 A6 A2 SDQS3 SD29 SD26 SDQS2 SD21 SD18 SDQS1 SD13 SD10 SD7 SDQS0 AC GND GND A9 A5 A1 SD31 SD27 SD25 SD23 SD22 SD19 SD16 SD14 SD11 SD8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 These contacts are not used and must be floated by the user. A22 SVCC SGND MGND MVCC FGND CS0 M_ GRANT LD12 NC LD10 LD9 U A20 A18 A16 A10 SDCKE1 LBA RW LD16 LD15 LD14 LD13 V BCLK EB1 EB0 LD17 W CS3 CS4 ECB CS1 GND Y DQM2 RAS CAS CS5 GND GND AA SD2 DQM3 DQM0 SDWE GND GND GND AB SD5 SD3 SD0 SDCLK SDCLK GND GND GND AC 16 17 18 21 22 23 19 20 Package Information and Pinout 118 Table 71. Ball Map—19 x 19 0.8 mm Pitch 1 Product Differences 6 Product Differences The locations that provide the differences between silicon Revision 2.0, 1.2, and previous versions are given in Table 72. The differences between the MCIMX31/MCIMX31L and the MCIMX31C/MCIMX31LC are outlined in Table 73. Table 72. Silicon Differentiation by Location within the Data Sheet Item Location Silicon 1.2 and Previous Silicon 2.0 Ordering Information Section 1.2, “Ordering Information Table 1 Table 1 Feature Differences Table 1.2.1, "Feature Differences Between Mask Sets," on page 3 N/A Table 1.2.1 Operating Ranges Table 4.1, "Chip-Level Conditions," on page 10 Table 8, "Operating Ranges," on Table 8, and Table 9, "Specific page 13 Operating Ranges for Silicon Revision 2.0," on page 14 Power-up Sequences Section 4.2.1, “Powering Up Figure 2, "Power-Up Sequence for Silicon Revisions 1.2 and Previous," on page 20 Power-down Sequences Section 4.2.2, “Powering Down Figure 3, "Option 1 Power-Up Sequence (Silicon Revision 2.0)," on page 21 — — Table 73. Product Differentiation Item Location MCIMX31/MCIMX31L MCIMX31C/MCIMX31LC Device ordering information Table 1, "Ordering Information," on page 3 See Table 1. See Table 1. Thermal simulation values Table 6, "Thermal Resistance Data—14 × 14 mm Package," on page 11 and Table 7, "Thermal Resistance Data—19 × 19 mm Package," on page 11 See Table 6 and Table 7. See Table 7. Core overdrive operating voltages Table 8, "Operating Ranges," on page 13 Capability to operate in overdrive Not capable of overdrive voltages. operating voltages. Fuse_VDD Table 8, "Operating Ranges," on page 13 and Table 9, "Specific Operating Ranges for Silicon Revision 2.0," on page 14 Fusebox read Supply Voltage 1.65 min, 1.95 max. Ambient operating temperature range Table 13, "Current Consumption for 0°C min, 70°C max –40×C to 85×C, for Silicon Revision –40°C min, 85°C max 2.0," on page 17, and Table 14, "Current Consumption for 0×C to 70×C, for Silicon Revision 2.0," on page 18 In read mode, FUSE_VDD should be floated. –40°C min, 85°C max Current consumption Table 13, "Current Consumption for Typical value changes for State values –40×C to 85×C, for Silicon Revision Retention, Doze, and Wait. See 2.0," on page 17 Table. Typical value changes for State Retention, Doze, and Wait. See Table. DPLL maximum output freq range MPLL and SPLL = 400 MHz Table 31, "DPLL Specifications," on MPLL and SPLL = 532 MHz page 37 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 119 Product Documentation Table 73. Product Differentiation (continued) Item Location MCIMX31/MCIMX31L MCIMX31C/MCIMX31LC GPIO maximum Table 15, "GPIO DC Electrical input current (100 kΩ Parameters," on page 22 PU) VI = 0, IIN = 25 μA VI = NVCC, IIN = 0.1 μA N/A N/A Core operating speed Table 8, "Operating Ranges," on page 13 532 MHz 400 MHz Package Table 70, "Ball Map—14 x 14 0.5 mm Pitch," on page 117 and Table 71, "Ball Map—19 x 19 0.8 mm Pitch," on page 118 MAPBGA Packages 457 14 x 14 mm, 0.5 mm Pitch 473 19 x 19 mm, 0.8 mm Pitch MAPBGA Package 473 19 x 19 mm, 0.8 mm Pitch Pin Assignment Table 66, "14 x 14 BGA Signal ID by MAPBGA Packages Ball Grid Location," on page 107 and 457 14 x 14 mm, 0.5 mm Pitch Table 69, "19 x 19 BGA Signal ID by 473 19 x 19 mm, 0.8 mm Pitch Ball Grid Location," on page 113 MAPBGA Package 473 19 x 19 mm, 0.8 mm Pitch 7 Product Documentation This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. MCIMX31 Product Brief (order number MCIMX31PB) MCIMX31 Reference Manual (order number MCIMX31RM) MCIMX31 Chip Errata (order number MCIMX31CE) The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. ARM Ltd. documentation is available from http://www.arm.com. 8 Revision History Table 74 summarizes revisions to this document since the release of Rev. 3.4. Table 74. Revision History Rev. 4 Location Revision Figure 87, Table 73 Updated. 4.1 Table 1, "Ordering Information," on page 3 Added note about JTAG compliance. 4.1 Section 1.2.1/3 Updated with new operating frequencies 4.1 Table 8, "Operating Ranges," on page 13 Added new operating frequencies MCIMX31/MCIMX31L Technical Data, Rev. 4.1 120 Freescale Semiconductor Revision History This page left intentionally blank MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 121 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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